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spi: Add A20 pinmux configuration

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A20 (as does A10) uses pins 0,1,2 and 23 in bank C
for SPI 0.

Signed-off-by: Priit Laes <priit.laes@paf.com>
This commit is contained in:
Priit Laes 2019-01-08 16:55:29 +02:00
parent 5325533ce7
commit 5831d54aa9
1 changed files with 6 additions and 0 deletions
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6
fel-spiflash.c
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@ -160,6 +160,12 @@ static bool spi0_init(feldev_handle *dev)
gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0);
gpio_set_cfgpin(dev, PC, 3, SUNXI_GPC_SPI0);
break;
case 0x1651: /* Allwinner A20 */
gpio_set_cfgpin(dev, PC, 0, SUNXI_GPC_SPI0);
gpio_set_cfgpin(dev, PC, 1, SUNXI_GPC_SPI0);
gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0);
gpio_set_cfgpin(dev, PC, 23, SUNXI_GPC_SPI0);
break;
case 0x1689: /* Allwinner A64 */
gpio_set_cfgpin(dev, PC, 0, SUN50I_GPC_SPI0);
gpio_set_cfgpin(dev, PC, 1, SUN50I_GPC_SPI0);