From 5831d54aa925e3a9ff31b2e06c817da305092ae4 Mon Sep 17 00:00:00 2001 From: Priit Laes Date: Tue, 8 Jan 2019 16:55:29 +0200 Subject: [PATCH] spi: Add A20 pinmux configuration A20 (as does A10) uses pins 0,1,2 and 23 in bank C for SPI 0. Signed-off-by: Priit Laes --- fel-spiflash.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/fel-spiflash.c b/fel-spiflash.c index 0039b06..2cc4f47 100644 --- a/fel-spiflash.c +++ b/fel-spiflash.c @@ -160,6 +160,12 @@ static bool spi0_init(feldev_handle *dev) gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0); gpio_set_cfgpin(dev, PC, 3, SUNXI_GPC_SPI0); break; + case 0x1651: /* Allwinner A20 */ + gpio_set_cfgpin(dev, PC, 0, SUNXI_GPC_SPI0); + gpio_set_cfgpin(dev, PC, 1, SUNXI_GPC_SPI0); + gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0); + gpio_set_cfgpin(dev, PC, 23, SUNXI_GPC_SPI0); + break; case 0x1689: /* Allwinner A64 */ gpio_set_cfgpin(dev, PC, 0, SUN50I_GPC_SPI0); gpio_set_cfgpin(dev, PC, 1, SUN50I_GPC_SPI0);