53 lines
2.0 KiB
Diff
53 lines
2.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Martin Blumenstingl <[email protected]>
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Date: Mon, 31 Jan 2022 23:02:59 +0100
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Subject: drm/meson: Skip VIU_OSD1_CTRL_STAT2 alpha replace value
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initialization
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The VIU_OSD1_CTRL_STAT2 and VIU_OSD2_CTRL_STAT2 registers on
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Meson8/Meson8b/Meson8m2 don't have the following bits:
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- replaced_alpha_en in bit [14]
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- replaced_alpha in bits [13:6]
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Don't initialize the replaced_alpha register bits in VIU_OSD1_CTRL_STAT2
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on Meson8/Meson8b/Meson8m2 because they are not implemented on those
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SoCs.
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Signed-off-by: Martin Blumenstingl <[email protected]>
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---
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drivers/gpu/drm/meson/meson_viu.c | 18 ++++++----
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1 file changed, 11 insertions(+), 7 deletions(-)
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diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
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index 111111111111..222222222222 100644
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--- a/drivers/gpu/drm/meson/meson_viu.c
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+++ b/drivers/gpu/drm/meson/meson_viu.c
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@@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv)
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
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writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
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- /* Set OSD alpha replace value */
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- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
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- 0xff << OSD_REPLACE_SHIFT,
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- priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
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- 0xff << OSD_REPLACE_SHIFT,
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- priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
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+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) &&
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+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) &&
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+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) {
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+ /* Set OSD alpha replace value */
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+ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
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+ 0xff << OSD_REPLACE_SHIFT,
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+ priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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+ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
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+ 0xff << OSD_REPLACE_SHIFT,
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+ priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
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+ }
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/* Disable VD1 AFBC */
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/* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/
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--
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Armbian
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