From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 31 Jan 2022 23:02:59 +0100 Subject: drm/meson: Skip VIU_OSD1_CTRL_STAT2 alpha replace value initialization The VIU_OSD1_CTRL_STAT2 and VIU_OSD2_CTRL_STAT2 registers on Meson8/Meson8b/Meson8m2 don't have the following bits: - replaced_alpha_en in bit [14] - replaced_alpha in bits [13:6] Don't initialize the replaced_alpha register bits in VIU_OSD1_CTRL_STAT2 on Meson8/Meson8b/Meson8m2 because they are not implemented on those SoCs. Signed-off-by: Martin Blumenstingl --- drivers/gpu/drm/meson/meson_viu.c | 18 ++++++---- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c index 111111111111..222222222222 100644 --- a/drivers/gpu/drm/meson/meson_viu.c +++ b/drivers/gpu/drm/meson/meson_viu.c @@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv) writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); - /* Set OSD alpha replace value */ - writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, - 0xff << OSD_REPLACE_SHIFT, - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); - writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, - 0xff << OSD_REPLACE_SHIFT, - priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { + /* Set OSD alpha replace value */ + writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, + 0xff << OSD_REPLACE_SHIFT, + priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); + writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, + 0xff << OSD_REPLACE_SHIFT, + priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); + } /* Disable VD1 AFBC */ /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/ -- Armbian