805 lines
21 KiB
C
805 lines
21 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* include/amlogic/aml_lcd_vout.h
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*
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* Copyright (C) 2020 Amlogic, Inc. All rights reserved.
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*
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*/
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#ifndef INC_AML_LCD_VOUT_H
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#define INC_AML_LCD_VOUT_H
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#include <common.h>
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#include <linux/list.h>
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#include <amlogic/aml_lcd_timing.h>
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#include <amlogic/aml_lcd_cus_ctrl.h>
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#ifdef CONFIG_AML_LCD_TCON
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#include <amlogic/aml_lcd_tcon_data.h>
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#endif
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/* **********************************
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* debug print define
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* ********************************** */
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//#define LCD_DEBUG_INFO
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extern unsigned int lcd_debug_print_flag;
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#define LCDPR(fmt, args...) printf("lcd: "fmt"", ## args)
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#define LCDERR(fmt, args...) printf("lcd: error: "fmt"", ## args)
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#define PR_BUF_MAX (4 * 1024)
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/* **********************************
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* clk parameter bit define
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* pll_ctrl, div_ctrl, clk_ctrl
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* ********************************** */
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/* ******** pll_ctrl ******** */
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#define PLL_CTRL_OD3 20 /* [21:20] */
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#define PLL_CTRL_OD2 18 /* [19:18] */
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#define PLL_CTRL_OD1 16 /* [17:16] */
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#define PLL_CTRL_N 9 /* [13:9] */
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#define PLL_CTRL_M 0 /* [8:0] */
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/* ******** div_ctrl ******** */
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#define DIV_CTRL_EDP_DIV1 24 /* [26:24] */
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#define DIV_CTRL_EDP_DIV0 20 /* [23:20] */
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#define DIV_CTRL_DIV_SEL 8 /* [15:8] */
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#define DIV_CTRL_XD 0 /* [7:0] */
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/* ******** clk_ctrl ******** */
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#define CLK_CTRL_LEVEL 28 /* [30:28] */
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#define CLK_CTRL_FRAC_SHIFT 24 /* [24] */
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#define CLK_CTRL_FRAC 0 /* [23:0] */
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/* **********************************
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* VENC to TCON sync delay
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* ********************************** */
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#define TTL_DELAY 13
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#define PRE_DE_DELAY 8
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#define LCD_PINMUX_END 0xff
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#define LCD_PINMUX_NUM 15
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/* **********************************
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* global control define
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* ********************************** */
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enum lcd_mode_e {
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LCD_MODE_TV = 0,
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LCD_MODE_TABLET,
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LCD_MODE_MAX,
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};
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enum lcd_chip_e {
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LCD_CHIP_GXTVBB = 0,
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LCD_CHIP_GXL, /* 1 */
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LCD_CHIP_GXM, /* 2 */
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LCD_CHIP_TXL, /* 3 */
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LCD_CHIP_TXLX, /* 4 */
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LCD_CHIP_AXG, /* 5 */
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LCD_CHIP_TXHD, /* 6 */
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LCD_CHIP_G12A, /* 7 */
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LCD_CHIP_G12B, /* 8 */
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LCD_CHIP_TL1, /* 9 */
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LCD_CHIP_SM1, /* 10 */
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LCD_CHIP_TM2, /* 11 */
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LCD_CHIP_T5, /* 12 */
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LCD_CHIP_T5D, /* 13 */
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LCD_CHIP_T5W, /* 14 */
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LCD_CHIP_MAX,
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};
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enum lcd_type_e {
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LCD_TTL = 0,
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LCD_LVDS,
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LCD_VBYONE,
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LCD_MIPI,
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LCD_MLVDS,
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LCD_P2P,
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LCD_TYPE_MAX,
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};
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#define MOD_LEN_MAX 48
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struct lcd_basic_s {
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char model_name[MOD_LEN_MAX];
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enum lcd_type_e lcd_type;
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unsigned char lcd_bits;
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unsigned char config_check;
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unsigned short screen_width; /* screen physical width in "mm" unit */
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unsigned short screen_height; /* screen physical height in "mm" unit */
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};
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#define LCD_CLK_FRAC_UPDATE (1 << 0)
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#define LCD_CLK_PLL_CHANGE (1 << 1)
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#define LCD_CLK_PLL_RESET (1 << 2)
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struct lcd_timing_s {
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struct lcd_detail_timing_s dft_timing; //panel parameter probe stage
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struct lcd_detail_timing_s base_timing; //panel parameter init stage
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struct lcd_detail_timing_s act_timing; //panel parameter actual stage
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unsigned char pll_flag;
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unsigned char clk_change; /* internal used */
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unsigned int ss_level;
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unsigned int ss_freq;
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unsigned int ss_mode;
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unsigned int enc_clk;
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unsigned long long bit_rate; /* Hz */
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unsigned int pll_ctrl; /* pll settings */
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unsigned int div_ctrl; /* divider settings */
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unsigned int clk_ctrl; /* clock settings */
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unsigned int hstart;
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unsigned int hend;
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unsigned int vstart;
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unsigned int vend;
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unsigned char pre_de_h;
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unsigned char pre_de_v;
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unsigned short de_hs_addr;
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unsigned short de_he_addr;
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unsigned short de_vs_addr;
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unsigned short de_ve_addr;
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unsigned short hs_hs_addr;
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unsigned short hs_he_addr;
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unsigned short hs_vs_addr;
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unsigned short hs_ve_addr;
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unsigned short vs_hs_addr;
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unsigned short vs_he_addr;
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unsigned short vs_vs_addr;
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unsigned short vs_ve_addr;
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unsigned short pre_h_de_start;
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unsigned short pre_h_de_end;
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unsigned short pre_v_de_start;
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unsigned short pre_v_de_end;
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unsigned short pre_hso_start;
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unsigned short pre_hso_end;
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unsigned short pre_vso_hstart;
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unsigned short pre_vso_hend;
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unsigned short pre_vso_start;
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unsigned short pre_vso_end;
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};
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struct lcd_disp_tmg_req_s {
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unsigned int alert_level;//0:disable, 1:warning, 2:fatal err
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unsigned int hswbp_vid;
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unsigned int hfp_vid;
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unsigned int vswbp_vid;
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unsigned int vfp_vid;
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};
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struct ttl_config_s {
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unsigned int clk_pol;
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unsigned int sync_valid; /* [1]DE, [0]hvsync */
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unsigned int swap_ctrl; /* [1]rb swap, [0]bit swap */
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};
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#define LVDS_PHY_VSWING_DFT 3
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#define LVDS_PHY_PREEM_DFT 0
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#define LVDS_PHY_CLK_VSWING_DFT 0
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#define LVDS_PHY_CLK_PREEM_DFT 0
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struct lvds_config_s {
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unsigned int lvds_repack;
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unsigned int dual_port;
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unsigned int pn_swap;
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unsigned int port_swap;
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unsigned int lane_reverse;
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unsigned int port_sel;
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unsigned int phy_vswing;
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unsigned int phy_preem;
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unsigned int phy_clk_vswing;
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unsigned int phy_clk_preem;
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};
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#define VX1_PHY_VSWING_DFT 3
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#define VX1_PHY_PREEM_DFT 0
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#define VX1_PWR_ON_RESET_DLY_DFT 500 /* 500ms */
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#define VX1_HPD_DATA_DELAY_DFT 10 /* 10ms */
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#define VX1_CDR_TRAINING_HOLD_DFT 200 /* 200ms */
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#define VX1_SW_FILTER_TIME_DFT 10 /* 10*100us=1ms */
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#define VX1_SW_FILTER_CNT_DFT 6
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#define VX1_SW_FILTER_RETRY_CNT_DFT 2
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#define VX1_SW_FILTER_RETRY_DLY_DFT 100 /* 100ms */
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#define VX1_SW_CDR_DET_TIME_DFT 20 /* 20us*100=2ms */
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#define VX1_SW_CDR_DET_CNT_DFT 100
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#define VX1_SW_CDR_TIMEOUT_CNT_DFT 100
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struct vbyone_config_s {
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unsigned int lane_count;
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unsigned int region_num;
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unsigned int byte_mode;
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unsigned int color_fmt;
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unsigned int phy_div;
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unsigned int phy_vswing; /*[5:4]:ext_pullup, [3:0]vswing*/
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unsigned int phy_preem;
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unsigned int ctrl_flag;
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/* bit[0]:power_on_reset_en
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bit[1]:hpd_data_delay_en
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bit[2]:cdr_training_hold_en
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bit[3]:hw_filter_en
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bit[5:4]:sw_filter */
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/* ctrl timing */
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unsigned int power_on_reset_delay; /* ms */
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unsigned int hpd_data_delay; /* ms */
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unsigned int cdr_training_hold; /* ms */
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/* hw filter */
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unsigned int hpd_hw_filter_time; /* ms */
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unsigned int hpd_hw_filter_cnt;
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unsigned int lockn_hw_filter_time; /* ms */
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unsigned int lockn_hw_filter_cnt;
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/* sw filter */
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unsigned int vx1_sw_filter_en; /* 0=disable, 1=sw_filter, 2=sw_filter with sw_reset */
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unsigned int vx1_sw_filter_time; /* 100us base */
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unsigned int vx1_sw_filter_cnt;
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unsigned int vx1_sw_filter_retry_cnt;
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unsigned int vx1_sw_filter_retry_delay; /* ms base */
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unsigned int vx1_sw_cdr_detect_time; /* us base * 100 times, must cover tcon lockn pulse */
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unsigned int vx1_sw_cdr_detect_cnt;
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unsigned int vx1_sw_cdr_timeout_cnt;
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/* hw filter */
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unsigned int hw_filter_time;
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unsigned int hw_filter_cnt;
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};
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/* mipi-dsi config */
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/* Operation mode parameters */
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#define OPERATION_VIDEO_MODE 0
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#define OPERATION_COMMAND_MODE 1
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#define SYNC_PULSE 0x0
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#define SYNC_EVENT 0x1
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#define BURST_MODE 0x2
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/* command config */
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#define DSI_CMD_SIZE_INDEX 1 /* byte[1] */
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#define DSI_GPIO_INDEX 2 /* byte[2] */
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#define DSI_INIT_ON_MAX 100
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#define DSI_INIT_OFF_MAX 30
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struct dsi_config_s {
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unsigned char lane_num;
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unsigned int bit_rate_max;
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unsigned int bit_rate_min;
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unsigned int clk_factor; /* bit_rate/pclk */
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unsigned int factor_numerator;
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unsigned int factor_denominator; /* 100 */
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unsigned char operation_mode_init; /* 0=video mode, 1=command mode */
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unsigned char operation_mode_display; /* 0=video mode, 1=command mode */
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unsigned char video_mode_type; /* 0=sync_pulse, 1=sync_event, 2=burst */
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unsigned char clk_always_hs; /* 0=disable, 1=enable */
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unsigned char phy_switch; /* 0=auto, 1=standard, 2=slow */
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unsigned int venc_data_width;
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unsigned int dpi_data_format;
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unsigned char *dsi_init_on;
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unsigned char *dsi_init_off;
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unsigned char extern_init;
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unsigned char check_en;
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unsigned char check_reg;
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unsigned char check_cnt;
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unsigned char check_state;
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};
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struct mlvds_config_s {
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unsigned int channel_num;
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unsigned int channel_sel0;
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unsigned int channel_sel1;
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unsigned int clk_phase; /* [14:13]=clk01_sel,
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* [12]=data bypass buffer,
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* [11:8]=pi2, [7:4]=pi1, [3:0]=pi0
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*/
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unsigned int pn_swap;
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unsigned int bit_swap; /* MSB/LSB reverse */
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unsigned int phy_vswing;
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unsigned int phy_preem;
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/* internal used */
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unsigned int pi_clk_sel; /* bit[9:0] */
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};
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enum p2p_type_e {
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P2P_CEDS = 0,
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P2P_CMPI,
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P2P_ISP,
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P2P_EPI,
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P2P_CHPI = 0x10, /* low common mode */
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P2P_CSPI,
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P2P_USIT,
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P2P_MAX,
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};
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struct p2p_config_s {
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unsigned int p2p_type; /* bit[4:0] for type, bit[5] for vcm flag */
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unsigned int lane_num;
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unsigned int channel_sel0;
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unsigned int channel_sel1;
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unsigned int pn_swap;
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unsigned int bit_swap; /* MSB/LSB reverse */
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unsigned int phy_vswing;
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unsigned int phy_preem;
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};
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#define PHY_BIT_VSWING (1 << 0)
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#define PHY_BIT_VCM (1 << 1)
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#define PHY_BIT_REF_BIAS (1 << 2)
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#define PHY_BIT_ODT (1 << 3)
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#define PHY_BIT_CV_MODE (1 << 4)
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#define PHY_BIT_LANE_PREEM (1 << 12)
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#define PHY_BIT_LAEN_AMP (1 << 13)
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#define PHY_BIT_LANE_SEL (1 << 14)
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#define PHY_PHASE_0 0
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#define PHY_PHASE_A 1
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#define PHY_PHASE_B 2
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struct phy_lane_s {
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unsigned int preem; //flag bit[12]
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unsigned int amp; //flag bit[13]
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unsigned int sel; //flag bit[14]
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unsigned char phase_sel;
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};
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#define PHY_CMODE 0
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#define PHY_VMODE 1
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#define CH_LANE_MAX 32
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struct phy_config_s {
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unsigned int flag;
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unsigned int vswing; //flag bit[0]
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unsigned int vcm; //flag bit[1]
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unsigned int ref_bias; //flag bit[2]
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unsigned int odt; //flag bit[3]
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unsigned int cv_mode; //flag bit[4] //val:0=cm,1=vm
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unsigned int weakly_pull_down;
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struct phy_lane_s lane[CH_LANE_MAX];
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unsigned int lane_num;
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unsigned int ch_swap0;
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unsigned int ch_swap1;
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unsigned int vswing_level;
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unsigned int ext_pullup;
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unsigned int preem_level;
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unsigned int low_common_mode;
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unsigned int clk_phase;
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unsigned int ckdi;
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unsigned int lane_valid; //(valid & mask)<<offset
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unsigned int lane_offset;
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unsigned int lane_mask; //local mask for lane range
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};
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struct lcd_ctrl_config_s {
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struct ttl_config_s *ttl_config;
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struct lvds_config_s *lvds_config;
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struct vbyone_config_s *vbyone_config;
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struct dsi_config_s *mipi_config;
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struct mlvds_config_s *mlvds_config;
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struct p2p_config_s *p2p_config;
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struct phy_config_s *phy_cfg;
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};
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/* **********************************
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* power control define
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* ********************************** */
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enum lcd_power_type_e {
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LCD_POWER_TYPE_CPU = 0,
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LCD_POWER_TYPE_PMU, /* 1 */
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LCD_POWER_TYPE_SIGNAL, /* 2 */
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LCD_POWER_TYPE_EXTERN, /* 3 */
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LCD_POWER_TYPE_WAIT_GPIO, /* 4 */
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LCD_POWER_TYPE_CLK_SS, /* 5 */
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LCD_POWER_TYPE_TCON_SPI_DATA_LOAD, /* 6 */
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LCD_POWER_TYPE_OFF_DELAY = 0xfd,
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LCD_POWER_TYPE_MAX,
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};
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#define LCD_POWER_TYPE_END 0xff
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enum lcd_pmu_gpio_e {
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LCD_PMU_GPIO0 = 0,
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LCD_PMU_GPIO1,
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LCD_PMU_GPIO2,
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LCD_PMU_GPIO3,
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LCD_PMU_GPIO4,
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LCD_PMU_GPIO_MAX,
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};
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#define LCD_CLK_SS_BIT_FREQ 0
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#define LCD_CLK_SS_BIT_MODE 4
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#define LCD_GPIO_MAX 0xff
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#define LCD_GPIO_OUTPUT_LOW 0
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#define LCD_GPIO_OUTPUT_HIGH 1
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#define LCD_GPIO_INPUT 2
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/* Power Control */
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#define LCD_CPU_GPIO_NUM_MAX 10
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#define LCD_CPU_GPIO_NAME_MAX 10
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#define LCD_PMU_GPIO_NUM_MAX 3
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#define LCD_PWR_STEP_MAX 15
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struct lcd_power_step_s {
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unsigned char type;
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int index; /* point to lcd_cpu_gpio_s or lcd_pmu_gpio_s or lcd_extern */
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unsigned short value;
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unsigned short delay;
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};
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struct lcd_power_ctrl_s {
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char cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
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int *pmu_gpio;
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struct lcd_power_step_s power_on_step[LCD_PWR_STEP_MAX];
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struct lcd_power_step_s power_off_step[LCD_PWR_STEP_MAX];
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};
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#define LCD_PINMX_MAX 10
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#define BL_PINMUX_MAX 20
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#define LCD_PINMUX_NAME_LEN_MAX 30
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struct lcd_pinmux_ctrl_s {
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char *name;
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unsigned int pinmux_set[LCD_PINMUX_NUM][2];
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unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
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};
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#define LCD_DURATION_MAX 8
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struct lcd_duration_s {
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unsigned int frame_rate;
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unsigned int duration_num;
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unsigned int duration_den;
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unsigned int frac;
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};
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struct lcd_vmode_info_s {
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char name[32];
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unsigned int width;
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unsigned int height;
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unsigned int base_fr;
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unsigned int duration_index;
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unsigned int duration_cnt;
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struct lcd_duration_s duration[LCD_DURATION_MAX];
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struct lcd_detail_timing_s *dft_timing;
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};
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struct lcd_vmode_list_s {
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struct lcd_vmode_info_s *info;
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struct lcd_vmode_list_s *next;
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};
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struct lcd_vmode_mgr_s {
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unsigned int vmode_cnt;
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struct lcd_vmode_list_s *vmode_list_header;
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struct lcd_vmode_info_s *cur_vmode_info;
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struct lcd_vmode_info_s *next_vmode_info;
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};
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struct cus_ctrl_config_s {
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unsigned int ctrl_en;
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unsigned int ctrl_cnt;
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unsigned int timing_cnt;
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unsigned int active_timing_type;
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unsigned char timing_switch_flag;
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unsigned char timing_ctrl_valid;
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struct lcd_cus_ctrl_attr_config_s *attr_config;
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struct lcd_cus_ctrl_attr_config_s *cur_timing_attr;
|
|
};
|
|
|
|
#define LCD_ENABLE_RETRY_MAX 3
|
|
#define CUS_PINMUX_NAME_MAX 44
|
|
#define CUS_PINMUX_MODE_MODEL_NAME 1
|
|
#define CUS_PINMUX_MODE_CUSTOM_NAME 2 //not support
|
|
struct lcd_config_s {
|
|
unsigned char lcd_mode;
|
|
unsigned char lcd_key_valid;
|
|
unsigned char lcd_clk_path; /* 0=hpll, 1=gp0_pll */
|
|
unsigned char retry_enable_flag;
|
|
unsigned char retry_enable_cnt;
|
|
unsigned int output_vmode;
|
|
unsigned int backlight_index;
|
|
struct lcd_basic_s lcd_basic;
|
|
struct lcd_timing_s lcd_timing;
|
|
struct lcd_ctrl_config_s lcd_control;
|
|
struct lcd_power_ctrl_s *lcd_power;
|
|
struct lcd_duration_s *std_duration;
|
|
unsigned char pinctrl_ver;
|
|
unsigned char fr_auto_cus; //0=follow global setting, 0xff=disable
|
|
unsigned char fr_auto_flag; //final fr_auto policy
|
|
struct cus_ctrl_config_s cus_ctrl;
|
|
struct lcd_pinmux_ctrl_s *lcd_pinmux;
|
|
unsigned int pinmux_set[LCD_PINMUX_NUM][2];
|
|
unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
|
|
char cus_pinmux_name[CUS_PINMUX_NAME_MAX];
|
|
};
|
|
|
|
extern struct lcd_config_s lcd_config_dft;
|
|
|
|
/* ==============backlight control config================== */
|
|
enum bl_ctrl_method_e {
|
|
BL_CTRL_GPIO = 0,
|
|
BL_CTRL_PWM,
|
|
BL_CTRL_PWM_COMBO,
|
|
BL_CTRL_LOCAL_DIMMING,
|
|
BL_CTRL_EXTERN,
|
|
BL_CTRL_MAX,
|
|
};
|
|
|
|
enum bl_pwm_method_e {
|
|
BL_PWM_NEGATIVE = 0,
|
|
BL_PWM_POSITIVE,
|
|
BL_PWM_METHOD_MAX,
|
|
};
|
|
|
|
enum bl_pwm_port_e {
|
|
BL_PWM_A = 0,
|
|
BL_PWM_B,
|
|
BL_PWM_C,
|
|
BL_PWM_D,
|
|
BL_PWM_E,
|
|
BL_PWM_F,
|
|
BL_PWM_G,
|
|
BL_PWM_H,
|
|
BL_PWM_I,
|
|
BL_PWM_J,
|
|
BL_PWM_AO_A = 0x50,
|
|
BL_PWM_AO_B,
|
|
BL_PWM_AO_C,
|
|
BL_PWM_AO_D,
|
|
BL_PWM_AO_E,
|
|
BL_PWM_AO_F,
|
|
BL_PWM_AO_G,
|
|
BL_PWM_AO_H,
|
|
BL_PWM_VS = 0xa0,
|
|
BL_PWM_MAX = 0xff,
|
|
};
|
|
|
|
enum bl_off_policy_e {
|
|
BL_OFF_POLICY_NONE = 0,
|
|
BL_OFF_POLICY_ALWAYS,
|
|
BL_OFF_POLICY_ONCE,
|
|
BL_OFF_POLICY_MAX,
|
|
};
|
|
|
|
#define XTAL_FREQ_HZ (24*1000*1000) /* 24M in HZ */
|
|
#define XTAL_HALF_FREQ_HZ (24*1000*500) /* 24M/2 in HZ */
|
|
|
|
#define BL_FREQ_DEFAULT 1000 /* unit: HZ */
|
|
#define BL_FREQ_VS_DEFAULT 2 /* multiple 2 of vfreq */
|
|
|
|
#define BL_LEVEL_FULL_SCALE 4095
|
|
#define BL_PWM_DUTY_FULL_SCALE 4095
|
|
|
|
#define PWM_MAP_RESCALING 0
|
|
#define PWM_MAP_NORMALIZATION 1
|
|
|
|
#define BL_GPIO_NUM_MAX 5
|
|
|
|
struct bl_pwm_config_s {
|
|
unsigned int index;
|
|
enum bl_pwm_method_e pwm_method;
|
|
enum bl_pwm_port_e pwm_port;
|
|
int level_max;
|
|
int level_min;
|
|
|
|
unsigned int pwm_freq; /* pwm_vs: 1~4(vfreq), pwm: freq(unit: Hz) */
|
|
unsigned int pwm_duty; /* 12bit */
|
|
unsigned int pwm_duty_dft; /* 12bit */
|
|
unsigned int pwm_duty_save; /* 12bit */
|
|
unsigned int pwm_duty_max; /* 12bit */
|
|
unsigned int pwm_duty_min; /* 12bit */
|
|
unsigned int pwm_phase;
|
|
|
|
unsigned int pwm_cnt; /* internal used for pwm control */
|
|
unsigned int pwm_pre_div; /* internal used for pwm control */
|
|
unsigned int pwm_value; /* internal used for pwm control */
|
|
|
|
unsigned int pwm_gpio;
|
|
unsigned int pwm_gpio_off;
|
|
unsigned int pinmux_flag;
|
|
unsigned int pinmux_set[LCD_PINMUX_NUM][2];
|
|
unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
|
|
};
|
|
|
|
struct bl_config_s {
|
|
unsigned char bl_key_valid;
|
|
char name[20];
|
|
int level_default;
|
|
int level_min;
|
|
int level_max;
|
|
int level;
|
|
|
|
int level_mid;
|
|
int level_mid_mapping;
|
|
|
|
int level_in_scale;
|
|
unsigned int pwm_duty_in_scale;
|
|
unsigned int pwm_mapping_method;
|
|
|
|
enum bl_ctrl_method_e method;
|
|
unsigned int en_gpio;
|
|
unsigned int en_gpio_on;
|
|
unsigned int en_gpio_off;
|
|
unsigned short power_on_delay;
|
|
unsigned short power_off_delay;
|
|
unsigned int en_sequence_reverse;
|
|
|
|
struct bl_pwm_config_s *bl_pwm;
|
|
struct bl_pwm_config_s *bl_pwm_combo0;
|
|
struct bl_pwm_config_s *bl_pwm_combo1;
|
|
unsigned int pwm_on_delay;
|
|
unsigned int pwm_off_delay;
|
|
|
|
char gpio_name[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
|
|
unsigned char pinctrl_ver;
|
|
struct lcd_pinmux_ctrl_s *bl_pinmux;
|
|
unsigned int pinmux_set[LCD_PINMUX_NUM][2];
|
|
unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
|
|
int bl_extern_index;
|
|
};
|
|
|
|
extern struct bl_config_s bl_config_dft;
|
|
|
|
#define LCD_INIT_LEVEL_NORMAL 0
|
|
#define LCD_INIT_LEVEL_PWR_OFF 1
|
|
#define LCD_INIT_LEVEL_KERNEL_ON 2
|
|
#define LCD_INIT_LEVEL_KERNEL_OFF 3
|
|
#define LCD_INIT_LEVEL_PREBOOT 4
|
|
/*
|
|
*bit[31:24]: frame_rate
|
|
*bit[23:20]: reserved, do not use
|
|
*bit[19:18]: lcd_init_level
|
|
*bit[17]: reserved
|
|
*bit[16]: reserved
|
|
*bit[15:8]: advanced flag(p2p_type when lcd_type=p2p)
|
|
*bit[7:4]: lcd bits
|
|
*bit[3:0]: lcd_type
|
|
*/
|
|
struct lcd_boot_ctrl_s {
|
|
unsigned char lcd_type;
|
|
unsigned char lcd_bits;
|
|
unsigned char advanced_flag;
|
|
unsigned char reserved;
|
|
unsigned char init_level;
|
|
unsigned char frame_rate;
|
|
};
|
|
|
|
/*
|
|
*bit[31:30]: lcd mode(0=normal, 1=tv; 2=tablet, 3=TBD)
|
|
*bit[29:28]: lcd debug para source(0=normal, 1=dts, 2=unifykey,
|
|
* 3=bsp for uboot)
|
|
*bit[27:20]: reserved
|
|
*bit[19:16]: lcd test pattern
|
|
*bit[15:0]: lcd debug print flag
|
|
*/
|
|
struct lcd_debug_ctrl_s {
|
|
unsigned short debug_print_flag;
|
|
unsigned char debug_test_pattern;
|
|
unsigned char debug_para_source;
|
|
unsigned char debug_lcd_mode;
|
|
};
|
|
|
|
/* ==============lcd driver================== */
|
|
struct aml_lcd_drv_s {
|
|
char version[15];
|
|
enum lcd_chip_e chip_type;
|
|
char rev_type;
|
|
unsigned char probe_done;
|
|
unsigned char lcd_status;
|
|
unsigned char config_check_glb;
|
|
unsigned char config_check_en;
|
|
|
|
struct lcd_config_s *lcd_config;
|
|
struct bl_config_s *bl_config;
|
|
struct lcd_disp_tmg_req_s disp_req;
|
|
struct lcd_vmode_mgr_s vmode_mgr;
|
|
|
|
int (*outputmode_check)(char *mode);
|
|
int (*config_valid)(char *mode);
|
|
void (*driver_init_pre)(void);
|
|
int (*driver_init)(void);
|
|
void (*driver_disable)(void);
|
|
void (*list_support_mode)(void);
|
|
int (*lcd_probe)(void);
|
|
int (*lcd_outputmode_check)(char *mode, unsigned int frac);
|
|
void (*lcd_prepare)(char *mode, unsigned int frac);
|
|
void (*lcd_enable)(char *mode, unsigned int frac);
|
|
void (*lcd_disable)(void);
|
|
void (*lcd_set_ss)(unsigned int level, unsigned int freq, unsigned int mode);
|
|
void (*lcd_get_ss)(void);
|
|
void (*lcd_test)(int num);
|
|
void (*lcd_config_check)(void);
|
|
int (*lcd_prbs)(unsigned int s, unsigned int mode_flag);
|
|
void (*lcd_clk)(void);
|
|
void (*lcd_info)(void);
|
|
void (*lcd_reg)(void);
|
|
void (*lcd_tcon_reg_print)(void);
|
|
void (*lcd_tcon_table_print)(void);
|
|
void (*lcd_tcon_vac_print)(void);
|
|
void (*lcd_tcon_demura_print)(void);
|
|
void (*lcd_tcon_acc_print)(void);
|
|
void (*lcd_tcon_data_print)(unsigned char index);
|
|
void (*lcd_tcon_spi_print)(void);
|
|
int (*tcon_forbidden_check)(void);
|
|
int (*lcd_tcon_spi_data_load)(void);
|
|
unsigned int (*lcd_tcon_reg_read)(unsigned int addr, unsigned int flag);
|
|
void (*lcd_tcon_reg_write)(unsigned int addr, unsigned int val, unsigned int flag);
|
|
unsigned int (*lcd_tcon_table_read)(unsigned int addr);
|
|
unsigned int (*lcd_tcon_table_write)(unsigned int addr, unsigned int val);
|
|
int (*tcon_mem_tee_protect)(int mem_flag, int protect_en);
|
|
void (*lcd_vbyone_rst)(void);
|
|
int (*lcd_vbyone_cdr)(void);
|
|
int (*lcd_vbyone_lock)(void);
|
|
void (*bl_on)(void);
|
|
void (*bl_off)(void);
|
|
void (*set_bl_level)(int level);
|
|
int (*get_bl_level)(void);
|
|
void (*bl_config_print)(void);
|
|
int unifykey_test_flag;
|
|
void (*unifykey_dump)(unsigned int);
|
|
void (*debug_print_set)(unsigned int flag);
|
|
|
|
/* for factory test */
|
|
struct lcd_power_step_s *factory_lcd_power_on_step;
|
|
int factory_bl_power_on_delay;
|
|
};
|
|
|
|
extern void lcd_config_bsp_init(void);
|
|
|
|
extern struct aml_lcd_drv_s *aml_lcd_get_driver(void);
|
|
|
|
extern int lcd_probe(void);
|
|
|
|
#ifdef CONFIG_CMD_INI
|
|
int model_file_is_exist(const char *file_path);
|
|
int model_get_file_size(const char *file_path);
|
|
int model_read_file(const char *file_path, unsigned char *data_buf, int buf_size);
|
|
unsigned char *model_read_file_to_buffer(const char *file_path, int *buf_size);
|
|
unsigned char *model_read_bin_to_buffer(const char *file_path, int *buf_size);
|
|
unsigned int CalCRC32(unsigned int crc, const unsigned char *ptr, int buf_len);
|
|
#else
|
|
static inline int model_file_is_exist(const char *file_path)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int model_get_file_size(const char *file_path)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int model_read_file(const char *file_path, unsigned char *data_buf, int buf_size)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline unsigned char *model_read_file_to_buffer(const char *file_path, int *buf_size)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline unsigned char *model_read_bin_to_buffer(const char *file_path, int *buf_size)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline unsigned int CalCRC32(unsigned int crc, const unsigned char *ptr, int buf_len)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int panel_param_mem_put(unsigned char *mem, const char *name, u32 len);
|
|
unsigned char *panel_param_mem_get(const char *name, u32 *len);
|
|
int panel_param_mem_modify(unsigned char *mem, const char *name, u32 len);
|
|
|
|
#endif /* INC_AML_LCD_VOUT_H */
|