/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * include/amlogic/aml_lcd_vout.h
 *
 * Copyright (C) 2020 Amlogic, Inc. All rights reserved.
 *
 */

#ifndef INC_AML_LCD_VOUT_H
#define INC_AML_LCD_VOUT_H

#include <common.h>
#include <linux/list.h>
#include <amlogic/aml_lcd_timing.h>
#include <amlogic/aml_lcd_cus_ctrl.h>
#ifdef CONFIG_AML_LCD_TCON
#include <amlogic/aml_lcd_tcon_data.h>
#endif

/* **********************************
 * debug print define
 * ********************************** */
//#define LCD_DEBUG_INFO
extern unsigned int lcd_debug_print_flag;

#define LCDPR(fmt, args...)     printf("lcd: "fmt"", ## args)
#define LCDERR(fmt, args...)    printf("lcd: error: "fmt"", ## args)

#define PR_BUF_MAX              (4 * 1024)

/* **********************************
 * clk parameter bit define
 * pll_ctrl, div_ctrl, clk_ctrl
 * ********************************** */
/* ******** pll_ctrl ******** */
#define PLL_CTRL_OD3                20 /* [21:20] */
#define PLL_CTRL_OD2                18 /* [19:18] */
#define PLL_CTRL_OD1                16 /* [17:16] */
#define PLL_CTRL_N                  9  /* [13:9] */
#define PLL_CTRL_M                  0  /* [8:0] */

/* ******** div_ctrl ******** */
#define DIV_CTRL_EDP_DIV1           24 /* [26:24] */
#define DIV_CTRL_EDP_DIV0           20 /* [23:20] */
#define DIV_CTRL_DIV_SEL            8 /* [15:8] */
#define DIV_CTRL_XD                 0 /* [7:0] */

/* ******** clk_ctrl ******** */
#define CLK_CTRL_LEVEL              28 /* [30:28] */
#define CLK_CTRL_FRAC_SHIFT         24 /* [24] */
#define CLK_CTRL_FRAC               0  /* [23:0] */


/* **********************************
 * VENC to TCON sync delay
 * ********************************** */
#define TTL_DELAY                   13
#define PRE_DE_DELAY                8


#define LCD_PINMUX_END          0xff
#define LCD_PINMUX_NUM          15

/* **********************************
 * global control define
 * ********************************** */
enum lcd_mode_e {
	LCD_MODE_TV = 0,
	LCD_MODE_TABLET,
	LCD_MODE_MAX,
};

enum lcd_chip_e {
	LCD_CHIP_GXTVBB = 0,
	LCD_CHIP_GXL,     	/* 1 */
	LCD_CHIP_GXM,     	/* 2 */
	LCD_CHIP_TXL,     	/* 3 */
	LCD_CHIP_TXLX,    	/* 4 */
	LCD_CHIP_AXG, 		/* 5 */
	LCD_CHIP_TXHD, 		/* 6 */
	LCD_CHIP_G12A, 		/* 7 */
	LCD_CHIP_G12B, 		/* 8 */
	LCD_CHIP_TL1, 		/* 9 */
	LCD_CHIP_SM1,		/* 10 */
	LCD_CHIP_TM2,		/* 11 */
	LCD_CHIP_T5,		/* 12 */
	LCD_CHIP_T5D,		/* 13 */
	LCD_CHIP_T5W,		/* 14 */
	LCD_CHIP_MAX,
};

enum lcd_type_e {
	LCD_TTL = 0,
	LCD_LVDS,
	LCD_VBYONE,
	LCD_MIPI,
	LCD_MLVDS,
	LCD_P2P,
	LCD_TYPE_MAX,
};

#define MOD_LEN_MAX        48
struct lcd_basic_s {
	char model_name[MOD_LEN_MAX];
	enum lcd_type_e lcd_type;
	unsigned char lcd_bits;
	unsigned char config_check;

	unsigned short screen_width;  /* screen physical width in "mm" unit */
	unsigned short screen_height; /* screen physical height in "mm" unit */
};

#define LCD_CLK_FRAC_UPDATE     (1 << 0)
#define LCD_CLK_PLL_CHANGE      (1 << 1)
#define LCD_CLK_PLL_RESET       (1 << 2)
struct lcd_timing_s {
	struct lcd_detail_timing_s dft_timing; //panel parameter probe stage
	struct lcd_detail_timing_s base_timing; //panel parameter init stage
	struct lcd_detail_timing_s act_timing; //panel parameter actual stage

	unsigned char pll_flag;
	unsigned char clk_change; /* internal used */
	unsigned int ss_level;
	unsigned int ss_freq;
	unsigned int ss_mode;
	unsigned int enc_clk;
	unsigned long long bit_rate; /* Hz */

	unsigned int pll_ctrl;  /* pll settings */
	unsigned int div_ctrl;  /* divider settings */
	unsigned int clk_ctrl;  /* clock settings */

	unsigned int hstart;
	unsigned int hend;
	unsigned int vstart;
	unsigned int vend;

	unsigned char pre_de_h;
	unsigned char pre_de_v;

	unsigned short de_hs_addr;
	unsigned short de_he_addr;
	unsigned short de_vs_addr;
	unsigned short de_ve_addr;

	unsigned short hs_hs_addr;
	unsigned short hs_he_addr;
	unsigned short hs_vs_addr;
	unsigned short hs_ve_addr;

	unsigned short vs_hs_addr;
	unsigned short vs_he_addr;
	unsigned short vs_vs_addr;
	unsigned short vs_ve_addr;

	unsigned short pre_h_de_start;
	unsigned short pre_h_de_end;
	unsigned short pre_v_de_start;
	unsigned short pre_v_de_end;
	unsigned short pre_hso_start;
	unsigned short pre_hso_end;
	unsigned short pre_vso_hstart;
	unsigned short pre_vso_hend;
	unsigned short pre_vso_start;
	unsigned short pre_vso_end;
};

struct lcd_disp_tmg_req_s {
	unsigned int alert_level;//0:disable, 1:warning, 2:fatal err
	unsigned int hswbp_vid;
	unsigned int hfp_vid;
	unsigned int vswbp_vid;
	unsigned int vfp_vid;
};

struct ttl_config_s {
	unsigned int clk_pol;
	unsigned int sync_valid; /* [1]DE, [0]hvsync */
	unsigned int swap_ctrl; /* [1]rb swap, [0]bit swap */
};

#define LVDS_PHY_VSWING_DFT        3
#define LVDS_PHY_PREEM_DFT         0
#define LVDS_PHY_CLK_VSWING_DFT    0
#define LVDS_PHY_CLK_PREEM_DFT     0
struct lvds_config_s {
	unsigned int lvds_repack;
	unsigned int dual_port;
	unsigned int pn_swap;
	unsigned int port_swap;
	unsigned int lane_reverse;
	unsigned int port_sel;
	unsigned int phy_vswing;
	unsigned int phy_preem;
	unsigned int phy_clk_vswing;
	unsigned int phy_clk_preem;
};

#define VX1_PHY_VSWING_DFT           3
#define VX1_PHY_PREEM_DFT            0

#define VX1_PWR_ON_RESET_DLY_DFT     500 /* 500ms */
#define VX1_HPD_DATA_DELAY_DFT       10 /* 10ms */
#define VX1_CDR_TRAINING_HOLD_DFT    200 /* 200ms */

#define VX1_SW_FILTER_TIME_DFT       10 /* 10*100us=1ms */
#define VX1_SW_FILTER_CNT_DFT        6
#define VX1_SW_FILTER_RETRY_CNT_DFT  2
#define VX1_SW_FILTER_RETRY_DLY_DFT  100 /* 100ms */
#define VX1_SW_CDR_DET_TIME_DFT      20 /* 20us*100=2ms */
#define VX1_SW_CDR_DET_CNT_DFT       100
#define VX1_SW_CDR_TIMEOUT_CNT_DFT   100

struct vbyone_config_s {
	unsigned int lane_count;
	unsigned int region_num;
	unsigned int byte_mode;
	unsigned int color_fmt;
	unsigned int phy_div;
	unsigned int phy_vswing; /*[5:4]:ext_pullup, [3:0]vswing*/
	unsigned int phy_preem;
	unsigned int ctrl_flag;
		/* bit[0]:power_on_reset_en
		   bit[1]:hpd_data_delay_en
		   bit[2]:cdr_training_hold_en
		   bit[3]:hw_filter_en
		   bit[5:4]:sw_filter */

	/* ctrl timing */
	unsigned int power_on_reset_delay; /* ms */
	unsigned int hpd_data_delay; /* ms */
	unsigned int cdr_training_hold; /* ms */
	/* hw filter */
	unsigned int hpd_hw_filter_time; /* ms */
	unsigned int hpd_hw_filter_cnt;
	unsigned int lockn_hw_filter_time; /* ms */
	unsigned int lockn_hw_filter_cnt;
	/* sw filter */
	unsigned int vx1_sw_filter_en; /* 0=disable, 1=sw_filter, 2=sw_filter with sw_reset */
	unsigned int vx1_sw_filter_time; /* 100us base */
	unsigned int vx1_sw_filter_cnt;
	unsigned int vx1_sw_filter_retry_cnt;
	unsigned int vx1_sw_filter_retry_delay; /* ms base */
	unsigned int vx1_sw_cdr_detect_time; /* us base * 100 times, must cover tcon lockn pulse */
	unsigned int vx1_sw_cdr_detect_cnt;
	unsigned int vx1_sw_cdr_timeout_cnt;
	/* hw filter */
	unsigned int hw_filter_time;
	unsigned int hw_filter_cnt;
};

/* mipi-dsi config */
/* Operation mode parameters */
#define OPERATION_VIDEO_MODE     0
#define OPERATION_COMMAND_MODE   1

#define SYNC_PULSE               0x0
#define SYNC_EVENT               0x1
#define BURST_MODE               0x2

/* command config */
#define DSI_CMD_SIZE_INDEX       1  /* byte[1] */
#define DSI_GPIO_INDEX           2  /* byte[2] */

#define DSI_INIT_ON_MAX          100
#define DSI_INIT_OFF_MAX         30

struct dsi_config_s {
	unsigned char lane_num;
	unsigned int bit_rate_max;
	unsigned int bit_rate_min;
	unsigned int clk_factor; /* bit_rate/pclk */
	unsigned int factor_numerator;
	unsigned int factor_denominator; /* 100 */
	unsigned char operation_mode_init; /* 0=video mode, 1=command mode */
	unsigned char operation_mode_display; /* 0=video mode, 1=command mode */
	unsigned char video_mode_type; /* 0=sync_pulse, 1=sync_event, 2=burst */
	unsigned char clk_always_hs; /* 0=disable, 1=enable */
	unsigned char phy_switch; /* 0=auto, 1=standard, 2=slow */

	unsigned int venc_data_width;
	unsigned int dpi_data_format;

	unsigned char *dsi_init_on;
	unsigned char *dsi_init_off;
	unsigned char extern_init;

	unsigned char check_en;
	unsigned char check_reg;
	unsigned char check_cnt;
	unsigned char check_state;
};

struct mlvds_config_s {
	unsigned int channel_num;
	unsigned int channel_sel0;
	unsigned int channel_sel1;
	unsigned int clk_phase; /* [14:13]=clk01_sel,
				 * [12]=data bypass buffer,
				 * [11:8]=pi2, [7:4]=pi1, [3:0]=pi0
				 */
	unsigned int pn_swap;
	unsigned int bit_swap; /* MSB/LSB reverse */
	unsigned int phy_vswing;
	unsigned int phy_preem;

	/* internal used */
	unsigned int pi_clk_sel; /* bit[9:0] */
};

enum p2p_type_e {
	P2P_CEDS = 0,
	P2P_CMPI,
	P2P_ISP,
	P2P_EPI,
	P2P_CHPI = 0x10, /* low common mode */
	P2P_CSPI,
	P2P_USIT,
	P2P_MAX,
};

struct p2p_config_s {
	unsigned int p2p_type; /* bit[4:0] for type, bit[5] for vcm flag */
	unsigned int lane_num;
	unsigned int channel_sel0;
	unsigned int channel_sel1;
	unsigned int pn_swap;
	unsigned int bit_swap; /* MSB/LSB reverse */
	unsigned int phy_vswing;
	unsigned int phy_preem;
};

#define PHY_BIT_VSWING      (1 << 0)
#define PHY_BIT_VCM         (1 << 1)
#define PHY_BIT_REF_BIAS    (1 << 2)
#define PHY_BIT_ODT         (1 << 3)
#define PHY_BIT_CV_MODE     (1 << 4)
#define PHY_BIT_LANE_PREEM  (1 << 12)
#define PHY_BIT_LAEN_AMP    (1 << 13)
#define PHY_BIT_LANE_SEL    (1 << 14)

#define PHY_PHASE_0 0
#define PHY_PHASE_A 1
#define PHY_PHASE_B 2

struct phy_lane_s {
	unsigned int preem; //flag bit[12]
	unsigned int amp;   //flag bit[13]
	unsigned int sel;   //flag bit[14]
	unsigned char phase_sel;
};

#define PHY_CMODE   0
#define PHY_VMODE   1
#define CH_LANE_MAX 32
struct phy_config_s {
	unsigned int flag;
	unsigned int vswing;     //flag bit[0]
	unsigned int vcm;        //flag bit[1]
	unsigned int ref_bias;   //flag bit[2]
	unsigned int odt;        //flag bit[3]
	unsigned int cv_mode;    //flag bit[4] //val:0=cm,1=vm
	unsigned int weakly_pull_down;
	struct phy_lane_s lane[CH_LANE_MAX];

	unsigned int lane_num;
	unsigned int ch_swap0;
	unsigned int ch_swap1;
	unsigned int vswing_level;
	unsigned int ext_pullup;
	unsigned int preem_level;
	unsigned int low_common_mode;
	unsigned int clk_phase;
	unsigned int ckdi;

	unsigned int lane_valid; //(valid & mask)<<offset
	unsigned int lane_offset;
	unsigned int lane_mask; //local mask for lane range
};

struct lcd_ctrl_config_s {
	struct ttl_config_s *ttl_config;
	struct lvds_config_s *lvds_config;
	struct vbyone_config_s *vbyone_config;
	struct dsi_config_s *mipi_config;
	struct mlvds_config_s *mlvds_config;
	struct p2p_config_s *p2p_config;
	struct phy_config_s *phy_cfg;
};

/* **********************************
 * power control define
 * ********************************** */
enum lcd_power_type_e {
	LCD_POWER_TYPE_CPU = 0,
	LCD_POWER_TYPE_PMU,                 /* 1 */
	LCD_POWER_TYPE_SIGNAL,              /* 2 */
	LCD_POWER_TYPE_EXTERN,              /* 3 */
	LCD_POWER_TYPE_WAIT_GPIO,           /* 4 */
	LCD_POWER_TYPE_CLK_SS,              /* 5 */
	LCD_POWER_TYPE_TCON_SPI_DATA_LOAD,  /* 6 */
	LCD_POWER_TYPE_OFF_DELAY = 0xfd,
	LCD_POWER_TYPE_MAX,
};

#define LCD_POWER_TYPE_END           0xff

enum lcd_pmu_gpio_e {
	LCD_PMU_GPIO0 = 0,
	LCD_PMU_GPIO1,
	LCD_PMU_GPIO2,
	LCD_PMU_GPIO3,
	LCD_PMU_GPIO4,
	LCD_PMU_GPIO_MAX,
};

#define LCD_CLK_SS_BIT_FREQ             0
#define LCD_CLK_SS_BIT_MODE             4

#define LCD_GPIO_MAX                    0xff
#define LCD_GPIO_OUTPUT_LOW             0
#define LCD_GPIO_OUTPUT_HIGH            1
#define LCD_GPIO_INPUT                  2

/* Power Control */
#define LCD_CPU_GPIO_NUM_MAX         10
#define LCD_CPU_GPIO_NAME_MAX        10
#define LCD_PMU_GPIO_NUM_MAX         3

#define LCD_PWR_STEP_MAX             15
struct lcd_power_step_s {
	unsigned char type;
	int index; /* point to lcd_cpu_gpio_s or lcd_pmu_gpio_s or lcd_extern */
	unsigned short value;
	unsigned short delay;
};

struct lcd_power_ctrl_s {
	char cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
	int *pmu_gpio;
	struct lcd_power_step_s power_on_step[LCD_PWR_STEP_MAX];
	struct lcd_power_step_s power_off_step[LCD_PWR_STEP_MAX];
};

#define LCD_PINMX_MAX              10
#define BL_PINMUX_MAX              20
#define LCD_PINMUX_NAME_LEN_MAX    30
struct lcd_pinmux_ctrl_s {
	char *name;
	unsigned int pinmux_set[LCD_PINMUX_NUM][2];
	unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
};

#define LCD_DURATION_MAX    8
struct lcd_duration_s {
	unsigned int frame_rate;
	unsigned int duration_num;
	unsigned int duration_den;
	unsigned int frac;
};

struct lcd_vmode_info_s {
	char name[32];
	unsigned int width;
	unsigned int height;
	unsigned int base_fr;
	unsigned int duration_index;
	unsigned int duration_cnt;
	struct lcd_duration_s duration[LCD_DURATION_MAX];
	struct lcd_detail_timing_s *dft_timing;
};

struct lcd_vmode_list_s {
	struct lcd_vmode_info_s *info;
	struct lcd_vmode_list_s *next;
};

struct lcd_vmode_mgr_s {
	unsigned int vmode_cnt;
	struct lcd_vmode_list_s *vmode_list_header;
	struct lcd_vmode_info_s *cur_vmode_info;
	struct lcd_vmode_info_s *next_vmode_info;
};

struct cus_ctrl_config_s {
	unsigned int ctrl_en;
	unsigned int ctrl_cnt;
	unsigned int timing_cnt;
	unsigned int active_timing_type;
	unsigned char timing_switch_flag;
	unsigned char timing_ctrl_valid;

	struct lcd_cus_ctrl_attr_config_s *attr_config;
	struct lcd_cus_ctrl_attr_config_s *cur_timing_attr;
};

#define LCD_ENABLE_RETRY_MAX    3
#define CUS_PINMUX_NAME_MAX	44
#define CUS_PINMUX_MODE_MODEL_NAME   1
#define CUS_PINMUX_MODE_CUSTOM_NAME  2 //not support
struct lcd_config_s {
	unsigned char lcd_mode;
	unsigned char lcd_key_valid;
	unsigned char lcd_clk_path; /* 0=hpll, 1=gp0_pll */
	unsigned char retry_enable_flag;
	unsigned char retry_enable_cnt;
	unsigned int output_vmode;
	unsigned int backlight_index;
	struct lcd_basic_s lcd_basic;
	struct lcd_timing_s lcd_timing;
	struct lcd_ctrl_config_s lcd_control;
	struct lcd_power_ctrl_s *lcd_power;
	struct lcd_duration_s *std_duration;
	unsigned char pinctrl_ver;
	unsigned char fr_auto_cus;  //0=follow global setting, 0xff=disable
	unsigned char fr_auto_flag; //final fr_auto policy
	struct cus_ctrl_config_s cus_ctrl;
	struct lcd_pinmux_ctrl_s *lcd_pinmux;
	unsigned int pinmux_set[LCD_PINMUX_NUM][2];
	unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
	char cus_pinmux_name[CUS_PINMUX_NAME_MAX];
};

extern struct lcd_config_s lcd_config_dft;

/* ==============backlight control config================== */
enum bl_ctrl_method_e {
	BL_CTRL_GPIO = 0,
	BL_CTRL_PWM,
	BL_CTRL_PWM_COMBO,
	BL_CTRL_LOCAL_DIMMING,
	BL_CTRL_EXTERN,
	BL_CTRL_MAX,
};

enum bl_pwm_method_e {
	BL_PWM_NEGATIVE = 0,
	BL_PWM_POSITIVE,
	BL_PWM_METHOD_MAX,
};

enum bl_pwm_port_e {
	BL_PWM_A = 0,
	BL_PWM_B,
	BL_PWM_C,
	BL_PWM_D,
	BL_PWM_E,
	BL_PWM_F,
	BL_PWM_G,
	BL_PWM_H,
	BL_PWM_I,
	BL_PWM_J,
	BL_PWM_AO_A = 0x50,
	BL_PWM_AO_B,
	BL_PWM_AO_C,
	BL_PWM_AO_D,
	BL_PWM_AO_E,
	BL_PWM_AO_F,
	BL_PWM_AO_G,
	BL_PWM_AO_H,
	BL_PWM_VS = 0xa0,
	BL_PWM_MAX = 0xff,
};

enum bl_off_policy_e {
	BL_OFF_POLICY_NONE = 0,
	BL_OFF_POLICY_ALWAYS,
	BL_OFF_POLICY_ONCE,
	BL_OFF_POLICY_MAX,
};

#define XTAL_FREQ_HZ		(24*1000*1000) /* 24M in HZ */
#define XTAL_HALF_FREQ_HZ	(24*1000*500)  /* 24M/2 in HZ */

#define BL_FREQ_DEFAULT			1000 /* unit: HZ */
#define BL_FREQ_VS_DEFAULT		2    /* multiple 2 of vfreq */

#define BL_LEVEL_FULL_SCALE    4095
#define BL_PWM_DUTY_FULL_SCALE 4095

#define PWM_MAP_RESCALING      0
#define PWM_MAP_NORMALIZATION  1

#define BL_GPIO_NUM_MAX		5

struct bl_pwm_config_s {
	unsigned int index;
	enum bl_pwm_method_e pwm_method;
	enum bl_pwm_port_e pwm_port;
	int level_max;
	int level_min;

	unsigned int pwm_freq; /* pwm_vs: 1~4(vfreq), pwm: freq(unit: Hz) */
	unsigned int pwm_duty; /* 12bit */
	unsigned int pwm_duty_dft; /* 12bit */
	unsigned int pwm_duty_save; /* 12bit */
	unsigned int pwm_duty_max; /* 12bit */
	unsigned int pwm_duty_min; /* 12bit */
	unsigned int pwm_phase;

	unsigned int pwm_cnt; /* internal used for pwm control */
	unsigned int pwm_pre_div; /* internal used for pwm control */
	unsigned int pwm_value; /* internal used for pwm control */

	unsigned int pwm_gpio;
	unsigned int pwm_gpio_off;
	unsigned int pinmux_flag;
	unsigned int pinmux_set[LCD_PINMUX_NUM][2];
	unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
};

struct bl_config_s {
	unsigned char bl_key_valid;
	char name[20];
	int level_default;
	int level_min;
	int level_max;
	int level;

	int level_mid;
	int level_mid_mapping;

	int level_in_scale;
	unsigned int pwm_duty_in_scale;
	unsigned int pwm_mapping_method;

	enum bl_ctrl_method_e method;
	unsigned int en_gpio;
	unsigned int en_gpio_on;
	unsigned int en_gpio_off;
	unsigned short power_on_delay;
	unsigned short power_off_delay;
	unsigned int en_sequence_reverse;

	struct bl_pwm_config_s *bl_pwm;
	struct bl_pwm_config_s *bl_pwm_combo0;
	struct bl_pwm_config_s *bl_pwm_combo1;
	unsigned int pwm_on_delay;
	unsigned int pwm_off_delay;

	char gpio_name[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
	unsigned char pinctrl_ver;
	struct lcd_pinmux_ctrl_s *bl_pinmux;
	unsigned int pinmux_set[LCD_PINMUX_NUM][2];
	unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
	int bl_extern_index;
};

extern struct bl_config_s bl_config_dft;

#define LCD_INIT_LEVEL_NORMAL         0
#define LCD_INIT_LEVEL_PWR_OFF        1
#define LCD_INIT_LEVEL_KERNEL_ON      2
#define LCD_INIT_LEVEL_KERNEL_OFF     3
#define LCD_INIT_LEVEL_PREBOOT        4
/*
 *bit[31:24]: frame_rate
 *bit[23:20]: reserved, do not use
 *bit[19:18]: lcd_init_level
 *bit[17]: reserved
 *bit[16]: reserved
 *bit[15:8]: advanced flag(p2p_type when lcd_type=p2p)
 *bit[7:4]: lcd bits
 *bit[3:0]: lcd_type
 */
struct lcd_boot_ctrl_s {
	unsigned char lcd_type;
	unsigned char lcd_bits;
	unsigned char advanced_flag;
	unsigned char reserved;
	unsigned char init_level;
	unsigned char frame_rate;
};

/*
 *bit[31:30]: lcd mode(0=normal, 1=tv; 2=tablet, 3=TBD)
 *bit[29:28]: lcd debug para source(0=normal, 1=dts, 2=unifykey,
 *                                  3=bsp for uboot)
 *bit[27:20]: reserved
 *bit[19:16]: lcd test pattern
 *bit[15:0]:  lcd debug print flag
 */
struct lcd_debug_ctrl_s {
	unsigned short debug_print_flag;
	unsigned char debug_test_pattern;
	unsigned char debug_para_source;
	unsigned char debug_lcd_mode;
};

/* ==============lcd driver================== */
struct aml_lcd_drv_s {
	char version[15];
	enum lcd_chip_e chip_type;
	char rev_type;
	unsigned char probe_done;
	unsigned char lcd_status;
	unsigned char config_check_glb;
	unsigned char config_check_en;

	struct lcd_config_s *lcd_config;
	struct bl_config_s *bl_config;
	struct lcd_disp_tmg_req_s disp_req;
	struct lcd_vmode_mgr_s vmode_mgr;

	int  (*outputmode_check)(char *mode);
	int  (*config_valid)(char *mode);
	void (*driver_init_pre)(void);
	int  (*driver_init)(void);
	void (*driver_disable)(void);
	void (*list_support_mode)(void);
	int  (*lcd_probe)(void);
	int  (*lcd_outputmode_check)(char *mode, unsigned int frac);
	void (*lcd_prepare)(char *mode, unsigned int frac);
	void (*lcd_enable)(char *mode, unsigned int frac);
	void (*lcd_disable)(void);
	void (*lcd_set_ss)(unsigned int level, unsigned int freq, unsigned int mode);
	void (*lcd_get_ss)(void);
	void (*lcd_test)(int num);
	void (*lcd_config_check)(void);
	int (*lcd_prbs)(unsigned int s, unsigned int mode_flag);
	void (*lcd_clk)(void);
	void (*lcd_info)(void);
	void (*lcd_reg)(void);
	void (*lcd_tcon_reg_print)(void);
	void (*lcd_tcon_table_print)(void);
	void (*lcd_tcon_vac_print)(void);
	void (*lcd_tcon_demura_print)(void);
	void (*lcd_tcon_acc_print)(void);
	void (*lcd_tcon_data_print)(unsigned char index);
	void (*lcd_tcon_spi_print)(void);
	int (*tcon_forbidden_check)(void);
	int (*lcd_tcon_spi_data_load)(void);
	unsigned int (*lcd_tcon_reg_read)(unsigned int addr, unsigned int flag);
	void (*lcd_tcon_reg_write)(unsigned int addr, unsigned int val, unsigned int flag);
	unsigned int (*lcd_tcon_table_read)(unsigned int addr);
	unsigned int (*lcd_tcon_table_write)(unsigned int addr, unsigned int val);
	int (*tcon_mem_tee_protect)(int mem_flag, int protect_en);
	void (*lcd_vbyone_rst)(void);
	int (*lcd_vbyone_cdr)(void);
	int (*lcd_vbyone_lock)(void);
	void (*bl_on)(void);
	void (*bl_off)(void);
	void (*set_bl_level)(int level);
	int  (*get_bl_level)(void);
	void (*bl_config_print)(void);
	int unifykey_test_flag;
	void (*unifykey_dump)(unsigned int);
	void (*debug_print_set)(unsigned int flag);

	/* for factory test */
	struct lcd_power_step_s *factory_lcd_power_on_step;
	int factory_bl_power_on_delay;
};

extern void lcd_config_bsp_init(void);

extern struct aml_lcd_drv_s *aml_lcd_get_driver(void);

extern int lcd_probe(void);

#ifdef CONFIG_CMD_INI
int model_file_is_exist(const char *file_path);
int model_get_file_size(const char *file_path);
int model_read_file(const char *file_path, unsigned char *data_buf, int buf_size);
unsigned char *model_read_file_to_buffer(const char *file_path, int *buf_size);
unsigned char *model_read_bin_to_buffer(const char *file_path, int *buf_size);
unsigned int CalCRC32(unsigned int crc, const unsigned char *ptr, int buf_len);
#else
static inline int model_file_is_exist(const char *file_path)
{
	return 0;
}

static inline int model_get_file_size(const char *file_path)
{
	return 0;
}

static inline int model_read_file(const char *file_path, unsigned char *data_buf, int buf_size)
{
	return 0;
}

static inline unsigned char *model_read_file_to_buffer(const char *file_path, int *buf_size)
{
	return NULL;
}

static inline unsigned char *model_read_bin_to_buffer(const char *file_path, int *buf_size)
{
	return NULL;
}

static inline unsigned int CalCRC32(unsigned int crc, const unsigned char *ptr, int buf_len)
{
	return 0;
}
#endif

int panel_param_mem_put(unsigned char *mem, const char *name, u32 len);
unsigned char *panel_param_mem_get(const char *name, u32 *len);
int panel_param_mem_modify(unsigned char *mem, const char *name, u32 len);

#endif /* INC_AML_LCD_VOUT_H */