65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/*
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* Copyright (c) 2021-2022 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RISCV_CACHE_H
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#define RISCV_CACHE_H
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#include "riscv_encoding.h"
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#define __FENCE(p, s) __asm volatile ("fence " #p "," #s : : : "memory")
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#define __RWMB() __FENCE(iorw, iorw)
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/*!< Unlock and invalidate D-Cache line specified by CSR CCM_XBEGINADDR */
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/*!< Flush the specific D-Cache line specified by CSR CCM_XBEGINADDR */
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/*!< Unlock, flush and invalidate the specific D-Cache line specified by CSR CCM_XBEGINADDR */
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/*!< Lock the specific D-Cache line specified by CSR CCM_XBEGINADDR */
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/*!< Unlock the specific D-Cache line specified by CSR CCM_XBEGINADDR */
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/*!< Unlock and flush and invalidate all the valid and dirty D-Cache lines */
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/*!< Flush all the valid and dirty D-Cache lines */
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/*!< Unlock and invalidate all the D-Cache lines */
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/*!< Unlock and invalidate I-Cache line specified by CSR CCM_XBEGINADDR */
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/*!< Lock the specific I-Cache line specified by CSR CCM_XBEGINADDR */
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/*!< Unlock the specific I-Cache line specified by CSR CCM_XBEGINADDR */
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/*!< Unlock and invalidate all the I-Cache lines */
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typedef enum CCM_CMD {
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CCM_DC_INVAL = 0x0,
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CCM_DC_WB = 0x1,
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CCM_DC_WBINVAL = 0x2,
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CCM_DC_LOCK = 0x3,
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CCM_DC_UNLOCK = 0x4,
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CCM_DC_WBINVAL_ALL = 0x6,
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CCM_DC_WB_ALL = 0x7,
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CCM_DC_INVAL_ALL = 0x17,
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CCM_IC_INVAL = 0x8,
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CCM_IC_LOCK = 0xb,
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CCM_IC_UNLOCK = 0xc,
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CCM_IC_INVAL_ALL = 0xd
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} CCM_CMD_Type;
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static inline void vFlushPipeCCM(void)
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{
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write_csr(ccm_fpipe, 0x1);
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}
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static inline void vMFlushDCacheLine(unsigned long addr)
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{
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write_csr(ccm_mbeginaddr, addr);
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write_csr(ccm_mcommand, CCM_DC_WB);
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vFlushPipeCCM();
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__RWMB();
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}
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static inline void vMInvalICacheLine(unsigned long addr)
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{
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write_csr(ccm_mbeginaddr, addr);
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write_csr(ccm_mcommand, CCM_IC_INVAL);
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vFlushPipeCCM();
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__RWMB();
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}
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#endif
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