299 lines
15 KiB
C
299 lines
15 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_SC2_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_SC2_CLKC_H
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#define CLKID_GP0_PLL 0
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#define CLKID_HIFI_PLL 1
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#define CLKID_PCIE_PLL_DCO 2
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#define CLKID_HDMI_PLL_DCO 3
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#define CLKID_MPLL_PREDIV 4
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#define CLKID_MPLL0 5
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#define CLKID_MPLL0_DIV 6
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#define CLKID_MPLL1 7
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#define CLKID_MPLL1_DIV 8
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#define CLKID_MPLL2 9
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#define CLKID_MPLL2_DIV 10
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#define CLKID_MPLL3 11
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#define CLKID_MPLL3_DIV 12
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#define CLKID_PCIE_PLL_DCO_DIV2 13
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#define CLKID_PCIE_PLL_OD 14
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#define CLKID_PCIE_PLL 15
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#define CLKID_PCIE_BGP 16
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#define CLKID_PCIE_HCSL 17
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#define CLKID_HDMI_PLL_OD 18
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#define CLKID_HDMI_PLL 19
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#define CLKID_FCLK_DIV2_DIV 20
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#define CLKID_FCLK_DIV2 21
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#define CLKID_FCLK_DIV2P5_DIV 22
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#define CLKID_FCLK_DIV2P5 23
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#define CLKID_FCLK_DIV3_DIV 24
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#define CLKID_FCLK_DIV3 25
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#define CLKID_FCLK_DIV4_DIV 26
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#define CLKID_FCLK_DIV4 27
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#define CLKID_FCLK_DIV5_DIV 28
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#define CLKID_FCLK_DIV5 29
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#define CLKID_FCLK_DIV7_DIV 30
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#define CLKID_FCLK_DIV7 31
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#define CLKID_CLK_24M_IN 32
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#define CLKID_CLK_12M_DIV 33
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#define CLKID_CLK_12M 34
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#define CLKID_CLK_25M_DIV 35
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#define CLKID_CLK_25M 36
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#define CLKID_RTC_DUAL_CLKIN 37
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#define CLKID_RTC_DUAL_DIV 38
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#define CLKID_RTC_DUAL_MUX 39
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#define CLKID_RTC_DUAL 40
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#define CLKID_RTC_CLK 41
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#define CLKID_CECA_DUAL_CLKIN 42
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#define CLKID_CECA_DUAL_DIV 43
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#define CLKID_CECA_DUAL_MUX 44
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#define CLKID_CECA_DUAL 45
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#define CLKID_CECA_CLK 46
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#define CLKID_CECB_DUAL_CLKIN 47
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#define CLKID_CECB_DUAL_DIV 48
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#define CLKID_CECB_DUAL_MUX 49
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#define CLKID_CECB_DUAL 50
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#define CLKID_CECB_CLK 51
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#define CLKID_SC_MUX 52
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#define CLKID_SC_DIV 53
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#define CLKID_SC 54
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#define CLKID_DSPA_0_MUX 55
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#define CLKID_DSPA_0_DIV 56
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#define CLKID_DSPA_0 57
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#define CLKID_DSPA_1_MUX 58
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#define CLKID_DSPA_1_DIV 59
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#define CLKID_DSPA_1 60
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#define CLKID_DSPA 61
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#define CLKID_VIDEO_SRC0_IN_MUX 62
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#define CLKID_VIDEO_SRC0_IN 63
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#define CLKID_VIDEO_SRC0_DIV 64
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#define CLKID_VIDEO_SRC0 65
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#define CLKID_VIDEO_SRC1_IN_MUX 66
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#define CLKID_VIDEO_SRC1_IN 67
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#define CLKID_VIDEO_SRC1_DIV 68
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#define CLKID_VIDEO_SRC1 69
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#define CLKID_VIDEO0_DIV1 70
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#define CLKID_VIDEO0_DIV2_GATE 71
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#define CLKID_VIDEO0_DIV2 72
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#define CLKID_VIDEO0_DIV4_GATE 73
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#define CLKID_VIDEO0_DIV4 74
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#define CLKID_VIDEO0_DIV6_GATE 75
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#define CLKID_VIDEO0_DIV6 76
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#define CLKID_VIDEO0_DIV12_GATE 77
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#define CLKID_VIDEO0_DIV12 78
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#define CLKID_VIDEO2_DIV1 79
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#define CLKID_VIDEO2_DIV2_GATE 80
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#define CLKID_VIDEO2_DIV2 81
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#define CLKID_VIDEO2_DIV4_GATE 82
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#define CLKID_VIDEO2_DIV4 83
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#define CLKID_VIDEO2_DIV6_GATE 84
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#define CLKID_VIDEO2_DIV6 85
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#define CLKID_VIDEO2_DIV12_GATE 86
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#define CLKID_VIDEO2_DIV12 87
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#define CLKID_LCD_AN_MUX 88
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#define CLKID_LCD_AN 89
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#define CLKID_LCD_AN_PH2 90
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#define CLKID_LCD_AN_PH3 91
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#define CLKID_ENCI_MUX 92
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#define CLKID_ENCI 93
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#define CLKID_ENCP_MUX 94
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#define CLKID_ENCP 95
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#define CLKID_ENCT_MUX 96
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#define CLKID_ENCT 97
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#define CLKID_ENCL_MUX 98
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#define CLKID_ENCL 99
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#define CLKID_VDAC_MUX 100
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#define CLKID_VDAC 101
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#define CLKID_VID_LOCK_MUX 102
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#define CLKID_VID_LOCK_DIV 103
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#define CLKID_VID_LOCK 104
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#define CLKID_HDMI_SYS_MUX 105
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#define CLKID_HDMI_SYS_DIV 106
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#define CLKID_HDMI_SYS 107
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#define CLKID_TS_DIV 108
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#define CLKID_TS 109
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#define CLKID_MALI_0_MUX 110
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#define CLKID_MALI_0_DIV 111
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#define CLKID_MALI_0 112
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#define CLKID_MALI_1_MUX 113
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#define CLKID_MALI_1_DIV 114
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#define CLKID_MALI_1 115
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#define CLKID_MALI 116
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#define CLKID_VDEC_0_MUX 117
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#define CLKID_VDEC_0_DIV 118
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#define CLKID_VDEC_0 119
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#define CLKID_VDEC_1_MUX 120
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#define CLKID_VDEC_1_DIV 121
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#define CLKID_VDEC_1 122
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#define CLKID_VDEC 123
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#define CLKID_HCODEC_0_MUX 124
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#define CLKID_HCODEC_0_DIV 125
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#define CLKID_HCODEC_0 126
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#define CLKID_HCODEC_1_MUX 127
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#define CLKID_HCODEC_1_DIV 128
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#define CLKID_HCODEC_1 129
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#define CLKID_HCODEC 130
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#define CLKID_HEVCB_0_MUX 131
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#define CLKID_HEVCB_0_DIV 132
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#define CLKID_HEVCB_0 133
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#define CLKID_HEVCB_1_MUX 134
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#define CLKID_HEVCB_1_DIV 135
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#define CLKID_HEVCB_1 136
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#define CLKID_HEVCB 137
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#define CLKID_HEVCF_0_MUX 138
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#define CLKID_HEVCF_0_DIV 139
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#define CLKID_HEVCF_0 140
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#define CLKID_HEVCF_1_MUX 141
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#define CLKID_HEVCF_1_DIV 142
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#define CLKID_HEVCF_1 143
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#define CLKID_HEVCF 144
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#define CLKID_WAVE_A_MUX 145
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#define CLKID_WAVE_A_DIV 146
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#define CLKID_WAVE_A 147
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#define CLKID_WAVE_B_MUX 148
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#define CLKID_WAVE_B_DIV 149
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#define CLKID_WAVE_B 150
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#define CLKID_WAVE_C_MUX 151
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#define CLKID_WAVE_C_DIV 152
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#define CLKID_WAVE_C 153
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#define CLKID_VPU_0_MUX 154
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#define CLKID_VPU_0_DIV 155
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#define CLKID_VPU_0 156
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#define CLKID_VPU_1_MUX 157
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#define CLKID_VPU_1_DIV 158
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#define CLKID_VPU_1 159
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#define CLKID_VPU 160
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#define CLKID_VPU_CLKB_TMP_MUX 161
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#define CLKID_VPU_CLKB_TMP_DIV 162
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#define CLKID_VPU_CLKB_TMP 163
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#define CLKID_VPU_CLKB_DIV 164
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#define CLKID_VPU_CLKB 165
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#define CLKID_VPU_CLKC_0_MUX 166
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#define CLKID_VPU_CLKC_0_DIV 167
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#define CLKID_VPU_CLKC_0 168
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#define CLKID_VPU_CLKC_1_MUX 169
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#define CLKID_VPU_CLKC_1_DIV 170
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#define CLKID_VPU_CLKC_1 171
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#define CLKID_VPU_CLKC 172
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#define CLKID_VAPB_0_MUX 173
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#define CLKID_VAPB_0_DIV 174
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#define CLKID_VAPB_0 175
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#define CLKID_VAPB_1_MUX 176
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#define CLKID_VAPB_1_DIV 177
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#define CLKID_VAPB_1 178
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#define CLKID_VAPB 179
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#define CLKID_GE2D 180
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#define CLKID_VDIN_MEAS_MUX 181
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#define CLKID_VDIN_MEAS_DIV 182
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#define CLKID_VDIN_MEAS 183
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#define CLKID_SD_EMMC_A_MUX 184
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#define CLKID_SD_EMMC_A_DIV 185
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#define CLKID_SD_EMMC_A 186
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#define CLKID_SD_EMMC_B_MUX 187
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#define CLKID_SD_EMMC_B_DIV 188
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#define CLKID_SD_EMMC_B 189
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#define CLKID_SD_EMMC_C_MUX 190
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#define CLKID_SD_EMMC_C_DIV 191
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#define CLKID_SD_EMMC_C 192
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#define CLKID_SPICC0_MUX 193
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#define CLKID_SPICC0_DIV 194
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#define CLKID_SPICC0 195
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#define CLKID_SPICC1_MUX 196
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#define CLKID_SPICC1_DIV 197
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#define CLKID_SPICC1 198
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#define CLKID_PWM_A_MUX 199
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#define CLKID_PWM_A_DIV 200
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#define CLKID_PWM_A 201
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#define CLKID_PWM_B_MUX 202
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#define CLKID_PWM_B_DIV 203
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#define CLKID_PWM_B 204
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#define CLKID_PWM_C_MUX 205
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#define CLKID_PWM_C_DIV 206
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#define CLKID_PWM_C 207
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#define CLKID_PWM_D_MUX 208
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#define CLKID_PWM_D_DIV 209
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#define CLKID_PWM_D 210
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#define CLKID_PWM_E_MUX 211
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#define CLKID_PWM_E_DIV 212
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#define CLKID_PWM_E 213
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#define CLKID_PWM_F_MUX 214
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#define CLKID_PWM_F_DIV 215
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#define CLKID_PWM_F 216
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#define CLKID_PWM_G_MUX 217
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#define CLKID_PWM_G_DIV 218
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#define CLKID_PWM_G 219
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#define CLKID_PWM_H_MUX 220
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#define CLKID_PWM_H_DIV 221
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#define CLKID_PWM_H 222
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#define CLKID_PWM_I_MUX 223
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#define CLKID_PWM_I_DIV 224
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#define CLKID_PWM_I 225
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#define CLKID_PWM_J_MUX 226
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#define CLKID_PWM_J_DIV 227
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#define CLKID_PWM_J 228
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#define CLKID_SAR_ADC_MUX 229
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#define CLKID_SAR_ADC_DIV 230
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#define CLKID_SAR_ADC 231
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#define CLKID_GEN_MUX 232
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#define CLKID_GEN_DIV 233
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#define CLKID_GEN 234
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#define CLKID_SYS_DDR 235
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#define CLKID_SYS_DOS 236
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#define CLKID_SYS_ETH_PHY 237
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#define CLKID_SYS_MALI 238
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#define CLKID_SYS_AOCPU 239
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#define CLKID_SYS_AUCPU 240
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#define CLKID_SYS_CEC 241
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#define CLKID_SYS_SD_EMMC_A 242
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#define CLKID_SYS_SD_EMMC_B 243
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#define CLKID_SYS_SD_EMMC_C 244
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#define CLKID_SYS_SC 245
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#define CLKID_SYS_ACODEC 246
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#define CLKID_SYS_SPIFC 247
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#define CLKID_SYS_MSR_CLK 248
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#define CLKID_SYS_IR_CTRL 249
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#define CLKID_SYS_AUDIO 250
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#define CLKID_SYS_ETH 251
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#define CLKID_SYS_UART_A 252
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#define CLKID_SYS_UART_B 253
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#define CLKID_SYS_UART_C 254
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#define CLKID_SYS_UART_D 255
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#define CLKID_SYS_UART_E 256
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#define CLKID_SYS_AIFIFO 257
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#define CLKID_SYS_TS_DDR 258
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#define CLKID_SYS_TS_PLL 259
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#define CLKID_SYS_GE2D 260
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#define CLKID_SYS_SPICC0 261
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#define CLKID_SYS_SPICC1 262
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#define CLKID_SYS_PCIE 263
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#define CLKID_SYS_USB 264
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#define CLKID_SYS_PCIE_PHY 265
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#define CLKID_SYS_I2C_M_A 266
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#define CLKID_SYS_I2C_M_B 267
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#define CLKID_SYS_I2C_M_C 268
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#define CLKID_SYS_I2C_M_D 269
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#define CLKID_SYS_I2C_M_E 270
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#define CLKID_SYS_I2C_M_F 271
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#define CLKID_SYS_HDMITX_APB 272
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#define CLKID_SYS_I2C_S_A 273
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#define CLKID_SYS_USB1_TO_DDR 274
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#define CLKID_SYS_HDCP22 275
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#define CLKID_SYS_MMC_APB 276
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#define CLKID_SYS_RSA 277
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#define CLKID_SYS_CPU_DEBUG 278
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#define CLKID_SYS_DSPA 279
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#define CLKID_SYS_VPU_INTR 280
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#define CLKID_SYS_SAR_ADC 281
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#define CLKID_SYS_GIC 282
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#define CLKID_SYS_PWM_AB 283
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#define CLKID_SYS_PWM_CD 284
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#define CLKID_SYS_PWM_EF 285
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#define CLKID_SYS_PWM_GH 286
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#define CLKID_SYS_PWM_IJ 287
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_SC2_CLKC_H */
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