/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_SC2_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_SC2_CLKC_H

#define CLKID_GP0_PLL                             0
#define CLKID_HIFI_PLL                            1
#define CLKID_PCIE_PLL_DCO                        2
#define CLKID_HDMI_PLL_DCO                        3
#define CLKID_MPLL_PREDIV                         4
#define CLKID_MPLL0                               5
#define CLKID_MPLL0_DIV                           6
#define CLKID_MPLL1                               7
#define CLKID_MPLL1_DIV                           8
#define CLKID_MPLL2                               9
#define CLKID_MPLL2_DIV                           10
#define CLKID_MPLL3                               11
#define CLKID_MPLL3_DIV                           12
#define CLKID_PCIE_PLL_DCO_DIV2                   13
#define CLKID_PCIE_PLL_OD                         14
#define CLKID_PCIE_PLL                            15
#define CLKID_PCIE_BGP                            16
#define CLKID_PCIE_HCSL                           17
#define CLKID_HDMI_PLL_OD                         18
#define CLKID_HDMI_PLL                            19
#define CLKID_FCLK_DIV2_DIV                       20
#define CLKID_FCLK_DIV2                           21
#define CLKID_FCLK_DIV2P5_DIV                     22
#define CLKID_FCLK_DIV2P5                         23
#define CLKID_FCLK_DIV3_DIV                       24
#define CLKID_FCLK_DIV3                           25
#define CLKID_FCLK_DIV4_DIV                       26
#define CLKID_FCLK_DIV4                           27
#define CLKID_FCLK_DIV5_DIV                       28
#define CLKID_FCLK_DIV5                           29
#define CLKID_FCLK_DIV7_DIV                       30
#define CLKID_FCLK_DIV7                           31
#define CLKID_CLK_24M_IN                          32
#define CLKID_CLK_12M_DIV                         33
#define CLKID_CLK_12M                             34
#define CLKID_CLK_25M_DIV                         35
#define CLKID_CLK_25M                             36
#define CLKID_RTC_DUAL_CLKIN                      37
#define CLKID_RTC_DUAL_DIV                        38
#define CLKID_RTC_DUAL_MUX                        39
#define CLKID_RTC_DUAL                            40
#define CLKID_RTC_CLK                             41
#define CLKID_CECA_DUAL_CLKIN                     42
#define CLKID_CECA_DUAL_DIV                       43
#define CLKID_CECA_DUAL_MUX                       44
#define CLKID_CECA_DUAL                           45
#define CLKID_CECA_CLK                            46
#define CLKID_CECB_DUAL_CLKIN                     47
#define CLKID_CECB_DUAL_DIV                       48
#define CLKID_CECB_DUAL_MUX                       49
#define CLKID_CECB_DUAL                           50
#define CLKID_CECB_CLK                            51
#define CLKID_SC_MUX                              52
#define CLKID_SC_DIV                              53
#define CLKID_SC                                  54
#define CLKID_DSPA_0_MUX                          55
#define CLKID_DSPA_0_DIV                          56
#define CLKID_DSPA_0                              57
#define CLKID_DSPA_1_MUX                          58
#define CLKID_DSPA_1_DIV                          59
#define CLKID_DSPA_1                              60
#define CLKID_DSPA                                61
#define CLKID_VIDEO_SRC0_IN_MUX                   62
#define CLKID_VIDEO_SRC0_IN                       63
#define CLKID_VIDEO_SRC0_DIV                      64
#define CLKID_VIDEO_SRC0                          65
#define CLKID_VIDEO_SRC1_IN_MUX                   66
#define CLKID_VIDEO_SRC1_IN                       67
#define CLKID_VIDEO_SRC1_DIV                      68
#define CLKID_VIDEO_SRC1                          69
#define CLKID_VIDEO0_DIV1                         70
#define CLKID_VIDEO0_DIV2_GATE                    71
#define CLKID_VIDEO0_DIV2                         72
#define CLKID_VIDEO0_DIV4_GATE                    73
#define CLKID_VIDEO0_DIV4                         74
#define CLKID_VIDEO0_DIV6_GATE                    75
#define CLKID_VIDEO0_DIV6                         76
#define CLKID_VIDEO0_DIV12_GATE                   77
#define CLKID_VIDEO0_DIV12                        78
#define CLKID_VIDEO2_DIV1                         79
#define CLKID_VIDEO2_DIV2_GATE                    80
#define CLKID_VIDEO2_DIV2                         81
#define CLKID_VIDEO2_DIV4_GATE                    82
#define CLKID_VIDEO2_DIV4                         83
#define CLKID_VIDEO2_DIV6_GATE                    84
#define CLKID_VIDEO2_DIV6                         85
#define CLKID_VIDEO2_DIV12_GATE                   86
#define CLKID_VIDEO2_DIV12                        87
#define CLKID_LCD_AN_MUX                          88
#define CLKID_LCD_AN                              89
#define CLKID_LCD_AN_PH2                          90
#define CLKID_LCD_AN_PH3                          91
#define CLKID_ENCI_MUX                            92
#define CLKID_ENCI                                93
#define CLKID_ENCP_MUX                            94
#define CLKID_ENCP                                95
#define CLKID_ENCT_MUX                            96
#define CLKID_ENCT                                97
#define CLKID_ENCL_MUX                            98
#define CLKID_ENCL                                99
#define CLKID_VDAC_MUX                            100
#define CLKID_VDAC                                101
#define CLKID_VID_LOCK_MUX                        102
#define CLKID_VID_LOCK_DIV                        103
#define CLKID_VID_LOCK                            104
#define CLKID_HDMI_SYS_MUX                        105
#define CLKID_HDMI_SYS_DIV                        106
#define CLKID_HDMI_SYS                            107
#define CLKID_TS_DIV                              108
#define CLKID_TS                                  109
#define CLKID_MALI_0_MUX                          110
#define CLKID_MALI_0_DIV                          111
#define CLKID_MALI_0                              112
#define CLKID_MALI_1_MUX                          113
#define CLKID_MALI_1_DIV                          114
#define CLKID_MALI_1                              115
#define CLKID_MALI                                116
#define CLKID_VDEC_0_MUX                          117
#define CLKID_VDEC_0_DIV                          118
#define CLKID_VDEC_0                              119
#define CLKID_VDEC_1_MUX                          120
#define CLKID_VDEC_1_DIV                          121
#define CLKID_VDEC_1                              122
#define CLKID_VDEC                                123
#define CLKID_HCODEC_0_MUX                        124
#define CLKID_HCODEC_0_DIV                        125
#define CLKID_HCODEC_0                            126
#define CLKID_HCODEC_1_MUX                        127
#define CLKID_HCODEC_1_DIV                        128
#define CLKID_HCODEC_1                            129
#define CLKID_HCODEC                              130
#define CLKID_HEVCB_0_MUX                         131
#define CLKID_HEVCB_0_DIV                         132
#define CLKID_HEVCB_0                             133
#define CLKID_HEVCB_1_MUX                         134
#define CLKID_HEVCB_1_DIV                         135
#define CLKID_HEVCB_1                             136
#define CLKID_HEVCB                               137
#define CLKID_HEVCF_0_MUX                         138
#define CLKID_HEVCF_0_DIV                         139
#define CLKID_HEVCF_0                             140
#define CLKID_HEVCF_1_MUX                         141
#define CLKID_HEVCF_1_DIV                         142
#define CLKID_HEVCF_1                             143
#define CLKID_HEVCF                               144
#define CLKID_WAVE_A_MUX                          145
#define CLKID_WAVE_A_DIV                          146
#define CLKID_WAVE_A                              147
#define CLKID_WAVE_B_MUX                          148
#define CLKID_WAVE_B_DIV                          149
#define CLKID_WAVE_B                              150
#define CLKID_WAVE_C_MUX                          151
#define CLKID_WAVE_C_DIV                          152
#define CLKID_WAVE_C                              153
#define CLKID_VPU_0_MUX                           154
#define CLKID_VPU_0_DIV                           155
#define CLKID_VPU_0                               156
#define CLKID_VPU_1_MUX                           157
#define CLKID_VPU_1_DIV                           158
#define CLKID_VPU_1                               159
#define CLKID_VPU                                 160
#define CLKID_VPU_CLKB_TMP_MUX                    161
#define CLKID_VPU_CLKB_TMP_DIV                    162
#define CLKID_VPU_CLKB_TMP                        163
#define CLKID_VPU_CLKB_DIV                        164
#define CLKID_VPU_CLKB                            165
#define CLKID_VPU_CLKC_0_MUX                      166
#define CLKID_VPU_CLKC_0_DIV                      167
#define CLKID_VPU_CLKC_0                          168
#define CLKID_VPU_CLKC_1_MUX                      169
#define CLKID_VPU_CLKC_1_DIV                      170
#define CLKID_VPU_CLKC_1                          171
#define CLKID_VPU_CLKC                            172
#define CLKID_VAPB_0_MUX                          173
#define CLKID_VAPB_0_DIV                          174
#define CLKID_VAPB_0                              175
#define CLKID_VAPB_1_MUX                          176
#define CLKID_VAPB_1_DIV                          177
#define CLKID_VAPB_1                              178
#define CLKID_VAPB                                179
#define CLKID_GE2D                                180
#define CLKID_VDIN_MEAS_MUX                       181
#define CLKID_VDIN_MEAS_DIV                       182
#define CLKID_VDIN_MEAS                           183
#define CLKID_SD_EMMC_A_MUX                       184
#define CLKID_SD_EMMC_A_DIV                       185
#define CLKID_SD_EMMC_A                           186
#define CLKID_SD_EMMC_B_MUX                       187
#define CLKID_SD_EMMC_B_DIV                       188
#define CLKID_SD_EMMC_B                           189
#define CLKID_SD_EMMC_C_MUX                       190
#define CLKID_SD_EMMC_C_DIV                       191
#define CLKID_SD_EMMC_C                           192
#define CLKID_SPICC0_MUX                          193
#define CLKID_SPICC0_DIV                          194
#define CLKID_SPICC0                              195
#define CLKID_SPICC1_MUX                          196
#define CLKID_SPICC1_DIV                          197
#define CLKID_SPICC1                              198
#define CLKID_PWM_A_MUX                           199
#define CLKID_PWM_A_DIV                           200
#define CLKID_PWM_A                               201
#define CLKID_PWM_B_MUX                           202
#define CLKID_PWM_B_DIV                           203
#define CLKID_PWM_B                               204
#define CLKID_PWM_C_MUX                           205
#define CLKID_PWM_C_DIV                           206
#define CLKID_PWM_C                               207
#define CLKID_PWM_D_MUX                           208
#define CLKID_PWM_D_DIV                           209
#define CLKID_PWM_D                               210
#define CLKID_PWM_E_MUX                           211
#define CLKID_PWM_E_DIV                           212
#define CLKID_PWM_E                               213
#define CLKID_PWM_F_MUX                           214
#define CLKID_PWM_F_DIV                           215
#define CLKID_PWM_F                               216
#define CLKID_PWM_G_MUX                           217
#define CLKID_PWM_G_DIV                           218
#define CLKID_PWM_G                               219
#define CLKID_PWM_H_MUX                           220
#define CLKID_PWM_H_DIV                           221
#define CLKID_PWM_H                               222
#define CLKID_PWM_I_MUX                           223
#define CLKID_PWM_I_DIV                           224
#define CLKID_PWM_I                               225
#define CLKID_PWM_J_MUX                           226
#define CLKID_PWM_J_DIV                           227
#define CLKID_PWM_J                               228
#define CLKID_SAR_ADC_MUX                         229
#define CLKID_SAR_ADC_DIV                         230
#define CLKID_SAR_ADC                             231
#define CLKID_GEN_MUX                             232
#define CLKID_GEN_DIV                             233
#define CLKID_GEN                                 234
#define CLKID_SYS_DDR                             235
#define CLKID_SYS_DOS                             236
#define CLKID_SYS_ETH_PHY                         237
#define CLKID_SYS_MALI                            238
#define CLKID_SYS_AOCPU                           239
#define CLKID_SYS_AUCPU                           240
#define CLKID_SYS_CEC                             241
#define CLKID_SYS_SD_EMMC_A                       242
#define CLKID_SYS_SD_EMMC_B                       243
#define CLKID_SYS_SD_EMMC_C                       244
#define CLKID_SYS_SC                              245
#define CLKID_SYS_ACODEC                          246
#define CLKID_SYS_SPIFC                           247
#define CLKID_SYS_MSR_CLK                         248
#define CLKID_SYS_IR_CTRL                         249
#define CLKID_SYS_AUDIO                           250
#define CLKID_SYS_ETH                             251
#define CLKID_SYS_UART_A                          252
#define CLKID_SYS_UART_B                          253
#define CLKID_SYS_UART_C                          254
#define CLKID_SYS_UART_D                          255
#define CLKID_SYS_UART_E                          256
#define CLKID_SYS_AIFIFO                          257
#define CLKID_SYS_TS_DDR                          258
#define CLKID_SYS_TS_PLL                          259
#define CLKID_SYS_GE2D                            260
#define CLKID_SYS_SPICC0                          261
#define CLKID_SYS_SPICC1                          262
#define CLKID_SYS_PCIE                            263
#define CLKID_SYS_USB                             264
#define CLKID_SYS_PCIE_PHY                        265
#define CLKID_SYS_I2C_M_A                         266
#define CLKID_SYS_I2C_M_B                         267
#define CLKID_SYS_I2C_M_C                         268
#define CLKID_SYS_I2C_M_D                         269
#define CLKID_SYS_I2C_M_E                         270
#define CLKID_SYS_I2C_M_F                         271
#define CLKID_SYS_HDMITX_APB                      272
#define CLKID_SYS_I2C_S_A                         273
#define CLKID_SYS_USB1_TO_DDR                     274
#define CLKID_SYS_HDCP22                          275
#define CLKID_SYS_MMC_APB                         276
#define CLKID_SYS_RSA                             277
#define CLKID_SYS_CPU_DEBUG                       278
#define CLKID_SYS_DSPA                            279
#define CLKID_SYS_VPU_INTR                        280
#define CLKID_SYS_SAR_ADC                         281
#define CLKID_SYS_GIC                             282
#define CLKID_SYS_PWM_AB                          283
#define CLKID_SYS_PWM_CD                          284
#define CLKID_SYS_PWM_EF                          285
#define CLKID_SYS_PWM_GH                          286
#define CLKID_SYS_PWM_IJ                          287

#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_SC2_CLKC_H */