351 lines
18 KiB
C
351 lines
18 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S5_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_S5_CLKC_H
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#define CLKID_SYS2_PLL 0
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#define CLKID_GP0_PLL 1
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#define CLKID_GP2_PLL 2
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#define CLKID_HIFI_PLL 3
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#define CLKID_HIFI1_PLL 4
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#define CLKID_FPLL_DCO 5
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#define CLKID_NNA_PLL 6
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#define CLKID_PCIE_PLL_DCO 7
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#define CLKID_PCIE1_PLL_DCO 8
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#define CLKID_FCLK_50M_EN 9
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#define CLKID_FCLK_50M 10
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#define CLKID_FCLK_DIV2_DIV 11
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#define CLKID_FCLK_DIV2 12
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#define CLKID_FCLK_DIV2P5_DIV 13
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#define CLKID_FCLK_DIV2P5 14
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#define CLKID_FCLK_DIV3_DIV 15
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#define CLKID_FCLK_DIV3 16
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#define CLKID_FCLK_DIV4_DIV 17
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#define CLKID_FCLK_DIV4 18
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#define CLKID_FCLK_DIV5_DIV 19
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#define CLKID_FCLK_DIV5 20
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#define CLKID_FCLK_DIV7_DIV 21
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#define CLKID_FCLK_DIV7 22
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#define CLKID_FPLL_TMDS_OD 23
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#define CLKID_FPLL_TMDS_OD1 24
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#define CLKID_FPLL_TMDS 25
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#define CLKID_FPLL_PIXEL 26
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#define CLKID_NNA_PLL_AUDIO 27
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#define CLKID_PCIE_PLL_DCO_DIV2 28
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#define CLKID_PCIE_PLL_OD 29
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#define CLKID_PCIE_PLL 30
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#define CLKID_PCIE_BGP 31
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#define CLKID_PCIE_HCSL 32
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#define CLKID_PCIE_HCSL_IN_PAD 33
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#define CLKID_PCIE_CLK_IN 34
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#define CLKID_PCIE1_PLL_DCO_DIV2 35
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#define CLKID_PCIE1_PLL_OD 36
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#define CLKID_PCIE1_PLL 37
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#define CLKID_PCIE1_BGP 38
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#define CLKID_PCIE1_HCSL 39
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#define CLKID_PCIE1_HCSL_IN_PAD 40
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#define CLKID_PCIE1_CLK_IN 41
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#define CLKID_RTC_DUAL_CLKIN 42
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#define CLKID_RTC_DUAL_DIV 43
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#define CLKID_RTC_DUAL_MUX 44
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#define CLKID_RTC_DUAL 45
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#define CLKID_RTC_CLK 46
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#define CLKID_CECA_DUAL_CLKIN 47
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#define CLKID_CECA_DUAL_DIV 48
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#define CLKID_CECA_DUAL_MUX 49
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#define CLKID_CECA_DUAL 50
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#define CLKID_CECA_CLK 51
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#define CLKID_CECB_DUAL_CLKIN 52
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#define CLKID_CECB_DUAL_DIV 53
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#define CLKID_CECB_DUAL_MUX 54
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#define CLKID_CECB_DUAL 55
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#define CLKID_CECB_CLK 56
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#define CLKID_VAPB_MUX 57
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#define CLKID_VAPB_DIV 58
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#define CLKID_VAPB 59
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#define CLKID_GE2D_MUX 60
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#define CLKID_GE2D_DIV 61
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#define CLKID_GE2D 62
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#define CLKID_SC_MUX 63
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#define CLKID_SC_DIV 64
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#define CLKID_SC 65
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#define CLKID_VIDEO_SRC0_IN_MUX 66
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#define CLKID_VIDEO_SRC0_IN 67
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#define CLKID_VIDEO_SRC0_DIV 68
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#define CLKID_VIDEO_SRC0 69
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#define CLKID_VIDEO_SRC1_IN_MUX 70
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#define CLKID_VIDEO_SRC1_IN 71
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#define CLKID_VIDEO_SRC1_DIV 72
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#define CLKID_VIDEO_SRC1 73
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#define CLKID_VIDEO0_DIV1 74
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#define CLKID_VIDEO0_DIV2_GATE 75
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#define CLKID_VIDEO0_DIV2 76
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#define CLKID_VIDEO0_DIV4_GATE 77
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#define CLKID_VIDEO0_DIV4 78
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#define CLKID_VIDEO0_DIV6_GATE 79
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#define CLKID_VIDEO0_DIV6 80
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#define CLKID_VIDEO0_DIV12_GATE 81
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#define CLKID_VIDEO0_DIV12 82
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#define CLKID_VIDEO2_DIV1 83
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#define CLKID_VIDEO2_DIV2_GATE 84
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#define CLKID_VIDEO2_DIV2 85
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#define CLKID_VIDEO2_DIV4_GATE 86
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#define CLKID_VIDEO2_DIV4 87
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#define CLKID_VIDEO2_DIV6_GATE 88
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#define CLKID_VIDEO2_DIV6 89
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#define CLKID_VIDEO2_DIV12_GATE 90
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#define CLKID_VIDEO2_DIV12 91
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#define CLKID_ENCI_MUX 92
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#define CLKID_ENCI 93
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#define CLKID_ENCT_MUX 94
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#define CLKID_ENCT 95
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#define CLKID_ENCP_MUX 96
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#define CLKID_ENCP 97
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#define CLKID_ENCL_MUX 98
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#define CLKID_ENCL 99
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#define CLKID_VDAC_MUX 100
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#define CLKID_VDAC 101
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#define CLKID_ENC0_HDMITX_PIXEL_MUX 102
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#define CLKID_ENC0_HDMITX_PIXEL 103
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#define CLKID_ENC0_HDMITX_FE_MUX 104
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#define CLKID_ENC0_HDMITX_FE 105
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#define CLKID_ENC0_HDMITX_PNX_MUX 106
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#define CLKID_ENC0_HDMITX_PNX 107
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#define CLKID_HDMITX_PIXEL_MUX 108
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#define CLKID_HDMITX_PIXEL_DIV 109
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#define CLKID_HDMITX_PIXEL 110
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#define CLKID_HDMITX_FE_MUX 111
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#define CLKID_HDMITX_FE_DIV 112
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#define CLKID_HDMITX_FE 113
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#define CLKID_HDMITX_PNX_MUX 114
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#define CLKID_HDMITX_PNX_DIV 115
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#define CLKID_HDMITX_PNX 116
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#define CLKID_VPU_0_MUX 117
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#define CLKID_VPU_0_DIV 118
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#define CLKID_VPU_0 119
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#define CLKID_VPU_1_MUX 120
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#define CLKID_VPU_1_DIV 121
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#define CLKID_VPU_1 122
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#define CLKID_VPU 123
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#define CLKID_VPU_CLKB_TMP_MUX 124
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#define CLKID_VPU_CLKB_TMP_DIV 125
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#define CLKID_VPU_CLKB_TMP 126
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#define CLKID_VPU_CLKB_DIV 127
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#define CLKID_VPU_CLKB 128
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#define CLKID_VDIN_MEAS_MUX 129
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#define CLKID_VDIN_MEAS_DIV 130
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#define CLKID_VDIN_MEAS 131
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#define CLKID_VID_LOCK_MUX 132
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#define CLKID_VID_LOCK_DIV 133
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#define CLKID_VID_LOCK 134
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#define CLKID_CMPR_MUX 135
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#define CLKID_CMPR_DIV 136
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#define CLKID_CMPR 137
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#define CLKID_MALI_0_MUX 138
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#define CLKID_MALI_0_DIV 139
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#define CLKID_MALI_0 140
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#define CLKID_MALI_1_MUX 141
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#define CLKID_MALI_1_DIV 142
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#define CLKID_MALI_1 143
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#define CLKID_MALI 144
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#define CLKID_VDEC_0_MUX 145
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#define CLKID_VDEC_0_DIV 146
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#define CLKID_VDEC_0 147
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#define CLKID_VDEC_1_MUX 148
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#define CLKID_VDEC_1_DIV 149
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#define CLKID_VDEC_1 150
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#define CLKID_VDEC 151
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#define CLKID_HCODEC_0_MUX 152
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#define CLKID_HCODEC_0_DIV 153
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#define CLKID_HCODEC_0 154
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#define CLKID_HCODEC_1_MUX 155
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#define CLKID_HCODEC_1_DIV 156
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#define CLKID_HCODEC_1 157
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#define CLKID_HCODEC 158
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#define CLKID_HEVC_0_MUX 159
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#define CLKID_HEVC_0_DIV 160
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#define CLKID_HEVC_0 161
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#define CLKID_HEVC_1_MUX 162
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#define CLKID_HEVC_1_DIV 163
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#define CLKID_HEVC_1 164
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#define CLKID_HEVC 165
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#define CLKID_VC9000E_AXI_MUX 166
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#define CLKID_VC9000E_AXI_DIV 167
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#define CLKID_VC9000E_AXI 168
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#define CLKID_VC9000E_CORE_MUX 169
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#define CLKID_VC9000E_CORE_DIV 170
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#define CLKID_VC9000E_CORE 171
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#define CLKID_HDMITX_SYS_MUX 172
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#define CLKID_HDMITX_SYS_DIV 173
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#define CLKID_HDMITX_SYS 174
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#define CLKID_HDMITX_PRIF_MUX 175
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#define CLKID_HDMITX_PRIF_DIV 176
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#define CLKID_HDMITX_PRIF 177
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#define CLKID_HDMITX_200M_MUX 178
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#define CLKID_HDMITX_200M_DIV 179
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#define CLKID_HDMITX_200M 180
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#define CLKID_HDMITX_AUD_MUX 181
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#define CLKID_HDMITX_AUD_DIV 182
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#define CLKID_HDMITX_AUD 183
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#define CLKID_HTX_TMDS_MUX 184
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#define CLKID_HTX_TMDS_DIV 185
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#define CLKID_HTX_TMDS 186
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#define CLKID_NNA_0_MUX 187
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#define CLKID_NNA_0_DIV 188
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#define CLKID_NNA_0 189
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#define CLKID_NNA_1_MUX 190
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#define CLKID_NNA_1_DIV 191
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#define CLKID_NNA_1 192
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#define CLKID_NNA 193
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#define CLKID_PWM_A_MUX 194
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#define CLKID_PWM_A_DIV 195
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#define CLKID_PWM_A 196
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#define CLKID_PWM_B_MUX 197
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#define CLKID_PWM_B_DIV 198
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#define CLKID_PWM_B 199
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#define CLKID_PWM_C_MUX 200
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#define CLKID_PWM_C_DIV 201
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#define CLKID_PWM_C 202
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#define CLKID_PWM_D_MUX 203
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#define CLKID_PWM_D_DIV 204
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#define CLKID_PWM_D 205
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#define CLKID_PWM_E_MUX 206
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#define CLKID_PWM_E_DIV 207
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#define CLKID_PWM_E 208
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#define CLKID_PWM_F_MUX 209
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#define CLKID_PWM_F_DIV 210
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#define CLKID_PWM_F 211
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#define CLKID_PWM_G_MUX 212
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#define CLKID_PWM_G_DIV 213
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#define CLKID_PWM_G 214
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#define CLKID_PWM_H_MUX 215
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#define CLKID_PWM_H_DIV 216
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#define CLKID_PWM_H 217
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#define CLKID_PWM_I_MUX 218
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#define CLKID_PWM_I_DIV 219
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#define CLKID_PWM_I 220
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#define CLKID_PWM_J_MUX 221
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#define CLKID_PWM_J_DIV 222
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#define CLKID_PWM_J 223
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#define CLKID_SPICC0_MUX 224
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#define CLKID_SPICC0_DIV 225
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#define CLKID_SPICC0 226
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#define CLKID_SPICC1_MUX 227
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#define CLKID_SPICC1_DIV 228
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#define CLKID_SPICC1 229
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#define CLKID_SPICC2_MUX 230
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#define CLKID_SPICC2_DIV 231
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#define CLKID_SPICC2 232
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#define CLKID_SD_EMMC_A_MUX 233
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#define CLKID_SD_EMMC_A_DIV 234
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#define CLKID_SD_EMMC_A 235
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#define CLKID_SD_EMMC_B_MUX 236
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#define CLKID_SD_EMMC_B_DIV 237
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#define CLKID_SD_EMMC_B 238
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#define CLKID_SD_EMMC_C_MUX 239
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#define CLKID_SD_EMMC_C_DIV 240
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#define CLKID_SD_EMMC_C 241
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#define CLKID_ETH_CLK_RMII_MUX 242
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#define CLKID_ETH_CLK_RMII_DIV 243
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#define CLKID_ETH_CLK_RMII 244
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#define CLKID_ETH_CLK125M_DIV 245
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#define CLKID_ETH_CLK125M 246
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#define CLKID_TS_DIV 247
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#define CLKID_TS 248
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#define CLKID_CDAC_MUX 249
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#define CLKID_CDAC_DIV 250
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#define CLKID_CDAC 251
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#define CLKID_SAR_ADC_MUX 252
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#define CLKID_SAR_ADC_DIV 253
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#define CLKID_SAR_ADC 254
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#define CLKID_USB_250M_MUX 255
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#define CLKID_USB_250M_DIV 256
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#define CLKID_USB_250M 257
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#define CLKID_PCIE_400M_MUX 258
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#define CLKID_PCIE_400M_DIV 259
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#define CLKID_PCIE_400M 260
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#define CLKID_PCIE_MUX 261
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#define CLKID_PCIE_DIV 262
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#define CLKID_PCIE 263
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#define CLKID_PCIE_TL_MUX 264
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#define CLKID_PCIE_TL_DIV 265
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#define CLKID_PCIE_TL 266
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#define CLKID_CLK_24M_IN 267
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#define CLKID_CLK_24M_DIV 268
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#define CLKID_CLK_12_24M 269
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#define CLKID_CLK_25M_DIV 270
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#define CLKID_CLK_25M 271
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#define CLKID_GEN_MUX 272
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#define CLKID_GEN_DIV 273
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#define CLKID_GEN 274
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#define CLKID_SYS_DDR 275
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#define CLKID_SYS_ETHPHY 276
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#define CLKID_SYS_GPU 277
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#define CLKID_SYS_AOCPU 278
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#define CLKID_SYS_AUCPU 279
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#define CLKID_SYS_DEWARPC 280
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#define CLKID_SYS_DEWARPB 281
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#define CLKID_SYS_DEWARPA 282
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#define CLKID_SYS_AMPIPE_NAND 283
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#define CLKID_SYS_AMPIPE_ETH 284
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#define CLKID_SYS_AM2AXI0 285
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#define CLKID_SYS_SD_EMMC_A 286
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#define CLKID_SYS_SD_EMMC_B 287
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#define CLKID_SYS_SD_EMMC_C 288
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#define CLKID_SYS_VC9000E 289
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#define CLKID_SYS_ACODEC 290
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#define CLKID_SYS_SPIFC 291
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#define CLKID_SYS_MSR_CLK 292
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#define CLKID_SYS_IR_CTRL 293
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#define CLKID_SYS_AUDIO 294
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#define CLKID_SYS_DOS 295
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#define CLKID_SYS_ETH 296
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#define CLKID_SYS_UART_A 297
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#define CLKID_SYS_UART_B 298
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#define CLKID_SYS_UART_C 299
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#define CLKID_SYS_UART_D 300
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#define CLKID_SYS_UART_E 301
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#define CLKID_SYS_UART_F 302
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#define CLKID_SYS_SPICC2 303
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#define CLKID_SYS_TS_A55 304
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#define CLKID_SYS_GE2D 305
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#define CLKID_SYS_SPICC0 306
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#define CLKID_SYS_SPICC1 307
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#define CLKID_SYS_SMART_CARD 308
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#define CLKID_SYS_PCIE 309
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#define CLKID_SYS_PCIEPHY 310
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#define CLKID_SYS_USBGENERAL 311
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#define CLKID_SYS_PCIEPHY0 312
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#define CLKID_SYS_PCIEPHY1 313
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#define CLKID_SYS_PCIEPHY2 314
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#define CLKID_SYS_I2C_M_A 315
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#define CLKID_SYS_I2C_M_B 316
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#define CLKID_SYS_I2C_M_C 317
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#define CLKID_SYS_I2C_M_D 318
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#define CLKID_SYS_I2C_M_E 319
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#define CLKID_SYS_I2C_M_F 320
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#define CLKID_SYS_I2C_S_A 321
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#define CLKID_SYS_CMPR 322
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#define CLKID_SYS_MMC_PCLK 323
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#define CLKID_SYS_HDMITX_PCLK 324
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#define CLKID_SYS_HDMI20_AES_CLK 325
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#define CLKID_SYS_PCLK_SYS_CPU_APB 326
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#define CLKID_SYS_CEC 327
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#define CLKID_SYS_VPU_INTR 328
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#define CLKID_SYS_SAR_ADC 329
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#define CLKID_SYS_GIC 330
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#define CLKID_SYS_TS_GPU 331
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#define CLKID_SYS_TS_NNA 332
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#define CLKID_SYS_TS_VPU 333
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#define CLKID_SYS_TS_DOS 334
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#define CLKID_SYS_PWM_AB 335
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#define CLKID_SYS_PWM_CD 336
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#define CLKID_SYS_PWM_EF 337
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#define CLKID_SYS_PWM_GH 338
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#define CLKID_SYS_PWM_IJ 339
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S5_CLKC_H */
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