/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S5_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_S5_CLKC_H

#define CLKID_SYS2_PLL                            0
#define CLKID_GP0_PLL                             1
#define CLKID_GP2_PLL                             2
#define CLKID_HIFI_PLL                            3
#define CLKID_HIFI1_PLL                           4
#define CLKID_FPLL_DCO                            5
#define CLKID_NNA_PLL                             6
#define CLKID_PCIE_PLL_DCO                        7
#define CLKID_PCIE1_PLL_DCO                       8
#define CLKID_FCLK_50M_EN                         9
#define CLKID_FCLK_50M                            10
#define CLKID_FCLK_DIV2_DIV                       11
#define CLKID_FCLK_DIV2                           12
#define CLKID_FCLK_DIV2P5_DIV                     13
#define CLKID_FCLK_DIV2P5                         14
#define CLKID_FCLK_DIV3_DIV                       15
#define CLKID_FCLK_DIV3                           16
#define CLKID_FCLK_DIV4_DIV                       17
#define CLKID_FCLK_DIV4                           18
#define CLKID_FCLK_DIV5_DIV                       19
#define CLKID_FCLK_DIV5                           20
#define CLKID_FCLK_DIV7_DIV                       21
#define CLKID_FCLK_DIV7                           22
#define CLKID_FPLL_TMDS_OD                        23
#define CLKID_FPLL_TMDS_OD1                       24
#define CLKID_FPLL_TMDS                           25
#define CLKID_FPLL_PIXEL                          26
#define CLKID_NNA_PLL_AUDIO                       27
#define CLKID_PCIE_PLL_DCO_DIV2                   28
#define CLKID_PCIE_PLL_OD                         29
#define CLKID_PCIE_PLL                            30
#define CLKID_PCIE_BGP                            31
#define CLKID_PCIE_HCSL                           32
#define CLKID_PCIE_HCSL_IN_PAD                    33
#define CLKID_PCIE_CLK_IN                         34
#define CLKID_PCIE1_PLL_DCO_DIV2                  35
#define CLKID_PCIE1_PLL_OD                        36
#define CLKID_PCIE1_PLL                           37
#define CLKID_PCIE1_BGP                           38
#define CLKID_PCIE1_HCSL                          39
#define CLKID_PCIE1_HCSL_IN_PAD                   40
#define CLKID_PCIE1_CLK_IN                        41
#define CLKID_RTC_DUAL_CLKIN                      42
#define CLKID_RTC_DUAL_DIV                        43
#define CLKID_RTC_DUAL_MUX                        44
#define CLKID_RTC_DUAL                            45
#define CLKID_RTC_CLK                             46
#define CLKID_CECA_DUAL_CLKIN                     47
#define CLKID_CECA_DUAL_DIV                       48
#define CLKID_CECA_DUAL_MUX                       49
#define CLKID_CECA_DUAL                           50
#define CLKID_CECA_CLK                            51
#define CLKID_CECB_DUAL_CLKIN                     52
#define CLKID_CECB_DUAL_DIV                       53
#define CLKID_CECB_DUAL_MUX                       54
#define CLKID_CECB_DUAL                           55
#define CLKID_CECB_CLK                            56
#define CLKID_VAPB_MUX                            57
#define CLKID_VAPB_DIV                            58
#define CLKID_VAPB                                59
#define CLKID_GE2D_MUX                            60
#define CLKID_GE2D_DIV                            61
#define CLKID_GE2D                                62
#define CLKID_SC_MUX                              63
#define CLKID_SC_DIV                              64
#define CLKID_SC                                  65
#define CLKID_VIDEO_SRC0_IN_MUX                   66
#define CLKID_VIDEO_SRC0_IN                       67
#define CLKID_VIDEO_SRC0_DIV                      68
#define CLKID_VIDEO_SRC0                          69
#define CLKID_VIDEO_SRC1_IN_MUX                   70
#define CLKID_VIDEO_SRC1_IN                       71
#define CLKID_VIDEO_SRC1_DIV                      72
#define CLKID_VIDEO_SRC1                          73
#define CLKID_VIDEO0_DIV1                         74
#define CLKID_VIDEO0_DIV2_GATE                    75
#define CLKID_VIDEO0_DIV2                         76
#define CLKID_VIDEO0_DIV4_GATE                    77
#define CLKID_VIDEO0_DIV4                         78
#define CLKID_VIDEO0_DIV6_GATE                    79
#define CLKID_VIDEO0_DIV6                         80
#define CLKID_VIDEO0_DIV12_GATE                   81
#define CLKID_VIDEO0_DIV12                        82
#define CLKID_VIDEO2_DIV1                         83
#define CLKID_VIDEO2_DIV2_GATE                    84
#define CLKID_VIDEO2_DIV2                         85
#define CLKID_VIDEO2_DIV4_GATE                    86
#define CLKID_VIDEO2_DIV4                         87
#define CLKID_VIDEO2_DIV6_GATE                    88
#define CLKID_VIDEO2_DIV6                         89
#define CLKID_VIDEO2_DIV12_GATE                   90
#define CLKID_VIDEO2_DIV12                        91
#define CLKID_ENCI_MUX                            92
#define CLKID_ENCI                                93
#define CLKID_ENCT_MUX                            94
#define CLKID_ENCT                                95
#define CLKID_ENCP_MUX                            96
#define CLKID_ENCP                                97
#define CLKID_ENCL_MUX                            98
#define CLKID_ENCL                                99
#define CLKID_VDAC_MUX                            100
#define CLKID_VDAC                                101
#define CLKID_ENC0_HDMITX_PIXEL_MUX               102
#define CLKID_ENC0_HDMITX_PIXEL                   103
#define CLKID_ENC0_HDMITX_FE_MUX                  104
#define CLKID_ENC0_HDMITX_FE                      105
#define CLKID_ENC0_HDMITX_PNX_MUX                 106
#define CLKID_ENC0_HDMITX_PNX                     107
#define CLKID_HDMITX_PIXEL_MUX                    108
#define CLKID_HDMITX_PIXEL_DIV                    109
#define CLKID_HDMITX_PIXEL                        110
#define CLKID_HDMITX_FE_MUX                       111
#define CLKID_HDMITX_FE_DIV                       112
#define CLKID_HDMITX_FE                           113
#define CLKID_HDMITX_PNX_MUX                      114
#define CLKID_HDMITX_PNX_DIV                      115
#define CLKID_HDMITX_PNX                          116
#define CLKID_VPU_0_MUX                           117
#define CLKID_VPU_0_DIV                           118
#define CLKID_VPU_0                               119
#define CLKID_VPU_1_MUX                           120
#define CLKID_VPU_1_DIV                           121
#define CLKID_VPU_1                               122
#define CLKID_VPU                                 123
#define CLKID_VPU_CLKB_TMP_MUX                    124
#define CLKID_VPU_CLKB_TMP_DIV                    125
#define CLKID_VPU_CLKB_TMP                        126
#define CLKID_VPU_CLKB_DIV                        127
#define CLKID_VPU_CLKB                            128
#define CLKID_VDIN_MEAS_MUX                       129
#define CLKID_VDIN_MEAS_DIV                       130
#define CLKID_VDIN_MEAS                           131
#define CLKID_VID_LOCK_MUX                        132
#define CLKID_VID_LOCK_DIV                        133
#define CLKID_VID_LOCK                            134
#define CLKID_CMPR_MUX                            135
#define CLKID_CMPR_DIV                            136
#define CLKID_CMPR                                137
#define CLKID_MALI_0_MUX                          138
#define CLKID_MALI_0_DIV                          139
#define CLKID_MALI_0                              140
#define CLKID_MALI_1_MUX                          141
#define CLKID_MALI_1_DIV                          142
#define CLKID_MALI_1                              143
#define CLKID_MALI                                144
#define CLKID_VDEC_0_MUX                          145
#define CLKID_VDEC_0_DIV                          146
#define CLKID_VDEC_0                              147
#define CLKID_VDEC_1_MUX                          148
#define CLKID_VDEC_1_DIV                          149
#define CLKID_VDEC_1                              150
#define CLKID_VDEC                                151
#define CLKID_HCODEC_0_MUX                        152
#define CLKID_HCODEC_0_DIV                        153
#define CLKID_HCODEC_0                            154
#define CLKID_HCODEC_1_MUX                        155
#define CLKID_HCODEC_1_DIV                        156
#define CLKID_HCODEC_1                            157
#define CLKID_HCODEC                              158
#define CLKID_HEVC_0_MUX                          159
#define CLKID_HEVC_0_DIV                          160
#define CLKID_HEVC_0                              161
#define CLKID_HEVC_1_MUX                          162
#define CLKID_HEVC_1_DIV                          163
#define CLKID_HEVC_1                              164
#define CLKID_HEVC                                165
#define CLKID_VC9000E_AXI_MUX                     166
#define CLKID_VC9000E_AXI_DIV                     167
#define CLKID_VC9000E_AXI                         168
#define CLKID_VC9000E_CORE_MUX                    169
#define CLKID_VC9000E_CORE_DIV                    170
#define CLKID_VC9000E_CORE                        171
#define CLKID_HDMITX_SYS_MUX                      172
#define CLKID_HDMITX_SYS_DIV                      173
#define CLKID_HDMITX_SYS                          174
#define CLKID_HDMITX_PRIF_MUX                     175
#define CLKID_HDMITX_PRIF_DIV                     176
#define CLKID_HDMITX_PRIF                         177
#define CLKID_HDMITX_200M_MUX                     178
#define CLKID_HDMITX_200M_DIV                     179
#define CLKID_HDMITX_200M                         180
#define CLKID_HDMITX_AUD_MUX                      181
#define CLKID_HDMITX_AUD_DIV                      182
#define CLKID_HDMITX_AUD                          183
#define CLKID_HTX_TMDS_MUX                        184
#define CLKID_HTX_TMDS_DIV                        185
#define CLKID_HTX_TMDS                            186
#define CLKID_NNA_0_MUX                           187
#define CLKID_NNA_0_DIV                           188
#define CLKID_NNA_0                               189
#define CLKID_NNA_1_MUX                           190
#define CLKID_NNA_1_DIV                           191
#define CLKID_NNA_1                               192
#define CLKID_NNA                                 193
#define CLKID_PWM_A_MUX                           194
#define CLKID_PWM_A_DIV                           195
#define CLKID_PWM_A                               196
#define CLKID_PWM_B_MUX                           197
#define CLKID_PWM_B_DIV                           198
#define CLKID_PWM_B                               199
#define CLKID_PWM_C_MUX                           200
#define CLKID_PWM_C_DIV                           201
#define CLKID_PWM_C                               202
#define CLKID_PWM_D_MUX                           203
#define CLKID_PWM_D_DIV                           204
#define CLKID_PWM_D                               205
#define CLKID_PWM_E_MUX                           206
#define CLKID_PWM_E_DIV                           207
#define CLKID_PWM_E                               208
#define CLKID_PWM_F_MUX                           209
#define CLKID_PWM_F_DIV                           210
#define CLKID_PWM_F                               211
#define CLKID_PWM_G_MUX                           212
#define CLKID_PWM_G_DIV                           213
#define CLKID_PWM_G                               214
#define CLKID_PWM_H_MUX                           215
#define CLKID_PWM_H_DIV                           216
#define CLKID_PWM_H                               217
#define CLKID_PWM_I_MUX                           218
#define CLKID_PWM_I_DIV                           219
#define CLKID_PWM_I                               220
#define CLKID_PWM_J_MUX                           221
#define CLKID_PWM_J_DIV                           222
#define CLKID_PWM_J                               223
#define CLKID_SPICC0_MUX                          224
#define CLKID_SPICC0_DIV                          225
#define CLKID_SPICC0                              226
#define CLKID_SPICC1_MUX                          227
#define CLKID_SPICC1_DIV                          228
#define CLKID_SPICC1                              229
#define CLKID_SPICC2_MUX                          230
#define CLKID_SPICC2_DIV                          231
#define CLKID_SPICC2                              232
#define CLKID_SD_EMMC_A_MUX                       233
#define CLKID_SD_EMMC_A_DIV                       234
#define CLKID_SD_EMMC_A                           235
#define CLKID_SD_EMMC_B_MUX                       236
#define CLKID_SD_EMMC_B_DIV                       237
#define CLKID_SD_EMMC_B                           238
#define CLKID_SD_EMMC_C_MUX                       239
#define CLKID_SD_EMMC_C_DIV                       240
#define CLKID_SD_EMMC_C                           241
#define CLKID_ETH_CLK_RMII_MUX                    242
#define CLKID_ETH_CLK_RMII_DIV                    243
#define CLKID_ETH_CLK_RMII                        244
#define CLKID_ETH_CLK125M_DIV                     245
#define CLKID_ETH_CLK125M                         246
#define CLKID_TS_DIV                              247
#define CLKID_TS                                  248
#define CLKID_CDAC_MUX                            249
#define CLKID_CDAC_DIV                            250
#define CLKID_CDAC                                251
#define CLKID_SAR_ADC_MUX                         252
#define CLKID_SAR_ADC_DIV                         253
#define CLKID_SAR_ADC                             254
#define CLKID_USB_250M_MUX                        255
#define CLKID_USB_250M_DIV                        256
#define CLKID_USB_250M                            257
#define CLKID_PCIE_400M_MUX                       258
#define CLKID_PCIE_400M_DIV                       259
#define CLKID_PCIE_400M                           260
#define CLKID_PCIE_MUX                            261
#define CLKID_PCIE_DIV                            262
#define CLKID_PCIE                                263
#define CLKID_PCIE_TL_MUX                         264
#define CLKID_PCIE_TL_DIV                         265
#define CLKID_PCIE_TL                             266
#define CLKID_CLK_24M_IN                          267
#define CLKID_CLK_24M_DIV                         268
#define CLKID_CLK_12_24M                          269
#define CLKID_CLK_25M_DIV                         270
#define CLKID_CLK_25M                             271
#define CLKID_GEN_MUX                             272
#define CLKID_GEN_DIV                             273
#define CLKID_GEN                                 274
#define CLKID_SYS_DDR                             275
#define CLKID_SYS_ETHPHY                          276
#define CLKID_SYS_GPU                             277
#define CLKID_SYS_AOCPU                           278
#define CLKID_SYS_AUCPU                           279
#define CLKID_SYS_DEWARPC                         280
#define CLKID_SYS_DEWARPB                         281
#define CLKID_SYS_DEWARPA                         282
#define CLKID_SYS_AMPIPE_NAND                     283
#define CLKID_SYS_AMPIPE_ETH                      284
#define CLKID_SYS_AM2AXI0                         285
#define CLKID_SYS_SD_EMMC_A                       286
#define CLKID_SYS_SD_EMMC_B                       287
#define CLKID_SYS_SD_EMMC_C                       288
#define CLKID_SYS_VC9000E                         289
#define CLKID_SYS_ACODEC                          290
#define CLKID_SYS_SPIFC                           291
#define CLKID_SYS_MSR_CLK                         292
#define CLKID_SYS_IR_CTRL                         293
#define CLKID_SYS_AUDIO                           294
#define CLKID_SYS_DOS                             295
#define CLKID_SYS_ETH                             296
#define CLKID_SYS_UART_A                          297
#define CLKID_SYS_UART_B                          298
#define CLKID_SYS_UART_C                          299
#define CLKID_SYS_UART_D                          300
#define CLKID_SYS_UART_E                          301
#define CLKID_SYS_UART_F                          302
#define CLKID_SYS_SPICC2                          303
#define CLKID_SYS_TS_A55                          304
#define CLKID_SYS_GE2D                            305
#define CLKID_SYS_SPICC0                          306
#define CLKID_SYS_SPICC1                          307
#define CLKID_SYS_SMART_CARD                      308
#define CLKID_SYS_PCIE                            309
#define CLKID_SYS_PCIEPHY                         310
#define CLKID_SYS_USBGENERAL                      311
#define CLKID_SYS_PCIEPHY0                        312
#define CLKID_SYS_PCIEPHY1                        313
#define CLKID_SYS_PCIEPHY2                        314
#define CLKID_SYS_I2C_M_A                         315
#define CLKID_SYS_I2C_M_B                         316
#define CLKID_SYS_I2C_M_C                         317
#define CLKID_SYS_I2C_M_D                         318
#define CLKID_SYS_I2C_M_E                         319
#define CLKID_SYS_I2C_M_F                         320
#define CLKID_SYS_I2C_S_A                         321
#define CLKID_SYS_CMPR                            322
#define CLKID_SYS_MMC_PCLK                        323
#define CLKID_SYS_HDMITX_PCLK                     324
#define CLKID_SYS_HDMI20_AES_CLK                  325
#define CLKID_SYS_PCLK_SYS_CPU_APB                326
#define CLKID_SYS_CEC                             327
#define CLKID_SYS_VPU_INTR                        328
#define CLKID_SYS_SAR_ADC                         329
#define CLKID_SYS_GIC                             330
#define CLKID_SYS_TS_GPU                          331
#define CLKID_SYS_TS_NNA                          332
#define CLKID_SYS_TS_VPU                          333
#define CLKID_SYS_TS_DOS                          334
#define CLKID_SYS_PWM_AB                          335
#define CLKID_SYS_PWM_CD                          336
#define CLKID_SYS_PWM_EF                          337
#define CLKID_SYS_PWM_GH                          338
#define CLKID_SYS_PWM_IJ                          339

#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S5_CLKC_H */