342 lines
17 KiB
C
342 lines
17 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C5_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_C5_CLKC_H
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#define CLKID_GP0_PLL 0
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#define CLKID_HIFI_PLL 1
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#define CLKID_DSI_PLL 2
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#define CLKID_MCLK_PLL 3
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#define CLKID_MCLK1_PLL 4
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#define CLKID_FCLK_DIV50M_DIV 5
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#define CLKID_FCLK_DIV50M 6
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#define CLKID_FCLK_DIV2_DIV 7
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#define CLKID_FCLK_DIV2 8
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#define CLKID_FCLK_DIV2P5_DIV 9
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#define CLKID_FCLK_DIV2P5 10
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#define CLKID_FCLK_DIV3_DIV 11
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#define CLKID_FCLK_DIV3 12
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#define CLKID_FCLK_DIV4_DIV 13
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#define CLKID_FCLK_DIV4 14
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#define CLKID_FCLK_DIV5_DIV 15
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#define CLKID_FCLK_DIV5 16
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#define CLKID_FCLK_DIV7_DIV 17
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#define CLKID_FCLK_DIV7 18
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#define CLKID_MCLK_0_PRE_DIV 19
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#define CLKID_MCLK_0_PRE 20
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#define CLKID_MCLK_0_MUX 21
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#define CLKID_MCLK_0_DIV 22
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#define CLKID_MCLK_0 23
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#define CLKID_MCLK_1_PRE_DIV 24
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#define CLKID_MCLK_1_PRE 25
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#define CLKID_MCLK_1_MUX 26
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#define CLKID_MCLK_1_DIV 27
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#define CLKID_MCLK_1 28
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#define CLKID_MCLK1_0_PRE_DIV 29
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#define CLKID_MCLK1_0_PRE 30
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#define CLKID_MCLK1_0_MUX 31
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#define CLKID_MCLK1_0_DIV 32
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#define CLKID_MCLK1_0 33
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#define CLKID_MCLK1_1_PRE_DIV 34
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#define CLKID_MCLK1_1_PRE 35
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#define CLKID_MCLK1_1_MUX 36
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#define CLKID_MCLK1_1_DIV 37
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#define CLKID_MCLK1_1 38
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#define CLKID_RTC_DUAL_CLKIN 39
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#define CLKID_RTC_DUAL_DIV 40
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#define CLKID_RTC_DUAL_MUX 41
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#define CLKID_RTC_DUAL 42
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#define CLKID_RTC_CLK 43
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#define CLKID_SAR_ADC_MUX 44
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#define CLKID_SAR_ADC_DIV 45
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#define CLKID_SAR_ADC 46
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#define CLKID_PWM_C_MUX 47
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#define CLKID_PWM_C_DIV 48
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#define CLKID_PWM_C 49
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#define CLKID_PWM_D_MUX 50
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#define CLKID_PWM_D_DIV 51
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#define CLKID_PWM_D 52
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#define CLKID_PWM_E_MUX 53
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#define CLKID_PWM_E_DIV 54
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#define CLKID_PWM_E 55
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#define CLKID_PWM_F_MUX 56
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#define CLKID_PWM_F_DIV 57
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#define CLKID_PWM_F 58
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#define CLKID_PWM_G_MUX 59
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#define CLKID_PWM_G_DIV 60
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#define CLKID_PWM_G 61
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#define CLKID_PWM_H_MUX 62
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#define CLKID_PWM_H_DIV 63
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#define CLKID_PWM_H 64
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#define CLKID_PWM_I_MUX 65
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#define CLKID_PWM_I_DIV 66
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#define CLKID_PWM_I 67
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#define CLKID_PWM_J_MUX 68
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#define CLKID_PWM_J_DIV 69
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#define CLKID_PWM_J 70
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#define CLKID_PWM_K_MUX 71
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#define CLKID_PWM_K_DIV 72
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#define CLKID_PWM_K 73
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#define CLKID_PWM_L_MUX 74
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#define CLKID_PWM_L_DIV 75
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#define CLKID_PWM_L 76
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#define CLKID_PWM_M_MUX 77
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#define CLKID_PWM_M_DIV 78
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#define CLKID_PWM_M 79
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#define CLKID_PWM_N_MUX 80
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#define CLKID_PWM_N_DIV 81
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#define CLKID_PWM_N 82
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#define CLKID_PWM_O_MUX 83
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#define CLKID_PWM_O_DIV 84
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#define CLKID_PWM_O 85
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#define CLKID_PWM_P_MUX 86
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#define CLKID_PWM_P_DIV 87
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#define CLKID_PWM_P 88
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#define CLKID_PWM_Q_MUX 89
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#define CLKID_PWM_Q_DIV 90
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#define CLKID_PWM_Q 91
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#define CLKID_PWM_R_MUX 92
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#define CLKID_PWM_R_DIV 93
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#define CLKID_PWM_R 94
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#define CLKID_PWM_S_MUX 95
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#define CLKID_PWM_S_DIV 96
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#define CLKID_PWM_S 97
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#define CLKID_PWM_T_MUX 98
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#define CLKID_PWM_T_DIV 99
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#define CLKID_PWM_T 100
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#define CLKID_SPISG0_MUX 101
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#define CLKID_SPISG0_DIV 102
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#define CLKID_SPISG0 103
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#define CLKID_SPISG1_MUX 104
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#define CLKID_SPISG1_DIV 105
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#define CLKID_SPISG1 106
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#define CLKID_SPISG2_MUX 107
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#define CLKID_SPISG2_DIV 108
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#define CLKID_SPISG2 109
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#define CLKID_SD_EMMC_A_MUX 110
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#define CLKID_SD_EMMC_A_DIV 111
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#define CLKID_SD_EMMC_A 112
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#define CLKID_SD_EMMC_B_MUX 113
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#define CLKID_SD_EMMC_B_DIV 114
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#define CLKID_SD_EMMC_B 115
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#define CLKID_SD_EMMC_C_MUX 116
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#define CLKID_SD_EMMC_C_DIV 117
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#define CLKID_SD_EMMC_C 118
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#define CLKID_ETH_RMII_DIV 119
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#define CLKID_ETH_RMII 120
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#define CLKID_ETH_125M_DIV 121
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#define CLKID_ETH_125M 122
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#define CLKID_TS_DIV 123
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#define CLKID_TS 124
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#define CLKID_CAN0_PE_MUX 125
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#define CLKID_CAN0_PE_DIV 126
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#define CLKID_CAN0_PE 127
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#define CLKID_CAN1_PE_MUX 128
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#define CLKID_CAN1_PE_DIV 129
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#define CLKID_CAN1_PE 130
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#define CLKID_CAN0_FILTER_MUX 131
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#define CLKID_CAN0_FILTER_DIV 132
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#define CLKID_CAN0_FILTER 133
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#define CLKID_CAN1_FILTER_MUX 134
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#define CLKID_CAN1_FILTER_DIV 135
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#define CLKID_CAN1_FILTER 136
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#define CLKID_I3C_MUX 137
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#define CLKID_I3C_DIV 138
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#define CLKID_I3C 139
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#define CLKID_USB_48M_MUX 140
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#define CLKID_USB_48M_DIV 141
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#define CLKID_USB_48M 142
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#define CLKID_USB_250M_MUX 143
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#define CLKID_USB_250M_DIV 144
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#define CLKID_USB_250M 145
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#define CLKID_PCIE0_TL_MUX 146
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#define CLKID_PCIE0_TL_DIV 147
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#define CLKID_PCIE0_TL 148
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#define CLKID_AMFC_MUX 149
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#define CLKID_AMFC_DIV 150
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#define CLKID_AMFC 151
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#define CLKID_CMPR_MUX 152
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#define CLKID_CMPR_DIV 153
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#define CLKID_CMPR 154
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#define CLKID_VGE_MUX 155
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#define CLKID_VGE_DIV 156
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#define CLKID_VGE 157
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#define CLKID_CVE_MUX 158
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#define CLKID_CVE_DIV 159
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#define CLKID_CVE 160
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#define CLKID_DEWARPA_MUX 161
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#define CLKID_DEWARPA_DIV 162
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#define CLKID_DEWARPA 163
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#define CLKID_NNA_CORE_MUX 164
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#define CLKID_NNA_CORE_DIV 165
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#define CLKID_NNA_CORE 166
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#define CLKID_NNA2_CORE_MUX 167
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#define CLKID_NNA2_CORE_DIV 168
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#define CLKID_NNA2_CORE 169
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#define CLKID_VAPB_0_MUX 170
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#define CLKID_VAPB_0_DIV 171
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#define CLKID_VAPB_0 172
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#define CLKID_VAPB_1_MUX 173
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#define CLKID_VAPB_1_DIV 174
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#define CLKID_VAPB_1 175
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#define CLKID_VAPB 176
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#define CLKID_GE2D 177
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#define CLKID_ISP0_MUX 178
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#define CLKID_ISP0_DIV 179
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#define CLKID_ISP0 180
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#define CLKID_AI_ISP_MUX 181
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#define CLKID_AI_ISP_DIV 182
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#define CLKID_AI_ISP 183
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#define CLKID_GLB_MUX 184
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#define CLKID_GLB_DIV 185
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#define CLKID_GLB 186
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#define CLKID_CSIPHY0_MUX 187
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#define CLKID_CSIPHY0_DIV 188
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#define CLKID_CSIPHY0 189
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#define CLKID_HEVCF_0_MUX 190
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#define CLKID_HEVCF_0_DIV 191
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#define CLKID_HEVCF_0 192
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#define CLKID_HEVCF_1_MUX 193
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#define CLKID_HEVCF_1_DIV 194
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#define CLKID_HEVCF_1 195
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#define CLKID_HEVCF 196
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#define CLKID_HCODEC_0_MUX 197
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#define CLKID_HCODEC_0_DIV 198
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#define CLKID_HCODEC_0 199
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#define CLKID_HCODEC_1_MUX 200
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#define CLKID_HCODEC_1_DIV 201
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#define CLKID_HCODEC_1 202
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#define CLKID_HCODEC 203
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#define CLKID_VOUT_MCLK_MUX 204
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#define CLKID_VOUT_MCLK_DIV 205
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#define CLKID_VOUT_MCLK 206
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#define CLKID_VOUT_VENC_MCLK_MUX 207
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#define CLKID_VOUT_VENC_MCLK_DIV 208
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#define CLKID_VOUT_VENC_MCLK 209
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#define CLKID_DSI_MEAS_MUX 210
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#define CLKID_DSI_MEAS_DIV 211
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#define CLKID_DSI_MEAS 212
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#define CLKID_CLK_24M_IN 213
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#define CLKID_CLK_12M_DIV 214
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#define CLKID_CLK_12_24M 215
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#define CLKID_GEN_MUX 216
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#define CLKID_GEN_DIV 217
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#define CLKID_GEN 218
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#define CLKID_SYS_DOS 219
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#define CLKID_SYS_TAHOE 220
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#define CLKID_SYS_MIPI_DSI 221
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#define CLKID_SYS_ETH_PHY 222
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#define CLKID_SYS_AMFC 223
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#define CLKID_SYS_NNA 224
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#define CLKID_SYS_PCIE 225
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#define CLKID_SYS_PCIEMAC 226
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#define CLKID_SYS_GLB 227
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#define CLKID_SYS_MIPI_DSI_PHY 228
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#define CLKID_SYS_SD_EMMC_A 229
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#define CLKID_SYS_SD_EMMC_B 230
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#define CLKID_SYS_SD_EMMC_C 231
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#define CLKID_SYS_ACODEC 232
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#define CLKID_SYS_MIPI_ISP 233
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#define CLKID_SYS_MSR_CLK 234
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#define CLKID_SYS_AUDIO 235
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#define CLKID_SYS_ETH_MAC 236
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#define CLKID_SYS_UART_B 237
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#define CLKID_SYS_UART_C 238
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#define CLKID_SYS_UART_D 239
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#define CLKID_SYS_UART_E 240
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#define CLKID_SYS_UART_F 241
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#define CLKID_SYS_ETH_AXI 242
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#define CLKID_SYS_TS_ISP 243
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#define CLKID_SYS_TS_NNA 244
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#define CLKID_SYS_TS_PLL 245
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#define CLKID_SYS_PWM_M 246
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#define CLKID_SYS_PWM_N 247
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#define CLKID_SYS_CVE 248
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#define CLKID_SYS_GE2D 249
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#define CLKID_SYS_SPISG0 250
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#define CLKID_SYS_USB_U2H 251
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#define CLKID_SYS_USB_U3DRD 252
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#define CLKID_SYS_PERIPH 253
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#define CLKID_SYS_PWM_H 254
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#define CLKID_SYS_PWM_I 255
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#define CLKID_SYS_PWM_J 256
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#define CLKID_SYS_PWM_K 257
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#define CLKID_SYS_PWM_L 258
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#define CLKID_SYS_I2C_M_C 259
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#define CLKID_SYS_I2C_M_D 260
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#define CLKID_SYS_I2C_M_E 261
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#define CLKID_SYS_I2C_M_F 262
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#define CLKID_SYS_I2C_M_G 263
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#define CLKID_SYS_PIO 264
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#define CLKID_SYS_PWM_G 265
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#define CLKID_SYS_PWM_F 266
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#define CLKID_SYS_PWM_E 267
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#define CLKID_SYS_PWM_D 268
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#define CLKID_SYS_PWM_C 269
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#define CLKID_SYS_MMC_APB 270
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#define CLKID_SYS_CPU_APB 271
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#define CLKID_SYS_PP_DMA 272
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#define CLKID_SYS_PP_WRAPPER 273
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#define CLKID_SYS_CSI2_PHY0_APB 274
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#define CLKID_SYS_AUX_ADC 275
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#define CLKID_SYS_GIC 276
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#define CLKID_SYS_PWM_T 277
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#define CLKID_SYS_PWM_S 278
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#define CLKID_SYS_PWM_R 279
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#define CLKID_SYS_PWM_Q 280
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#define CLKID_SYS_PWM_P 281
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#define CLKID_SYS_PWM_O 282
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#define CLKID_SYS_CAN0 283
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#define CLKID_SYS_CAN1 284
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#define CLKID_SYS_I3C 285
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#define CLKID_AXI_SYS_NIC 286
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#define CLKID_AXI_RAMA 287
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/**
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* ao clk ids
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*/
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#define CLKID_OSC_32M_EN 0
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#define CLKID_AO_ROUGH_32K_DIV 1
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#define CLKID_AO_ROUGH_32K 2
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#define CLKID_AO_OSCIN32K_CLK 3
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#define CLKID_AO_OSCIN_CLK 4
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#define CLKID_AO_SYS_CLK 5
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#define CLKID_AO_PSRAM_MUX 6
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#define CLKID_AO_PSRAM_DIV 7
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#define CLKID_AO_PSRAM 8
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#define CLKID_AO_PWM_A_MUX 9
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#define CLKID_AO_PWM_A_DIV 10
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#define CLKID_AO_PWM_A 11
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#define CLKID_AO_PWM_B_MUX 12
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#define CLKID_AO_PWM_B_DIV 13
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#define CLKID_AO_PWM_B 14
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#define CLKID_AO_SYS_RTC_REG 15
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#define CLKID_AO_SYS_CLKTREE 16
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#define CLKID_AO_SYS_RST_CTRL 17
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#define CLKID_AO_SYS_CLK_PAD 18
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#define CLKID_AO_SYS_RTC_DIG 19
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#define CLKID_AO_SYS_IRQ 20
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#define CLKID_AO_SYS_PWRCTRL 21
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#define CLKID_AO_SYS_PWM_A 22
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#define CLKID_AO_SYS_PWM_B 23
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#define CLKID_AO_SYS_I3C 24
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#define CLKID_AO_SYS_SPISG0 25
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#define CLKID_AO_SYS_IR_CTRL 26
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#define CLKID_AO_SYS_I2C_M_A 27
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#define CLKID_AO_SYS_I2C_M_B 28
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#define CLKID_AO_SYS_SED 29
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#define CLKID_AO_SYS_UART_A 30
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#define CLKID_AO_SYS_UART_B 31
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#define CLKID_AO_SYS_AO_SPI 32
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#define CLKID_AO_SYS_RTC_SECURE 33
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#define CLKID_AO_SYS_AO_ISP 34
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#define CLKID_AO_SYS_AOCPU 35
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#define CLKID_AO_SYS_SRAM 36
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#define CLKID_AO_SYS_PSRAM_APB 37
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#define CLKID_AO_SYS_PSRAM_AXI 38
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C5_CLKC_H */
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