/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C5_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_C5_CLKC_H

#define CLKID_GP0_PLL                             0
#define CLKID_HIFI_PLL                            1
#define CLKID_DSI_PLL                             2
#define CLKID_MCLK_PLL                            3
#define CLKID_MCLK1_PLL                           4
#define CLKID_FCLK_DIV50M_DIV                     5
#define CLKID_FCLK_DIV50M                         6
#define CLKID_FCLK_DIV2_DIV                       7
#define CLKID_FCLK_DIV2                           8
#define CLKID_FCLK_DIV2P5_DIV                     9
#define CLKID_FCLK_DIV2P5                         10
#define CLKID_FCLK_DIV3_DIV                       11
#define CLKID_FCLK_DIV3                           12
#define CLKID_FCLK_DIV4_DIV                       13
#define CLKID_FCLK_DIV4                           14
#define CLKID_FCLK_DIV5_DIV                       15
#define CLKID_FCLK_DIV5                           16
#define CLKID_FCLK_DIV7_DIV                       17
#define CLKID_FCLK_DIV7                           18
#define CLKID_MCLK_0_PRE_DIV                      19
#define CLKID_MCLK_0_PRE                          20
#define CLKID_MCLK_0_MUX                          21
#define CLKID_MCLK_0_DIV                          22
#define CLKID_MCLK_0                              23
#define CLKID_MCLK_1_PRE_DIV                      24
#define CLKID_MCLK_1_PRE                          25
#define CLKID_MCLK_1_MUX                          26
#define CLKID_MCLK_1_DIV                          27
#define CLKID_MCLK_1                              28
#define CLKID_MCLK1_0_PRE_DIV                     29
#define CLKID_MCLK1_0_PRE                         30
#define CLKID_MCLK1_0_MUX                         31
#define CLKID_MCLK1_0_DIV                         32
#define CLKID_MCLK1_0                             33
#define CLKID_MCLK1_1_PRE_DIV                     34
#define CLKID_MCLK1_1_PRE                         35
#define CLKID_MCLK1_1_MUX                         36
#define CLKID_MCLK1_1_DIV                         37
#define CLKID_MCLK1_1                             38
#define CLKID_RTC_DUAL_CLKIN                      39
#define CLKID_RTC_DUAL_DIV                        40
#define CLKID_RTC_DUAL_MUX                        41
#define CLKID_RTC_DUAL                            42
#define CLKID_RTC_CLK                             43
#define CLKID_SAR_ADC_MUX                         44
#define CLKID_SAR_ADC_DIV                         45
#define CLKID_SAR_ADC                             46
#define CLKID_PWM_C_MUX                           47
#define CLKID_PWM_C_DIV                           48
#define CLKID_PWM_C                               49
#define CLKID_PWM_D_MUX                           50
#define CLKID_PWM_D_DIV                           51
#define CLKID_PWM_D                               52
#define CLKID_PWM_E_MUX                           53
#define CLKID_PWM_E_DIV                           54
#define CLKID_PWM_E                               55
#define CLKID_PWM_F_MUX                           56
#define CLKID_PWM_F_DIV                           57
#define CLKID_PWM_F                               58
#define CLKID_PWM_G_MUX                           59
#define CLKID_PWM_G_DIV                           60
#define CLKID_PWM_G                               61
#define CLKID_PWM_H_MUX                           62
#define CLKID_PWM_H_DIV                           63
#define CLKID_PWM_H                               64
#define CLKID_PWM_I_MUX                           65
#define CLKID_PWM_I_DIV                           66
#define CLKID_PWM_I                               67
#define CLKID_PWM_J_MUX                           68
#define CLKID_PWM_J_DIV                           69
#define CLKID_PWM_J                               70
#define CLKID_PWM_K_MUX                           71
#define CLKID_PWM_K_DIV                           72
#define CLKID_PWM_K                               73
#define CLKID_PWM_L_MUX                           74
#define CLKID_PWM_L_DIV                           75
#define CLKID_PWM_L                               76
#define CLKID_PWM_M_MUX                           77
#define CLKID_PWM_M_DIV                           78
#define CLKID_PWM_M                               79
#define CLKID_PWM_N_MUX                           80
#define CLKID_PWM_N_DIV                           81
#define CLKID_PWM_N                               82
#define CLKID_PWM_O_MUX                           83
#define CLKID_PWM_O_DIV                           84
#define CLKID_PWM_O                               85
#define CLKID_PWM_P_MUX                           86
#define CLKID_PWM_P_DIV                           87
#define CLKID_PWM_P                               88
#define CLKID_PWM_Q_MUX                           89
#define CLKID_PWM_Q_DIV                           90
#define CLKID_PWM_Q                               91
#define CLKID_PWM_R_MUX                           92
#define CLKID_PWM_R_DIV                           93
#define CLKID_PWM_R                               94
#define CLKID_PWM_S_MUX                           95
#define CLKID_PWM_S_DIV                           96
#define CLKID_PWM_S                               97
#define CLKID_PWM_T_MUX                           98
#define CLKID_PWM_T_DIV                           99
#define CLKID_PWM_T                               100
#define CLKID_SPISG0_MUX                          101
#define CLKID_SPISG0_DIV                          102
#define CLKID_SPISG0                              103
#define CLKID_SPISG1_MUX                          104
#define CLKID_SPISG1_DIV                          105
#define CLKID_SPISG1                              106
#define CLKID_SPISG2_MUX                          107
#define CLKID_SPISG2_DIV                          108
#define CLKID_SPISG2                              109
#define CLKID_SD_EMMC_A_MUX                       110
#define CLKID_SD_EMMC_A_DIV                       111
#define CLKID_SD_EMMC_A                           112
#define CLKID_SD_EMMC_B_MUX                       113
#define CLKID_SD_EMMC_B_DIV                       114
#define CLKID_SD_EMMC_B                           115
#define CLKID_SD_EMMC_C_MUX                       116
#define CLKID_SD_EMMC_C_DIV                       117
#define CLKID_SD_EMMC_C                           118
#define CLKID_ETH_RMII_DIV                        119
#define CLKID_ETH_RMII                            120
#define CLKID_ETH_125M_DIV                        121
#define CLKID_ETH_125M                            122
#define CLKID_TS_DIV                              123
#define CLKID_TS                                  124
#define CLKID_CAN0_PE_MUX                         125
#define CLKID_CAN0_PE_DIV                         126
#define CLKID_CAN0_PE                             127
#define CLKID_CAN1_PE_MUX                         128
#define CLKID_CAN1_PE_DIV                         129
#define CLKID_CAN1_PE                             130
#define CLKID_CAN0_FILTER_MUX                     131
#define CLKID_CAN0_FILTER_DIV                     132
#define CLKID_CAN0_FILTER                         133
#define CLKID_CAN1_FILTER_MUX                     134
#define CLKID_CAN1_FILTER_DIV                     135
#define CLKID_CAN1_FILTER                         136
#define CLKID_I3C_MUX                             137
#define CLKID_I3C_DIV                             138
#define CLKID_I3C                                 139
#define CLKID_USB_48M_MUX                         140
#define CLKID_USB_48M_DIV                         141
#define CLKID_USB_48M                             142
#define CLKID_USB_250M_MUX                        143
#define CLKID_USB_250M_DIV                        144
#define CLKID_USB_250M                            145
#define CLKID_PCIE0_TL_MUX                        146
#define CLKID_PCIE0_TL_DIV                        147
#define CLKID_PCIE0_TL                            148
#define CLKID_AMFC_MUX                            149
#define CLKID_AMFC_DIV                            150
#define CLKID_AMFC                                151
#define CLKID_CMPR_MUX                            152
#define CLKID_CMPR_DIV                            153
#define CLKID_CMPR                                154
#define CLKID_VGE_MUX                             155
#define CLKID_VGE_DIV                             156
#define CLKID_VGE                                 157
#define CLKID_CVE_MUX                             158
#define CLKID_CVE_DIV                             159
#define CLKID_CVE                                 160
#define CLKID_DEWARPA_MUX                         161
#define CLKID_DEWARPA_DIV                         162
#define CLKID_DEWARPA                             163
#define CLKID_NNA_CORE_MUX                        164
#define CLKID_NNA_CORE_DIV                        165
#define CLKID_NNA_CORE                            166
#define CLKID_NNA2_CORE_MUX                       167
#define CLKID_NNA2_CORE_DIV                       168
#define CLKID_NNA2_CORE                           169
#define CLKID_VAPB_0_MUX                          170
#define CLKID_VAPB_0_DIV                          171
#define CLKID_VAPB_0                              172
#define CLKID_VAPB_1_MUX                          173
#define CLKID_VAPB_1_DIV                          174
#define CLKID_VAPB_1                              175
#define CLKID_VAPB                                176
#define CLKID_GE2D                                177
#define CLKID_ISP0_MUX                            178
#define CLKID_ISP0_DIV                            179
#define CLKID_ISP0                                180
#define CLKID_AI_ISP_MUX                          181
#define CLKID_AI_ISP_DIV                          182
#define CLKID_AI_ISP                              183
#define CLKID_GLB_MUX                             184
#define CLKID_GLB_DIV                             185
#define CLKID_GLB                                 186
#define CLKID_CSIPHY0_MUX                         187
#define CLKID_CSIPHY0_DIV                         188
#define CLKID_CSIPHY0                             189
#define CLKID_HEVCF_0_MUX                         190
#define CLKID_HEVCF_0_DIV                         191
#define CLKID_HEVCF_0                             192
#define CLKID_HEVCF_1_MUX                         193
#define CLKID_HEVCF_1_DIV                         194
#define CLKID_HEVCF_1                             195
#define CLKID_HEVCF                               196
#define CLKID_HCODEC_0_MUX                        197
#define CLKID_HCODEC_0_DIV                        198
#define CLKID_HCODEC_0                            199
#define CLKID_HCODEC_1_MUX                        200
#define CLKID_HCODEC_1_DIV                        201
#define CLKID_HCODEC_1                            202
#define CLKID_HCODEC                              203
#define CLKID_VOUT_MCLK_MUX                       204
#define CLKID_VOUT_MCLK_DIV                       205
#define CLKID_VOUT_MCLK                           206
#define CLKID_VOUT_VENC_MCLK_MUX                  207
#define CLKID_VOUT_VENC_MCLK_DIV                  208
#define CLKID_VOUT_VENC_MCLK                      209
#define CLKID_DSI_MEAS_MUX                        210
#define CLKID_DSI_MEAS_DIV                        211
#define CLKID_DSI_MEAS                            212
#define CLKID_CLK_24M_IN                          213
#define CLKID_CLK_12M_DIV                         214
#define CLKID_CLK_12_24M                          215
#define CLKID_GEN_MUX                             216
#define CLKID_GEN_DIV                             217
#define CLKID_GEN                                 218
#define CLKID_SYS_DOS                             219
#define CLKID_SYS_TAHOE                           220
#define CLKID_SYS_MIPI_DSI                        221
#define CLKID_SYS_ETH_PHY                         222
#define CLKID_SYS_AMFC                            223
#define CLKID_SYS_NNA                             224
#define CLKID_SYS_PCIE                            225
#define CLKID_SYS_PCIEMAC                         226
#define CLKID_SYS_GLB                             227
#define CLKID_SYS_MIPI_DSI_PHY                    228
#define CLKID_SYS_SD_EMMC_A                       229
#define CLKID_SYS_SD_EMMC_B                       230
#define CLKID_SYS_SD_EMMC_C                       231
#define CLKID_SYS_ACODEC                          232
#define CLKID_SYS_MIPI_ISP                        233
#define CLKID_SYS_MSR_CLK                         234
#define CLKID_SYS_AUDIO                           235
#define CLKID_SYS_ETH_MAC                         236
#define CLKID_SYS_UART_B                          237
#define CLKID_SYS_UART_C                          238
#define CLKID_SYS_UART_D                          239
#define CLKID_SYS_UART_E                          240
#define CLKID_SYS_UART_F                          241
#define CLKID_SYS_ETH_AXI                         242
#define CLKID_SYS_TS_ISP                          243
#define CLKID_SYS_TS_NNA                          244
#define CLKID_SYS_TS_PLL                          245
#define CLKID_SYS_PWM_M                           246
#define CLKID_SYS_PWM_N                           247
#define CLKID_SYS_CVE                             248
#define CLKID_SYS_GE2D                            249
#define CLKID_SYS_SPISG0                          250
#define CLKID_SYS_USB_U2H                         251
#define CLKID_SYS_USB_U3DRD                       252
#define CLKID_SYS_PERIPH                          253
#define CLKID_SYS_PWM_H                           254
#define CLKID_SYS_PWM_I                           255
#define CLKID_SYS_PWM_J                           256
#define CLKID_SYS_PWM_K                           257
#define CLKID_SYS_PWM_L                           258
#define CLKID_SYS_I2C_M_C                         259
#define CLKID_SYS_I2C_M_D                         260
#define CLKID_SYS_I2C_M_E                         261
#define CLKID_SYS_I2C_M_F                         262
#define CLKID_SYS_I2C_M_G                         263
#define CLKID_SYS_PIO                             264
#define CLKID_SYS_PWM_G                           265
#define CLKID_SYS_PWM_F                           266
#define CLKID_SYS_PWM_E                           267
#define CLKID_SYS_PWM_D                           268
#define CLKID_SYS_PWM_C                           269
#define CLKID_SYS_MMC_APB                         270
#define CLKID_SYS_CPU_APB                         271
#define CLKID_SYS_PP_DMA                          272
#define CLKID_SYS_PP_WRAPPER                      273
#define CLKID_SYS_CSI2_PHY0_APB                   274
#define CLKID_SYS_AUX_ADC                         275
#define CLKID_SYS_GIC                             276
#define CLKID_SYS_PWM_T                           277
#define CLKID_SYS_PWM_S                           278
#define CLKID_SYS_PWM_R                           279
#define CLKID_SYS_PWM_Q                           280
#define CLKID_SYS_PWM_P                           281
#define CLKID_SYS_PWM_O                           282
#define CLKID_SYS_CAN0                            283
#define CLKID_SYS_CAN1                            284
#define CLKID_SYS_I3C                             285
#define CLKID_AXI_SYS_NIC                         286
#define CLKID_AXI_RAMA                            287

/**
 * ao clk ids
 */
#define CLKID_OSC_32M_EN                          0
#define CLKID_AO_ROUGH_32K_DIV                    1
#define CLKID_AO_ROUGH_32K                        2
#define CLKID_AO_OSCIN32K_CLK                     3
#define CLKID_AO_OSCIN_CLK                        4
#define CLKID_AO_SYS_CLK                          5
#define CLKID_AO_PSRAM_MUX                        6
#define CLKID_AO_PSRAM_DIV                        7
#define CLKID_AO_PSRAM                            8
#define CLKID_AO_PWM_A_MUX                        9
#define CLKID_AO_PWM_A_DIV                        10
#define CLKID_AO_PWM_A                            11
#define CLKID_AO_PWM_B_MUX                        12
#define CLKID_AO_PWM_B_DIV                        13
#define CLKID_AO_PWM_B                            14
#define CLKID_AO_SYS_RTC_REG                      15
#define CLKID_AO_SYS_CLKTREE                      16
#define CLKID_AO_SYS_RST_CTRL                     17
#define CLKID_AO_SYS_CLK_PAD                      18
#define CLKID_AO_SYS_RTC_DIG                      19
#define CLKID_AO_SYS_IRQ                          20
#define CLKID_AO_SYS_PWRCTRL                      21
#define CLKID_AO_SYS_PWM_A                        22
#define CLKID_AO_SYS_PWM_B                        23
#define CLKID_AO_SYS_I3C                          24
#define CLKID_AO_SYS_SPISG0                       25
#define CLKID_AO_SYS_IR_CTRL                      26
#define CLKID_AO_SYS_I2C_M_A                      27
#define CLKID_AO_SYS_I2C_M_B                      28
#define CLKID_AO_SYS_SED                          29
#define CLKID_AO_SYS_UART_A                       30
#define CLKID_AO_SYS_UART_B                       31
#define CLKID_AO_SYS_AO_SPI                       32
#define CLKID_AO_SYS_RTC_SECURE                   33
#define CLKID_AO_SYS_AO_ISP                       34
#define CLKID_AO_SYS_AOCPU                        35
#define CLKID_AO_SYS_SRAM                         36
#define CLKID_AO_SYS_PSRAM_APB                    37
#define CLKID_AO_SYS_PSRAM_AXI                    38

#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C5_CLKC_H */