diff --git a/patch/kernel/archive/rockchip64-6.6/dt/rk3399pro-tinker-edge-r.dts b/patch/kernel/archive/rockchip64-6.6/dt/rk3399pro-tinker-edge-r.dts
index 4db750115..165b1f524 100644
--- a/patch/kernel/archive/rockchip64-6.6/dt/rk3399pro-tinker-edge-r.dts
+++ b/patch/kernel/archive/rockchip64-6.6/dt/rk3399pro-tinker-edge-r.dts
@@ -3,6 +3,7 @@
  * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
  * Copyright (c) 2019 Radxa Limited
  * Copyright (c) 2019 Amarula Solutions(India)
+ * Copyright (c) 2024 ARCW <wmx129674@126.com> rk3399pro-tinker_edge_r
  */
 
 /dts-v1/;
@@ -304,14 +305,26 @@
 		<000000000 0x0000 0x0000 0x0000>;
 };
 
+&hdmi_in_vopb {
+	status = "okay";
+};
+
 &hdmi_in_vopl {
 	status = "disabled";
 };
 
+&dp_in_vopl {
+	status = "disable";
+};
+
+&dp_in_vopb {
+	status = "okay";
+};
+
 &vopb {
 	status = "okay";
-	// assigned-clocks = <&cru DCLK_VOP0_DIV>;
-	// assigned-clock-parents = <&cru PLL_VPLL>;
+	assigned-clocks = <&cru DCLK_VOP0_DIV>;
+	assigned-clock-parents = <&cru PLL_VPLL>;
 };
 
 &vopb_mmu {
@@ -320,8 +333,8 @@
 
 &vopl {
 	status = "okay";
-	// assigned-clocks = <&cru DCLK_VOP1_DIV>;
-	// assigned-clock-parents = <&cru PLL_CPLL>;
+	assigned-clocks = <&cru DCLK_VOP1_DIV>;
+	assigned-clock-parents = <&cru PLL_CPLL>;
 };
 
 &vopl_mmu {
diff --git a/patch/kernel/archive/rockchip64-6.9/dt/rk3399pro-tinker-edge-r.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399pro-tinker-edge-r.dts
index 3785bb5d7..165b1f524 100644
--- a/patch/kernel/archive/rockchip64-6.9/dt/rk3399pro-tinker-edge-r.dts
+++ b/patch/kernel/archive/rockchip64-6.9/dt/rk3399pro-tinker-edge-r.dts
@@ -33,13 +33,13 @@
 
 		pwr-led {
 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "default-on";
+			linux,default-trigger = "heartbeat";
 			retain-state-suspended = <1>;
 		};
 
 		act-led {
 			gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger="mmc0";
+			linux,default-trigger="cpu";
 		};
 
 		rsv-led {
@@ -83,6 +83,14 @@
 		status = "okay";
 	};
 
+	vcc1v8_s0: vcc1v8-s0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
 	vdd_3v3_reg: fixedregulator_3v3 {
 		compatible = "regulator-fixed";
 		regulator-name = "3v3";
@@ -114,6 +122,23 @@
 		regulator-name = "vbus_typec";
 	};
 
+	vcca0v9_s3: vcca0v9-s3 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		regulator-name = "vcca0v9_s3";
+		vin-supply = <&vcc1v8_s0>;
+	};
+
+	/* As above, actually supplied by vcc3v3_sys */
+	vcca1v8_s3: vcca1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-name = "vcca1v8_s3";
+		vin-supply = <&vcc1v8_s0>;
+	};
+
 	backlight: backlight {
 		status = "disabled";
 		compatible = "pwm-backlight";
@@ -199,7 +224,7 @@
 		compatible = "linux,spdif-dit";
 		#sound-dai-cells = <0>;
 	};
-	
+
 	hdmi_dp_sound: hdmi-dp-sound {
 		status = "okay";
 		compatible = "rockchip,rk3399-hdmi-dp";
@@ -280,14 +305,26 @@
 		<000000000 0x0000 0x0000 0x0000>;
 };
 
+&hdmi_in_vopb {
+	status = "okay";
+};
+
 &hdmi_in_vopl {
 	status = "disabled";
 };
 
-&vopb {	
+&dp_in_vopl {
+	status = "disable";
+};
+
+&dp_in_vopb {
 	status = "okay";
-	// assigned-clocks = <&cru DCLK_VOP0_DIV>;
-	// assigned-clock-parents = <&cru PLL_VPLL>;
+};
+
+&vopb {
+	status = "okay";
+	assigned-clocks = <&cru DCLK_VOP0_DIV>;
+	assigned-clock-parents = <&cru PLL_VPLL>;
 };
 
 &vopb_mmu {
@@ -296,8 +333,8 @@
 
 &vopl {
 	status = "okay";
-	// assigned-clocks = <&cru DCLK_VOP1_DIV>;
-	// assigned-clock-parents = <&cru PLL_CPLL>;
+	assigned-clocks = <&cru DCLK_VOP1_DIV>;
+	assigned-clock-parents = <&cru PLL_CPLL>;
 };
 
 &vopl_mmu {
@@ -993,7 +1030,7 @@
 		};
 		vsel2_gpio: vsel2-gpio {
 			rockchip,pins =
-				<1 RK_PB6 0 &pcfg_pull_down>;
+				<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
 		};
 
 		soc_slppin_gpio: soc-slppin-gpio {
@@ -1077,4 +1114,3 @@
 	// 	};
 	// };
 };
-