diff --git a/config/sources/families/media.conf b/config/sources/families/media.conf index 882dfd84e..152e26f74 100644 --- a/config/sources/families/media.conf +++ b/config/sources/families/media.conf @@ -17,7 +17,7 @@ elif [[ $BOARD == station-m3 ]]; then BOOTBRANCH='branch:rk3588' BOOTPATCHDIR="u-boot-station-p2" else - BOOTBRANCH="tag:v2022.07" + BOOTBRANCH="tag:v2022.04" BOOTPATCHDIR="u-boot-media" fi diff --git a/patch/u-boot/u-boot-media/0010-add-board-helios64.patch b/patch/u-boot/u-boot-media/0010-add-board-helios64.patch new file mode 100644 index 000000000..f90aacb7e --- /dev/null +++ b/patch/u-boot/u-boot-media/0010-add-board-helios64.patch @@ -0,0 +1,2234 @@ +From 0ad85609017068d93c0311c34438db4e43588090 Mon Sep 17 00:00:00 2001 +From: Aditya Prayoga +Date: Tue, 15 Sep 2020 18:41:54 +0700 +Subject: [PATCH] Patching something + +Signed-off-by: Aditya Prayoga +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi | 136 ++ + arch/arm/dts/rk3399-kobol-helios64.dts | 1146 +++++++++++++++++ + arch/arm/mach-rockchip/rk3399/Kconfig | 17 + + board/kobol/helios64/Kconfig | 24 + + board/kobol/helios64/MAINTAINERS | 6 + + board/kobol/helios64/Makefile | 5 + + board/kobol/helios64/helios64.c | 304 +++++ + board/kobol/helios64/sys_otp.c | 248 ++++ + board/kobol/helios64/sys_otp.h | 10 + + configs/helios64-rk3399_defconfig | 145 +++ + include/configs/helios64.h | 47 + + 12 files changed, 2089 insertions(+) + create mode 100644 arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3399-kobol-helios64.dts + create mode 100644 board/kobol/helios64/Kconfig + create mode 100644 board/kobol/helios64/MAINTAINERS + create mode 100644 board/kobol/helios64/Makefile + create mode 100644 board/kobol/helios64/helios64.c + create mode 100644 board/kobol/helios64/sys_otp.c + create mode 100644 board/kobol/helios64/sys_otp.h + create mode 100644 configs/helios64-rk3399_defconfig + create mode 100644 include/configs/helios64.h + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 530d60bf..d9fd6cf1 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -143,6 +143,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + rk3399-firefly.dtb \ + rk3399-gru-bob.dtb \ + rk3399-gru-kevin.dtb \ ++ rk3399-kobol-helios64.dtb \ + rk3399-khadas-edge.dtb \ + rk3399-khadas-edge-captain.dtb \ + rk3399-khadas-edge-v.dtb \ +diff --git a/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi +new file mode 100644 +index 00000000..2988a209 +--- /dev/null ++++ b/arch/arm/dts/rk3399-kobol-helios64-u-boot.dtsi +@@ -0,0 +1,136 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2020 Aditya Prayoga (aditya@kobol.io) ++ */ ++ ++#include "rk3399-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++/ { ++ aliases { ++ spi0 = &spi1; ++ spi1 = &spi2; ++ spi2 = &spi5; ++ ethernet0 = &gmac; ++ ethernet1 = &usb_lan; ++ }; ++ ++ chosen { ++ bootargs = "earlycon=uart8250,mmio32,0xff1a0000 earlyprintk"; ++ stdout-path = "serial2:1500000n8"; ++ u-boot,spl-boot-order = "same-as-spl", &spiflash, &sdmmc, &sdhci; ++ }; ++ ++ config { ++ u-boot,spl-payload-offset = <0x80000>; /* @ 512KB */ ++ }; ++}; ++ ++&gpio1 { ++ usb-mux-hs { ++ gpio-hog; ++ gpios = ; ++ output-low; ++ line-name = "USB_MUX_HS"; ++ }; ++ ++ usb-mux-oe { ++ gpio-hog; ++ gpios = ; ++ output-high; ++ line-name = "USB_MUX_OE#"; ++ }; ++ ++ soc-flash-wp { ++ gpio-hog; ++ gpios = ; ++ output-low; ++ line-name = "SOC_WP#"; ++ }; ++}; ++ ++&gpio2 { ++ sata-flash-wp { ++ gpio-hog; ++ gpios = ; ++ output-high; ++ line-name = "SATA_WP#_LV"; ++ }; ++}; ++ ++&gpio4 { ++ auto-on-en-d { ++ gpio-hog; ++ gpios = ; ++ output-low; ++ line-name = "AUTO_ON_EN_D"; ++ }; ++ ++ auto-on-en-clk { ++ gpio-hog; ++ gpios = ; ++ output-low; ++ line-name = "AUTO_ON_EN_CLK"; ++ }; ++ ++ board-rev-id-0 { ++ gpio-hog; ++ gpios = ; ++ input; ++ }; ++ ++ board-rev-id-1 { ++ gpio-hog; ++ gpios = ; ++ input; ++ }; ++}; ++ ++&int_hub { ++ compatible = "usb-hub"; ++ usb,device-class = ; ++}; ++ ++&pcie_prst { ++ rockchip,pins = ++ <2 RK_PD4 RK_FUNC_GPIO &pcfg_output_low>; ++}; ++ ++&pcie_pwr_en { ++ rockchip,pins = ++ <1 RK_PD0 RK_FUNC_GPIO &pcfg_output_low>; ++}; ++ ++&pinctrl { ++ usb { ++ usb_mux_hs: usb-mux-hs { ++ rockchip,pins = ++ <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ usb_mux_oe: usb-mux-oe { ++ rockchip,pins = ++ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&spi1 { ++ spiflash: flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <25000000>; ++ status = "okay"; ++ m25p,fast-read; ++ u-boot,dm-pre-reloc; ++ }; ++}; ++ ++&vdd_center { ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++ regulator-init-microvolt = <950000>; ++}; ++ ++&vdd_log { ++ regulator-init-microvolt = <930000>; ++}; +diff --git a/arch/arm/dts/rk3399-kobol-helios64.dts b/arch/arm/dts/rk3399-kobol-helios64.dts +new file mode 100644 +index 00000000..9d067505 +--- /dev/null ++++ b/arch/arm/dts/rk3399-kobol-helios64.dts +@@ -0,0 +1,1149 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Aditya Prayoga (aditya@kobol.io) ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "Helios64"; ++ compatible = "kobol,helios64", "rockchip,rk3399"; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <100>; ++ ++ user2-button { ++ label = "User Button 2"; ++ linux,code = ; ++ press-threshold-microvolt = <100000>; ++ }; ++ }; ++ ++ beeper: beeper { ++ compatible = "gpio-beeper"; ++ gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc12v_dcin: vcc12v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc12v_dcin_bkup: vcc12v-dcin-bkup { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin_bkup"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ vcc12v_hdd: vcc12v-hdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_hdd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ vin-supply = <&vcc12v_dcin_bkup>; ++ }; ++ ++ /* switched by pmic_sleep */ ++ vcc1v8_sys_s0: vcc1v8-sys-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_sys_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc1v8_sys_s3>; ++ }; ++ ++ vcc0v9_s3: vcc0v9-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc0v9_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys_s3>; ++ }; ++ ++ avdd_0v9_s0: avdd-0v9-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd_0v9_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc1v8_sys_s3>; ++ }; ++ ++ avdd_1v8_s0: avdd-1v8-s0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "avdd_1v8_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys_s3>; ++ }; ++ ++ pcie_power: pcie-power { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pwr_en>; ++ regulator-name = "pcie_power"; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_perdev>; ++ }; ++ ++ vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v0_sd: vcc3v0-sd { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ regulator-name = "vcc3v0_sd"; ++ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_pwr_h>; ++ regulator-boot-on; ++ startup-delay-us = <20000>; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ vin-supply = <&vcc3v3_sys_s3>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_en>; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_perdev>; ++ }; ++ ++ vcc5v0_typec: vcc5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_vbus_en>; ++ regulator-name = "vcc5v0_typec"; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ vcc5v0_perdev: vcc5v0-perdev { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_perdev"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin_bkup>; ++ }; ++ ++ vcc5v0_hdd: vcc5v0-hdd { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_hdd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin_bkup>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin_bkup>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <830000>; ++ regulator-max-microvolt = <1400000>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ power_hdd_a: power-hdd-a { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdd_a_power>; ++ regulator-name = "power_hdd_a"; ++ }; ++ ++ power_hdd_b: power-hdd-b { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdd_b_power>; ++ regulator-name = "power_hdd_b"; ++ }; ++ ++ usblan_power: usblan-power { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb_lan_en>; ++ regulator-name = "usblan_power"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_usb>; ++ }; ++ ++ fan1: p7-fan { ++ compatible = "pwm-fan"; ++ pwms = <&pwm0 0 40000 0>; ++ cooling-min-state = <0>; ++ cooling-max-state = <3>; ++ #cooling-cells = <2>; ++ cooling-levels = <0 80 170 255>; ++ }; ++ ++ fan2: p6-fan { ++ compatible = "pwm-fan"; ++ pwms = <&pwm1 0 40000 0>; ++ cooling-min-state = <0>; ++ cooling-max-state = <3>; ++ #cooling-cells = <2>; ++ cooling-levels = <0 80 170 255>; ++ }; ++ ++ gpio-charger { ++ compatible = "gpio-charger"; ++ charger-type = "mains"; ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ charge-status-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ac_present_ap>, <&charger_status>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn>, <&user1btn>, <&wake_on_lan>; ++ ++ power { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "Power"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ ++ user1-button { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; ++ label = "User Button 1"; ++ linux,code = ; ++ }; ++ }; ++ ++ hdmi_dp_sound: hdmi-dp-sound { ++ status = "okay"; ++ compatible = "rockchip,rk3399-hdmi-dp"; ++ rockchip,cpu = <&i2s2>; ++ rockchip,codec = <&cdn_dp>; ++ }; ++ ++ io_leds: io-gpio-leds { ++ status = "okay"; ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&network_act>, <&usb3_act>, ++ <&sata_act>, <&sata_err_led>; ++ ++ network { ++ label = "helios64:blue:net"; ++ gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "netdev"; ++ default-state = "off"; ++ }; ++ ++ sata { ++ label = "helios64:blue:hdd-status"; ++ gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "disk-activity"; ++ default-state = "off"; ++ }; ++ ++ sata_err1 { ++ label = "helios64:red:ata1-err"; ++ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ sata_err2 { ++ label = "helios64:red:ata2-err"; ++ gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ sata_err3 { ++ label = "helios64:red:ata3-err"; ++ gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ sata_err4 { ++ label = "helios64:red:ata4-err"; ++ gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ sata_err5 { ++ label = "helios64:red:ata5-err"; ++ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; ++ default-state = "keep"; ++ }; ++ ++ usb3 { ++ label = "helios64:blue:usb3"; ++ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; ++ trigger-sources = <&int_hub_port1>, ++ <&int_hub_port2>, ++ <&int_hub_port3>; ++ linux,default-trigger = "usbport"; ++ default-state = "off"; ++ }; ++ }; ++ ++ pwmleds { ++ compatible = "pwm-leds"; ++ status = "okay"; ++ ++ power-led { ++ label = "helios64:blue:power-status"; ++ pwms = <&pwm3 0 2000000000 0>; ++ max-brightness = <255>; ++ }; ++ }; ++ ++ system_leds: system-gpio-leds { ++ status = "okay"; ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&system_led>; ++ ++ status-led { ++ label = "helios64::status"; ++ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "none"; ++ default-state = "on"; ++ mode = <0x23>; ++ }; ++ ++ fault-led { ++ label = "helios64:red:fault"; ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "panic"; ++ default-state = "keep"; ++ mode = <0x23>; ++ }; ++ }; ++}; ++ ++&cdn_dp { ++ status = "okay"; ++ extcon = <&fusb0>; ++ phys = <&tcphy0_dp>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_alert0 { ++ temperature = <80000>; ++}; ++ ++&cpu_alert1 { ++ temperature = <95000>; ++}; ++ ++&cpu_crit { ++ temperature = <100000>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_lan>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins &rgmii_phy_reset>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x28>; ++ rx_delay = <0x20>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ interrupt-parent = <&gpio0>; ++ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc3v3_sys_s3>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc5v0_sys>; ++ vcc12-supply = <&vcc3v3_sys_s3>; ++ vddio-supply = <&vcc3v0_s3>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr_s3: DCDC_REG3 { ++ regulator-name = "vcc_ddr_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_sys_s3: DCDC_REG4 { ++ regulator-name = "vcc1v8_sys_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ /* not used */ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ }; ++ ++ /* not used */ ++ vcc3v0_touch: LDO_REG2 { ++ regulator-name = "vcc3v0_touch"; ++ }; ++ ++ vcc1v8_s3: LDO_REG3 { ++ regulator-name = "vcc1v8_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sdio_s0: LDO_REG4 { ++ regulator-name = "vcc_sdio_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ /* not used */ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-name = "vcca3v0_codec"; ++ }; ++ ++ vcc1v5_s3: LDO_REG6 { ++ regulator-name = "vcc1v5_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ /* not used */ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-name = "vcca1v8_codec"; ++ }; ++ ++ vcc3v0_s3: LDO_REG8 { ++ regulator-name = "vcc3v0_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_sys_s0: SWITCH_REG1 { ++ regulator-name = "vcc3v3_sys_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel1_gpio>; ++ vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel2_gpio>; ++ vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <160>; ++ i2c-scl-falling-time-ns = <30>; ++ status = "okay"; ++ ++ gpio-expander@20 { ++ compatible = "nxp,pca9555"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pca0_pins>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ vcc-supply = <&vcc3v3_sys_s3>; ++ }; ++ ++ temp@4c { ++ compatible = "onnn,lm75"; ++ reg = <0x4c>; ++ vcc-supply = <&vcc3v3_sys_s0>; ++ }; ++}; ++ ++&i2c4 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <160>; ++ i2c-scl-falling-time-ns = <30>; ++ status = "okay"; ++ ++ fusb0: typec-portc@22 { ++ /* For use with typec-fusb302 */ ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ vbus-supply = <&vcc5v0_typec>; ++ status = "okay"; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ power-role = "dual"; ++ data-role = "dual"; ++ try-power-role = "sink"; ++ source-pdos = ; ++ sink-pdos = ; ++ op-sink-microwatt = <5000000>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usb_con_hs: endpoint { ++ remote-endpoint = <&u2phy0_typec_hs>; ++ }; ++ }; ++ port@1 { ++ reg = <1>; ++ usb_con_ss: endpoint { ++ remote-endpoint = <&tcphy0_typec_ss>; ++ }; ++ }; ++ port@2 { ++ reg = <2>; ++ usb_con_sbu: endpoint { ++ remote-endpoint = <&tcphy0_typec_dp>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++/* I2C on UEXT */ ++&i2c7 { ++ status = "okay"; ++}; ++ ++/* External I2C */ ++&i2c8 { ++ status = "okay"; ++}; ++ ++&i2s2 { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&io_domains { ++ status = "okay"; ++ bt656-supply = <&vcc1v8_sys_s0>; ++ audio-supply = <&vcc1v8_sys_s0>; ++ sdmmc-supply = <&vcc_sdio_s0>; ++ gpio1830-supply = <&vcc3v0_s3>; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; ++ num-lanes = <2>; ++ max-link-speed = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_prst &pcie_clkreqn_cpm>; ++ vpcie12v-supply = <&vcc12v_dcin>; ++ vpcie3v3-supply = <&pcie_power>; ++ vpcie1v8-supply = <&avdd_1v8_s0>; ++ vpcie0v9-supply = <&avdd_0v9_s0>; ++ status = "okay"; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ buttons { ++ pwrbtn: pwrbtn { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ user1btn: usr1btn { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ charger { ++ ac_present_ap: ac-present-ap { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ charger_status: charger-status { ++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fan { ++ fan1_sense: fan1-sense { ++ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ fan2_sense: fan2-sense { ++ rockchip,pins = <4 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb30x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = ++ <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ fusb0_vbus_en: fusb0-vbus-en { ++ rockchip,pins = ++ <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gmac { ++ rgmii_phy_reset: rgmii-phy-reset { ++ rockchip,pins = ++ <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; ++ }; ++ }; ++ ++ leds { ++ network_act: network-act { ++ rockchip,pins = ++ <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ usb3_act: usb3-act { ++ rockchip,pins = ++ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ sata_act: sata-act { ++ rockchip,pins = ++ <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ system_led: sys-led { ++ rockchip,pins = ++ <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>, ++ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ sata_err_led: sata-err-led { ++ rockchip,pins = ++ <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>, ++ <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>, ++ <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, ++ <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>, ++ <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ misc { ++ pca0_pins: pca0-pins { ++ rockchip,pins = ++ <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wake_on_lan: wake-on-lan { ++ rockchip,pins = ++ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_prst: pcie-prst { ++ rockchip,pins = ++ <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_pwr_en: pcie-pwr-en { ++ rockchip,pins = ++ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = ++ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = ++ <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ power { ++ hdd_a_power: hdd-a-power { ++ rockchip,pins = ++ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ hdd_b_power: hdd-b-power { ++ rockchip,pins = ++ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_usb_en: vcc5v0-usb-en { ++ rockchip,pins = ++ <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ sdmmc0_pwr_h: sdmmc0-pwr-h { ++ rockchip,pins = ++ ; ++ }; ++ ++ usb_lan_en: usb-lan-en { ++ rockchip,pins = ++ <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc3v0_s3>; ++ status = "okay"; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcc1v8_s3>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ assigned-clock-rates = <150000000>; ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ supports-emmc; ++ non-removable; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ sd-uhs-sdr104; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ vmmc-supply = <&vcc3v0_sd>; ++ vqmmc-supply = <&vcc_sdio_s0>; ++ status = "okay"; ++}; ++ ++&spi1 { ++ status = "okay"; ++}; ++ ++/* UEXT connector */ ++&spi2 { ++ status = "okay"; ++}; ++ ++&spi5 { ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ extcon = <&fusb0>; ++ status = "okay"; ++}; ++ ++&tcphy0_dp { ++ port { ++ tcphy0_typec_dp: endpoint { ++ remote-endpoint = <&usb_con_sbu>; ++ }; ++ }; ++}; ++ ++&tcphy0_usb3 { ++ port { ++ tcphy0_typec_ss: endpoint { ++ remote-endpoint = <&usb_con_ss>; ++ }; ++ }; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ extcon = <&fusb0>; ++ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ ++ port { ++ u2phy0_typec_hs: endpoint { ++ remote-endpoint = <&usb_con_hs>; ++ }; ++ }; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_usb>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ extcon = <&fusb0>; ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ dr_mode = "otg"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ int_hub: hub@1 { ++ compatible = "usb2109,0815"; ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ int_hub_port1: port@1 { ++ reg = <1>; ++ #trigger-source-cells = <0>; ++ }; ++ ++ int_hub_port2: port@2 { ++ reg = <2>; ++ #trigger-source-cells = <0>; ++ }; ++ ++ int_hub_port3: port@3 { ++ reg = <3>; ++ #trigger-source-cells = <0>; ++ }; ++ ++ usb_lan: device@4 { ++ compatible = "usbbda,8156"; ++ reg = <4>; ++ ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ interface@0 { /* interface 0 of configuration 1 */ ++ compatible = "usbbda,8156.config1.0"; ++ reg = <0 1>; ++ }; ++ }; ++ }; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; +diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig +index 254b9c5b..5f89bf6e 100644 +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -26,6 +26,22 @@ config TARGET_PINEBOOK_PRO_RK3399 + with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port, + 1920*1080 screen and all the usual laptop features. + ++config TARGET_HELIOS64 ++ bool "Kobol Innovations Helios64" ++ select BOARD_LATE_INIT ++ help ++ Helios64 is a Network Attached Storage board based on Rockchip RK3399. ++ ++ Key features of the Helios64 include: ++ * on-board PCIe to 5 Ports SATA Controller JMB585 ++ * on-board USB 3.0 hub (3x USB 3.0 host) ++ * USB Type-C (Support DisplayPort Alt Mode) ++ * on-board 1 Gigabit Ethernet ++ * on-board 2.5 Gigabit Ethernet (Realtek RTL8156) ++ * on-board eMMC ++ * on-board LPDDR4 ++ * SPI, I2C, UART, GPIO ++ + config TARGET_PUMA_RK3399 + bool "Theobroma Systems RK3399-Q7 (Puma)" + help +@@ -153,6 +169,7 @@ endif # BOOTCOUNT_LIMIT + + source "board/firefly/roc-pc-rk3399/Kconfig" + source "board/google/gru/Kconfig" ++source "board/kobol/helios64/Kconfig" + source "board/pine64/pinebook-pro-rk3399/Kconfig" + source "board/pine64/rockpro64_rk3399/Kconfig" + source "board/rockchip/evb_rk3399/Kconfig" +diff --git a/board/kobol/helios64/Kconfig b/board/kobol/helios64/Kconfig +new file mode 100644 +index 00000000..644cdbd8 +--- /dev/null ++++ b/board/kobol/helios64/Kconfig +@@ -0,0 +1,24 @@ ++if TARGET_HELIOS64 ++ ++config SYS_BOARD ++ default "helios64" ++ ++config SYS_VENDOR ++ default "kobol" ++ ++config SYS_CONFIG_NAME ++ default "helios64" ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ ++config ENV_SECT_SIZE ++ default 0x1000 if ENV_IS_IN_SPI_FLASH ++ ++config ENV_SIZE ++ default 0x8000 ++ ++config ENV_OFFSET ++ default 0x460000 if ENV_IS_IN_SPI_FLASH ++ ++endif +diff --git a/board/kobol/helios64/MAINTAINERS b/board/kobol/helios64/MAINTAINERS +new file mode 100644 +index 00000000..a9c88c79 +--- /dev/null ++++ b/board/kobol/helios64/MAINTAINERS +@@ -0,0 +1,6 @@ ++HELIOS64 BOARD ++M: Aditya Prayoga ++S: Maintained ++F: board/kobol/helios64/ ++F: include/configs/helios64.h ++F: configs/helios64_defconfig +diff --git a/board/kobol/helios64/Makefile b/board/kobol/helios64/Makefile +new file mode 100644 +index 00000000..ab34245a +--- /dev/null ++++ b/board/kobol/helios64/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (C) 2020 Aditya Prayoga ++ ++obj-y := helios64.o sys_otp.o +diff --git a/board/kobol/helios64/helios64.c b/board/kobol/helios64/helios64.c +new file mode 100644 +index 00000000..c7a0efa4 +--- /dev/null ++++ b/board/kobol/helios64/helios64.c +@@ -0,0 +1,321 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2020 Aditya Prayoga (aditya@kobol.io) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "sys_otp.h" ++ ++#ifndef CONFIG_TPL_BUILD ++int board_early_init_f(void) ++{ ++#ifdef CONFIG_SPL_BUILD ++#define GPIO0_BASE 0xff720000 ++#define GRF_BASE 0xff770000 ++ struct rk3399_grf_regs * const grf = (void *)GRF_BASE; ++ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; ++ ++ /* Turn ON status LED. At this stage, FDT & DM is not initialized yet */ ++ spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); ++#endif ++ return 0; ++} ++#endif ++ ++#ifndef CONFIG_SPL_BUILD ++int board_early_init_r(void) ++{ ++ read_otp_data(); ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_MISC_INIT_R ++#define GRF_IO_VSEL_BT565_SHIFT 0 ++#define GRF_IO_VSEL_AUDIO_SHIFT 1 ++#define GRF_IO_VSEL_SDMMC_SHIFT 2 ++#define GRF_IO_VSEL_GPIO1830_SHIFT 3 ++ ++#define PMUGRF_CON0_VSEL_SHIFT 8 ++#define PMUGRF_CON0_PMU1830_VOL_SHIFT 9 ++static void setup_iodomain(void) ++{ ++ struct rk3399_grf_regs *grf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ struct rk3399_pmugrf_regs *pmugrf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); ++ ++ /* BT565 is in 1.8v domain */ ++ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); ++ ++ /* AUDIO is in 1.8v domain */ ++ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_AUDIO_SHIFT); ++ ++ /* SDMMC is in 3.0v domain */ ++ rk_setreg(&grf->io_vsel, 0 << GRF_IO_VSEL_SDMMC_SHIFT); ++ ++ /* GPIO1830 is in 3.0v domain */ ++ rk_setreg(&grf->io_vsel, 0 << GRF_IO_VSEL_GPIO1830_SHIFT); ++ ++ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ ++ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); ++ rk_setreg(&pmugrf->soc_con0, 0 << PMUGRF_CON0_PMU1830_VOL_SHIFT); ++} ++ ++static void init_vdd_center(void) ++{ ++ struct udevice *regulator; ++ struct dm_regulator_uclass_plat *uc_pdata; ++ int ret; ++ ++ ret = regulator_get_by_platname("vdd_center", ®ulator); ++ if (ret) ++ return; ++ ++ uc_pdata = dev_get_uclass_plat(regulator); ++ ret = regulator_set_value(regulator, uc_pdata->init_uV); ++ if (ret) ++ debug("%s vdd_center init fail! ret %d\n", __func__, ret); ++} ++ ++/* ++ * Swap mmc0 and mmc1 in boot_targets if booted from SD-Card. ++ * ++ * If bootsource is uSD-card we can assume that we want to use the ++ * SD-Card instead of the eMMC as first boot_target for distroboot. ++ * We only want to swap the defaults and not any custom environment a ++ * user has set. We exit early if a changed boot_targets environment ++ * is detected. ++ */ ++static int setup_boottargets(void) ++{ ++ const char *boot_device = ++ ofnode_read_chosen_string("u-boot,spl-boot-device"); ++ char *env_default, *env; ++ ++ if (!boot_device) { ++ debug("%s: /chosen/u-boot,spl-boot-device not set\n", ++ __func__); ++ return -1; ++ } ++ debug("%s: booted from %s\n", __func__, boot_device); ++ ++ env_default = env_get_default("boot_targets"); ++ env = env_get("boot_targets"); ++ if (!env) { ++ debug("%s: boot_targets does not exist\n", __func__); ++ return -1; ++ } ++ debug("%s: boot_targets current: %s - default: %s\n", ++ __func__, env, env_default); ++ ++ if (strcmp(env_default, env) != 0) { ++ debug("%s: boot_targets not default, don't change it\n", ++ __func__); ++ return 0; ++ } ++ ++ /* ++ * Only run, if booting from mmc1 (i.e. /mmc@fe320000) and ++ * only consider cases where the default boot-order first ++ * tries to boot from mmc0 (eMMC) and then from mmc1 ++ * (i.e. external SD). ++ * ++ * In other words: the SD card will be moved to earlier in the ++ * order, if U-Boot was also loaded from the SD-card. ++ */ ++ if (!strcmp(boot_device, "/mmc@fe320000")) { ++ char *mmc0, *mmc1; ++ ++ debug("%s: booted from SD-Card\n", __func__); ++ mmc0 = strstr(env, "mmc0"); ++ mmc1 = strstr(env, "mmc1"); ++ ++ if (!mmc0 || !mmc1) { ++ debug("%s: only one mmc boot_target found\n", __func__); ++ return -1; ++ } ++ ++ /* ++ * If mmc0 comes first in the boot order, we need to change ++ * the strings to make mmc1 first. ++ */ ++ if (mmc0 < mmc1) { ++ mmc0[3] = '1'; ++ mmc1[3] = '0'; ++ debug("%s: set boot_targets to: %s\n", __func__, env); ++ env_set("boot_targets", env); ++ } ++ } ++ ++ return 0; ++} ++ ++static void setup_leds(void) ++{ ++ struct udevice *dev; ++ ++ led_get_by_label("helios64::status", &dev); ++ led_set_state(dev, LEDST_OFF); ++ mdelay(250); ++ led_set_state(dev, LEDST_ON); ++} ++ ++int misc_init_r(void) ++{ ++ const u32 cpuid_offset = 0x7; ++ const u32 cpuid_length = 0x10; ++ u8 cpuid[cpuid_length]; ++ int ret; ++ ++ setup_iodomain(); ++ init_vdd_center(); ++ set_board_info(); ++ ++ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_cpuid_set(cpuid, cpuid_length); ++ if (ret) ++ return ret; ++ ++ if (mac_read_from_otp()) ++ ret = rockchip_setup_macaddr(); ++ ++ setup_boottargets(); ++ setup_leds(); ++ ++ return ret; ++} ++#endif ++ ++#ifdef CONFIG_ROCKCHIP_ADVANCED_RECOVERY ++void rockchip_prepare_download_mode(void) ++{ ++ struct gpio_desc *enable, *mux; ++ ++ if (gpio_hog_lookup_name("USB_MUX_OE#", &enable)) { ++ debug("Fail to get USB_MUX_OE\n"); ++ return; ++ } ++ ++ if (gpio_hog_lookup_name("USB_MUX_HS", &mux)) { ++ debug("Fail to get USB_MUX_HS\n"); ++ return; ++ } ++ ++ dm_gpio_set_value(enable, 0); ++ mdelay(100); ++ dm_gpio_set_value(mux, 1); ++ mdelay(100); ++ dm_gpio_set_value(enable, 1); ++} ++#endif ++ ++#ifdef CONFIG_LAST_STAGE_INIT ++static void auto_power_enable(void) ++{ ++ struct gpio_desc *enable, *clock; ++ ++ if (gpio_hog_lookup_name("AUTO_ON_EN_D", &enable)) { ++ debug("Fail to get AUTO_ON_EN_D\n"); ++ return; ++ } ++ ++ if (gpio_hog_lookup_name("AUTO_ON_EN_CLK", &clock)) { ++ debug("Fail to get AUTO_ON_EN_CLK\n"); ++ return; ++ } ++ ++ dm_gpio_set_value(enable, 1); ++ dm_gpio_set_value(clock, 1); ++ mdelay(10); ++ dm_gpio_set_value(clock, 0); ++} ++ ++static void sata_power_enable(void) ++{ ++ struct udevice *rail_a, *rail_b; ++ int ret; ++ ++ ret = regulator_get_by_platname("power_hdd_a", &rail_a); ++ if (!ret) { ++ ret = regulator_set_enable(rail_a, true); ++ if (!ret) ++ mdelay(10000); ++ } ++ ++ ret = regulator_get_by_platname("power_hdd_b", &rail_b); ++ if (!ret) ++ ret = regulator_set_enable(rail_b, true); ++ ++} ++ ++int last_stage_init(void) ++{ ++ auto_power_enable(); ++ sata_power_enable(); ++ ++#ifdef CONFIG_PCI ++ scsi_scan(true); ++#endif ++ ++ return 0; ++} ++#endif ++ ++#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) ++int checkboard(void) ++{ ++ int major, minor; ++ ++ printf("Revision: "); ++ ++ if (!get_revision(&major, &minor)) ++ printf("%i.%i - %s\n", major, minor, get_variant()); ++ else ++ printf("UNKNOWN\n"); ++ ++ return 0; ++} ++#endif ++ ++#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) ++int ft_board_setup(void *blob, struct bd_info *bd) ++{ ++ char *env; ++ ++ env = env_get("board_rev"); ++ if (env) ++ fdt_setprop_string(blob, fdt_path_offset(blob, "/"), ++ "kobol,board-rev", env); ++ ++ env = env_get("cpuid#"); ++ if (env) ++ fdt_setprop_string(blob, fdt_path_offset(blob, "/"), ++ "kobol,cpu-id", env); ++ ++ return 0; ++} ++#endif +diff --git a/board/kobol/helios64/sys_otp.c b/board/kobol/helios64/sys_otp.c +new file mode 100644 +index 00000000..3a278346 +--- /dev/null ++++ b/board/kobol/helios64/sys_otp.c +@@ -0,0 +1,248 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "sys_otp.h" ++ ++#define OTP_DEVICE_BUS 0 ++#define OTP_DEVICE_CS 0 ++#define MAX_NUM_PORTS 2 ++ ++enum board_variant { ++ BOARD_VARIANT_INVALID = 0, ++ BOARD_VARIANT_ENG_SAMPLE, ++ BOARD_VARIANT_4G_PROD_NO_ECC, ++ BOARD_VARIANT_MAX ++}; ++ ++struct __attribute__ ((__packed__)) otp_data_t { ++ u8 magic[8]; ++ u8 part_num[16]; ++ u8 variant; ++ u8 revision; ++ u8 serial_num[6]; ++ u8 mfg_year[2]; ++ u8 mfg_month; ++ u8 mfg_day; ++ u8 mac_addr[MAX_NUM_PORTS][6]; ++ u8 reserved[204]; ++ u32 checksum; ++} otp; ++ ++static struct spi_slave *slave; ++static int has_been_read = 0; ++static int data_valid = 0; ++ ++static inline int is_data_valid(void) ++{ ++ return data_valid; ++} ++ ++static inline int is_valid_header(void) ++{ ++ if ((otp.magic[0] == 'H') || (otp.magic[1] == '6') || ++ (otp.magic[2] == '4') || (otp.magic[3] == 'N') || ++ (otp.magic[4] == 'P') || (otp.magic[5] == 'V') || ++ (otp.magic[6] == '1') || (otp.magic[7] == 0)) ++ ++ return 1; ++ ++ return 0; ++} ++ ++static int init_system_otp(int bus, int cs) ++{ ++ int ret; ++ char name[30], *str; ++ struct udevice *dev; ++ ++ snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); ++ str = strdup(name); ++ if (!str) ++ return -ENOMEM; ++ ret = spi_get_bus_and_cs(bus, cs, 25000000, CONFIG_DEFAULT_SPI_MODE, "spi_generic_drv", ++ str, &dev, &slave); ++ return ret; ++} ++ ++#ifdef DEBUG ++/** ++ * show_otp_data - display the contents of the OTP register ++ */ ++static void show_otp_data(void) ++{ ++ u32 i; ++ u32 crc; ++ ++ const char* var_str[BOARD_VARIANT_MAX] = { ++ "Invalid variant", ++ "Engineering Sample", ++ "Production - 4GB non ECC" ++ }; ++ ++ printf("\n"); ++ printf("Register dump: (%lu bytes)\n", sizeof(otp)); ++ for (i = 0; i < sizeof(otp); i++) { ++ if ((i % 16) == 0) ++ printf("%02X: ", i); ++ printf("%02X ", ((u8 *)&otp)[i]); ++ if (((i % 16) == 15) || (i == sizeof(otp) - 1)) ++ printf("\n"); ++ } ++ ++ if (!is_valid_header()) ++ return; ++ ++ printf("Part Number: %s\n", otp.part_num); ++ printf("Variant: %s\n", var_str[otp.variant]); ++ printf("Revision: %x.%x\n", (otp.revision & 0xf0) >> 4, otp.revision & 0x0f); ++ printf("Serial Number: %012llx\n", *((uint64_t*) otp.serial_num) & ++ 0xFFFFFFFFFFFF); ++ printf("Manufacturing Date: %02X-%02X-%04X (DD-MM-YYYY)\n", otp.mfg_day, ++ otp.mfg_month, *(u16*) otp.mfg_year); ++ ++ printf("1GbE MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", ++ otp.mac_addr[0][0], otp.mac_addr[0][1], otp.mac_addr[0][2], ++ otp.mac_addr[0][3], otp.mac_addr[0][4], otp.mac_addr[0][5]); ++ ++ printf("2.5GbE MAC Address: %02X:%02X:%02X:%02X:%02X:%02X\n", ++ otp.mac_addr[1][0], otp.mac_addr[1][1], otp.mac_addr[1][2], ++ otp.mac_addr[1][3], otp.mac_addr[1][4], otp.mac_addr[1][5]); ++ ++ crc = crc32(0, (void *)&otp, sizeof(otp) - 4); ++ ++ if (crc == le32_to_cpu(otp.checksum)) ++ printf("CRC: %08x\n\n", le32_to_cpu(otp.checksum)); ++ else ++ printf("CRC: %08x (should be %08x)\n\n", ++ le32_to_cpu(otp.checksum), crc); ++ ++} ++#endif ++ ++int read_otp_data(void) ++{ ++ int ret; ++ u8 dout[5]; ++ ++ if (has_been_read) { ++ if (is_data_valid()) ++ return 0; ++ else ++ goto data_invalid; ++ } ++ ++ ret = init_system_otp(OTP_DEVICE_BUS, OTP_DEVICE_CS); ++ if (ret) ++ return ret; ++ ++ ret = spi_claim_bus(slave); ++ if (ret) { ++ debug("SPI: Failed to claim SPI bus: %d\n", ret); ++ return ret; ++ } ++ ++ dout[0] = 0x48; ++ dout[1] = 0x00; ++ dout[2] = 0x10; /* Security Register #1 */ ++ dout[3] = 0x00; ++ dout[4] = 0x00; /* Dummy Byte */ ++ ++ ret = spi_write_then_read(slave, dout, sizeof(dout), NULL, (u8 *)&otp, ++ sizeof(otp)); ++ ++ spi_release_bus(slave); ++#ifdef DEBUG ++ show_otp_data(); ++#endif ++ ++ has_been_read = (ret == 0) ? 1 : 0; ++ if (!is_valid_header()) ++ goto data_invalid; ++ ++ if (crc32(0, (void *)&otp, sizeof(otp) - 4) == ++ le32_to_cpu(otp.checksum)) ++ data_valid = 1; ++ ++ if (!is_data_valid()) ++ goto data_invalid; ++ ++ return 0; ++ ++data_invalid: ++ printf("Invalid board ID data!\n"); ++ return -1; ++} ++ ++int get_revision(int *major, int *minor) ++{ ++ if (!is_data_valid()) ++ return -1; ++ ++ *major = (otp.revision & 0xf0) >> 4; ++ *minor = otp.revision & 0x0f; ++ ++ return 0; ++} ++ ++const char *get_variant(void) ++{ ++ const char* var_str[BOARD_VARIANT_MAX] = { ++ "Unknown", ++ "Engineering Sample", ++ "4GB non ECC" ++ }; ++ ++ if ((otp.variant < BOARD_VARIANT_ENG_SAMPLE) || ++ (otp.variant >= BOARD_VARIANT_MAX)) ++ return var_str[0]; ++ ++ return var_str[otp.variant]; ++} ++ ++void set_board_info(void) ++{ ++ char env_str[13]; ++ ++ if (!is_data_valid()) ++ return; ++ ++ snprintf(env_str, sizeof(env_str), "%i.%i", (otp.revision & 0xf0) >> 4, otp.revision & 0x0f); ++ env_set("board_rev", env_str); ++ ++ sprintf(env_str, "%012llx", *((uint64_t*) otp.serial_num) & ++ 0xFFFFFFFFFFFF); ++ ++ env_set("serial#", env_str); ++} ++ ++int mac_read_from_otp(void) ++{ ++ unsigned int i; ++ int ret; ++ ++ if (!is_data_valid()) ++ return -1; ++ ++ for (i = 0; i < MAX_NUM_PORTS; i++) { ++ char enetvar[9]; ++ ++ sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i); ++ ++ if (!is_valid_ethaddr(otp.mac_addr[i])) { ++ debug("Not valid %s!\n", enetvar); ++ continue; ++ } ++ ++ /* Only initialize environment variables that are blank ++ * (i.e. have not yet been set) ++ */ ++ if (!env_get(enetvar)) ++ eth_env_set_enetaddr(enetvar, otp.mac_addr[i]); ++ } ++ ++ return ret; ++} +diff --git a/board/kobol/helios64/sys_otp.h b/board/kobol/helios64/sys_otp.h +new file mode 100644 +index 00000000..61f6f3b3 +--- /dev/null ++++ b/board/kobol/helios64/sys_otp.h +@@ -0,0 +1,10 @@ ++#ifndef __HELIOS64_SYS_OTP_H ++#define __HELIOS64_SYS_OTP_H ++ ++int read_otp_data(void); ++void set_board_info(void); ++int get_revision(int *major, int *minor); ++const char *get_variant(void); ++int mac_read_from_otp(void); ++ ++#endif +diff --git a/configs/helios64-rk3399_defconfig b/configs/helios64-rk3399_defconfig +new file mode 100644 +index 00000000..62210055 +--- /dev/null ++++ b/configs/helios64-rk3399_defconfig +@@ -0,0 +1,147 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-kobol-helios64" ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_ROCKCHIP_ADVANCED_RECOVERY=y ++CONFIG_ROCKCHIP_ADVANCED_RECOVERY_LED="helios64::status" ++# CONFIG_ROCKCHIP_ADVANCED_RECOVERY_ROCKUSB is not set ++CONFIG_TARGET_HELIOS64=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_SYS_LOAD_ADDR=0x800800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_OF_BOARD_SETUP=y ++CONFIG_USE_PREBOOT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-kobol-helios64.dtb" ++CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y ++CONFIG_BOARD_TYPES=y ++# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_BOARD_EARLY_INIT_F=y ++CONFIG_BOARD_EARLY_INIT_R=y ++CONFIG_LAST_STAGE_INIT=y ++CONFIG_MISC_INIT_R=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_I2C=y ++CONFIG_SPL_POWER=y ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_TPL=y ++CONFIG_CMD_CONFIG=y ++CONFIG_CMD_BOOTZ=y ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++CONFIG_CMD_BOOTEFI_HELLO=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CRC32_VERIFY=y ++CONFIG_CMD_MD5SUM=y ++CONFIG_MD5SUM_VERIFY=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MX_CYCLIC=y ++CONFIG_CMD_SHA1SUM=y ++CONFIG_SHA1SUM_VERIFY=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_ADC=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_CMD_READ=y ++CONFIG_CMD_SPI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_ROCKUSB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++CONFIG_CMD_EFIDEBUG=y ++CONFIG_CMD_EXCEPTION=y ++CONFIG_CMD_TIME=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_IP_DEFRAG=y ++# CONFIG_DM_DEVICE_REMOVE is not set ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SPL_FIRMWARE=y ++CONFIG_GPIO_HOG=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_DM_PCA953X=y ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_I2C_DEFAULT_BUS_NUMBER=0x8 ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_ROCKCHIP_EFUSE=y ++CONFIG_ROCKCHIP_OTP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_DM_MDIO=y ++CONFIG_PHY_GIGE=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_RGMII=y ++CONFIG_MII=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PCI=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y ++CONFIG_DM_PMIC_FAN53555=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_SPL_DM_REGULATOR_GPIO=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_DM_RESET=y ++CONFIG_SCSI=y ++CONFIG_DM_SCSI=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SYSCON=y ++CONFIG_DM_THERMAL=y ++CONFIG_USB=y ++# CONFIG_SPL_DM_USB is not set ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_FUNCTION_ROCKUSB=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y ++CONFIG_HEXDUMP=y +diff --git a/include/configs/helios64.h b/include/configs/helios64.h +new file mode 100644 +index 00000000..6fca9a6b +--- /dev/null ++++ b/include/configs/helios64.h +@@ -0,0 +1,47 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2020 Aditya Prayoga ++ */ ++ ++#ifndef __HELIOS64_H ++#define __HELIOS64_H ++ ++#include ++ ++#define SDRAM_BANK_SIZE (2UL << 30) ++ ++#if defined(CONFIG_ENV_IS_IN_MMC) ++ #define CONFIG_SYS_MMC_ENV_DEV 0 ++#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) ++ #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS ++ #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS ++ #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE ++ #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED ++#endif ++ ++ ++#ifndef CONFIG_SPL_BUILD ++#if CONFIG_IS_ENABLED(SCSI) ++ ++ #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 ++ #define CONFIG_SYS_SCSI_MAX_LUN 1 ++ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ ++ CONFIG_SYS_SCSI_MAX_LUN) ++ ++ #define BOOT_TARGET_SCSI(func) \ ++ func(SCSI, scsi, 0) ++#else ++ #define BOOT_TARGET_SCSI(func) ++#endif ++ ++#undef BOOT_TARGET_DEVICES ++#define BOOT_TARGET_DEVICES(func) \ ++ BOOT_TARGET_MMC(func) \ ++ BOOT_TARGET_USB(func) \ ++ BOOT_TARGET_SCSI(func) \ ++ BOOT_TARGET_PXE(func) \ ++ BOOT_TARGET_DHCP(func) ++ ++#endif ++ ++#endif +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/u-boot/u-boot-media/0020-add-board-nanopi-m4v2.patch b/patch/u-boot/u-boot-media/0020-add-board-nanopi-m4v2.patch new file mode 100644 index 000000000..0269ae947 --- /dev/null +++ b/patch/u-boot/u-boot-media/0020-add-board-nanopi-m4v2.patch @@ -0,0 +1,214 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 9900b442..afa9ec81 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -128,6 +128,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + rk3399-nanopi-m4.dtb \ + rk3399-nanopi-m4-2gb.dtb \ + rk3399-nanopi-m4b.dtb \ ++ rk3399-nanopi-m4v2.dtb \ + rk3399-nanopi-neo4.dtb \ + rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ +diff --git a/arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi +new file mode 100644 +index 00000000..4b775f6d +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-m4v2-u-boot.dtsi +@@ -0,0 +1,31 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019 Jagan Teki ++ */ ++ ++#include "rk3399-nanopi4-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = &sdmmc, &sdhci; ++ }; ++}; ++ ++&sdio0 { ++ status = "disabled"; ++}; ++ ++&vdd_center { ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++}; ++ ++&vdd_log { ++ regulator-init-microvolt = <950000>; ++}; ++ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm2_pin>; ++}; +diff --git a/arch/arm/dts/rk3399-nanopi-m4v2.dts b/arch/arm/dts/rk3399-nanopi-m4v2.dts +new file mode 100644 +index 00000000..eac77f2a +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-m4v2.dts +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * FriendlyElec NanoPi M4 board device tree source ++ * ++ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2018 Collabora Ltd. ++ * Copyright (c) 2019 Arm Ltd. ++ */ ++ ++/dts-v1/; ++#include "rk3399-nanopi4.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi M4V2"; ++ compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc5v0_core: vcc5v0-core { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_core"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vdd_5v>; ++ }; ++ ++ vcc5v0_usb1: vcc5v0-usb1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb1"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_usb2: vcc5v0-usb2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb2"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-init-microvolt = <900000>; ++ }; ++}; ++ ++&vcc3v3_sys { ++ vin-supply = <&vcc5v0_core>; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vcc5v0_usb1>; ++}; ++ ++&u2phy1_host { ++ phy-supply = <&vcc5v0_usb2>; ++}; ++ ++&vbus_typec { ++ regulator-always-on; ++ vin-supply = <&vdd_5v>; ++}; +diff --git a/configs/nanopi-m4v2-rk3399_defconfig b/configs/nanopi-m4v2-rk3399_defconfig +new file mode 100644 +index 00000000..dd26f73d +--- /dev/null ++++ b/configs/nanopi-m4v2-rk3399_defconfig +@@ -0,0 +1,76 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_EVB_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4v2" ++CONFIG_DEBUG_UART=y ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4v2.dtb" ++CONFIG_MISC_INIT_R=y ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_NVME=y ++CONFIG_PCI=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/patch/u-boot/u-boot-media/0030-add-board-orangepi-4.patch b/patch/u-boot/u-boot-media/0030-add-board-orangepi-4.patch new file mode 100644 index 000000000..55d2b9e58 --- /dev/null +++ b/patch/u-boot/u-boot-media/0030-add-board-orangepi-4.patch @@ -0,0 +1,328 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 0ba45ff7..530d60bf 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -132,6 +132,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + rk3399-nanopi-m4v2.dtb \ + rk3399-nanopi-neo4.dtb \ + rk3399-orangepi.dtb \ ++ rk3399-orangepi-4.dtb \ + rk3399-pinebook-pro.dtb \ + rk3399-puma-haikou.dtb \ + rk3399-roc-pc.dtb \ +diff --git a/arch/arm/dts/rk3399-orangepi-4-u-boot.dtsi b/arch/arm/dts/rk3399-orangepi-4-u-boot.dtsi +new file mode 100644 +index 00000000..5bd86966 +--- /dev/null ++++ b/arch/arm/dts/rk3399-orangepi-4-u-boot.dtsi +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019 Jagan Teki ++ */ ++ ++#include "rk3399-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; ++ }; ++}; +diff --git a/arch/arm/dts/rk3399-orangepi-4.dts b/arch/arm/dts/rk3399-orangepi-4.dts +new file mode 100644 +index 00000000..65e9c44b +--- /dev/null ++++ b/arch/arm/dts/rk3399-orangepi-4.dts +@@ -0,0 +1,206 @@ ++/* ++ * (C) Copyright 2016 Rockchip Electronics Co., Ltd ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "OrangePi 4 AI board"; ++ compatible = "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ vdd_center: vdd-center { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm3 0 25000 1>; ++ regulator-name = "vdd_center"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-init-microvolt = <950000>; ++ regulator-always-on; ++ regulator-boot-on; ++ status = "okay"; ++ }; ++ ++ vccsys: vccsys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vccsys"; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vcc_phy: vcc-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_phy"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-en { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc5v0_typec0: vcc5v0-typec0-en { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_typec0"; ++ gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ vcc5v0_typec1: vcc5v0-typec1-en { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_typec1"; ++ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&pwm3 { ++ status = "okay"; ++}; ++ ++&saradc { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ vbus-supply = <&vcc5v0_typec0>; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_1 { ++ vbus-supply = <&vcc5v0_typec1>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ i2c-scl-falling-time-ns = <50>; ++ i2c-scl-rising-time-ns = <100>; ++ u-boot,dm-pre-reloc; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ clock-output-names = "xin32k", "wifibt_32kin"; ++ interrupt-parent = <&gpio0>; ++ interrupts = <4 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ reg = <0x1b>; ++ rockchip,system-power-controller; ++ #clock-cells = <1>; ++ u-boot,dm-pre-reloc; ++ status = "okay"; ++ ++ vcc12-supply = <&vcc3v3_sys>; ++ ++ regulators { ++ vcc33_lcd: SWITCH_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc33_lcd"; ++ }; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <1 21 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ pmic_dvs2: pmic-dvs2 { ++ rockchip,pins = ++ <1 18 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++}; ++ ++&gmac { ++ phy-supply = <&vcc_phy>; ++ phy-mode = "rgmii"; ++ clock_in_out = "input"; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ tx_delay = <0x28>; ++ rx_delay = <0x11>; ++ status = "okay"; ++}; +diff --git a/configs/orangepi-4-rk3399_defconfig b/configs/orangepi-4-rk3399_defconfig +new file mode 100644 +index 00000000..18ec369f +--- /dev/null ++++ b/configs/orangepi-4-rk3399_defconfig +@@ -0,0 +1,79 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi-4" ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_EVB_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi-4.dtb" ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_REGULATOR=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_ROCKCHIP_EFUSE=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_NVME_PCI=y ++CONFIG_PCI=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_USB_GADGET=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y diff --git a/patch/u-boot/u-boot-media/0040-add-board-orangepi-r1plus.patch b/patch/u-boot/u-boot-media/0040-add-board-orangepi-r1plus.patch new file mode 100644 index 000000000..efa124129 --- /dev/null +++ b/patch/u-boot/u-boot-media/0040-add-board-orangepi-r1plus.patch @@ -0,0 +1,184 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 06ccc03e..a2657ebe 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ + dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb \ + rk3328-nanopi-r2s.dtb \ ++ rk3328-orangepi-r1-plus.dtb \ + rk3328-roc-cc.dtb \ + rk3328-rock64.dtb \ + rk3328-rock-pi-e.dtb +diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +new file mode 100644 +index 00000000..cf3452ea +--- /dev/null ++++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd ++ */ ++ ++#include "rk3328-u-boot.dtsi" ++#include "rk3328-sdram-ddr4-666.dtsi" ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; ++ }; ++}; ++ ++&usb_host0_xhci { ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus.dts b/arch/arm/dts/rk3328-orangepi-r1-plus.dts +new file mode 100644 +index 00000000..23023ad0 +--- /dev/null ++++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts +@@ -0,0 +1,45 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Shenzhen Xunlong Software CO.,Limited ++ * Copyright (c) 2021 AmadeusGhost ++ * ++ * Based on Nanopi R2S ++ */ ++ ++#include "rk3328-nanopi-r2s.dts" ++ ++/ { ++ model = "Xunlong Orange Pi R1 Plus"; ++ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; ++}; ++ ++&sys_led_pin { ++ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++}; ++ ++&sys_led { ++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; ++}; ++ ++/* No support in mainline u-boot for mach node ++&mach { ++ compatible = "orangepi,board"; ++ hwrev = <2>; ++ machine = "ORANGEPI-R1PLUS"; ++ model = "OrangePi R1PLUS"; ++}; ++*/ ++ ++&spi0 { ++ status = "okay"; ++ ++ spiflash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ }; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; +diff --git a/configs/orangepi_r1_plus_rk3328_defconfig b/configs/orangepi_r1_plus_rk3328_defconfig +new file mode 100644 +index 00000000..ddbe9715 +@@ -0,0 +1,95 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_ROCKCHIP_RK3328=y ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_TPL_LIBCOMMON_SUPPORT=y ++CONFIG_TPL_LIBGENERIC_SUPPORT=y ++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEBUG_UART_BASE=0xFF130000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" ++CONFIG_DEBUG_UART=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 ++# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" ++CONFIG_MISC_INIT_R=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_ATF=y ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_TPL_OF_CONTROL=y ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_TPL_OF_PLATDATA=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_TPL_DM=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_TPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_TPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_FASTBOOT_BUF_ADDR=0x800800 ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_TPL_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++# CONFIG_TPL_SYSRESET is not set ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_GADGET is not set ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_TPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y ++CONFIG_SMBIOS_MANUFACTURER="pine64" diff --git a/patch/u-boot/u-boot-media/0050-add-board-rock-pi-s.patch b/patch/u-boot/u-boot-media/0050-add-board-rock-pi-s.patch new file mode 100644 index 000000000..f48e9e1e6 --- /dev/null +++ b/patch/u-boot/u-boot-media/0050-add-board-rock-pi-s.patch @@ -0,0 +1,356 @@ +--- a/arch/arm/dts/Makefile 2020-12-25 15:14:09.980329455 +0200 ++++ b/arch/arm/dts/Makefile 2020-12-25 15:14:47.952271432 +0200 +@@ -106,7 +106,8 @@ + + dtb-$(CONFIG_ROCKCHIP_RK3308) += \ + rk3308-evb.dtb \ +- rk3308-roc-cc.dtb ++ rk3308-roc-cc.dtb \ ++ rk3308-rock-pi-s.dtb + + dtb-$(CONFIG_ROCKCHIP_RK3328) += \ + rk3328-evb.dtb \ +--- /dev/null 2020-12-23 11:47:50.044000030 +0200 ++++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi 2020-12-25 15:00:18.561552517 +0200 +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd ++ */ ++#include "rk3308-u-boot.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc; ++ }; ++}; ++ ++&uart2 { ++ u-boot,dm-pre-reloc; ++ clock-frequency = <24000000>; ++ status = "okay"; ++}; +--- /dev/null 2020-12-23 11:47:50.044000030 +0200 ++++ b/arch/arm/dts/rk3308-rock-pi-s.dts 2020-12-25 15:53:15.775897762 +0200 +@@ -0,0 +1,215 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 Akash Gajjar ++ * Copyright (c) 2019 Jagan Teki ++ */ ++ ++/dts-v1/; ++#include "rk3308.dtsi" ++ ++/ { ++ model = "Radxa ROCK Pi S"; ++ compatible = "radxa,rockpis", "rockchip,rk3308"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>; ++ ++ green-led { ++ label = "rockpis:green:power"; ++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "default-on"; ++ default-state = "on"; ++ }; ++ ++ blue-led { ++ label = "rockpis:blue:user"; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vdd_core: vdd-core { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm0 0 5000 1>; ++ regulator-name = "vdd_core"; ++ regulator-min-microvolt = <827000>; ++ regulator-max-microvolt = <1340000>; ++ regulator-init-microvolt = <1015000>; ++ regulator-settling-time-up-us = <250>; ++ regulator-always-on; ++ regulator-boot-on; ++ pwm-supply = <&vcc5v0_sys>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1050000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_ddr: vcc-ddr { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_1v8: vcc-1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_io>; ++ }; ++ ++ vcc_io: vcc-io { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_io"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_phy: vcc-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_phy"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc5v0_otg: vcc5v0-otg { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_otg"; ++ regulator-always-on; ++ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&otg_vbus_drv>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_core>; ++}; ++ ++&emmc { ++ bus-width = <4>; // Confirm if right value - <8> ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ /* supports-sd; */ ++ /* disable-wp; */ ++ non-removable; ++ /* num-slots = <1>; */ ++ /* please provide actual vmmc and vqmmc supplies ++ vin is not a valid supply for emmcs */ ++ vin-supply = <&vcc_io>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&mac { ++ phy-supply = <&vcc_phy>; ++ clock_in_out = "output"; ++ assigned-clocks = <&cru SCLK_MAC>; ++ assigned-clock-parents = <&cru SCLK_MAC_SRC>; ++ snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 50000 50000>; ++ status = "okay"; ++}; ++ ++&spi2 { ++ status = "okay"; ++ max-freq = <10000000>; ++}; ++ ++&pinctrl { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_32k>; ++ ++ leds { ++ green_led_gio: green-led-gpio { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ heartbeat_led_gpio: heartbeat-led-gpio { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ otg_vbus_drv: otg-vbus-drv { ++ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++ pinctrl-0 = <&pwm0_pin_pull_down>; ++}; ++ ++&saradc { ++ vref-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_xfer &uart4_rts &uart4_cts>; ++ status = "okay"; ++}; +--- /dev/null 2020-12-23 11:47:50.044000030 +0200 ++++ b/configs/rock-pi-s-rk3308_defconfig 2020-12-25 17:35:28.269897086 +0200 +@@ -0,0 +1,103 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00600000 ++CONFIG_SPL_GPIO_SUPPORT=y ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_SYS_MALLOC_F_LEN=0x2000 ++CONFIG_ROCKCHIP_RK3308=y ++CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 ++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_TARGET_EVB_RK3308=y ++CONFIG_SPL_STACK_R_ADDR=0xc00000 ++CONFIG_PRE_CON_BUF_ADDR=0x0f200000 ++CONFIG_DEBUG_UART_BASE=0xFF0C0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_LIBDISK_SUPPORT=y ++CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s" ++CONFIG_DEBUG_UART=y ++CONFIG_BAUDRATE=1500000 ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_ANDROID_BOOT_IMAGE=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y ++# CONFIG_SYS_DEVICE_NULLDEV is not set ++CONFIG_DEFAULT_FDT_FILE="rk3308-rock-pi-s.dtb" ++CONFIG_MISC_INIT_R=y ++CONFIG_VERSION_VARIABLE=y ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_BOARD_TYPES=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y ++CONFIG_CMD_CONFIG=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_IMI is not set ++# CONFIG_CMD_XIMG is not set ++CONFIG_CMD_GPT=y ++# CONFIG_CMD_LOADB is not set ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_ITEST is not set ++# CONFIG_CMD_SETEXPR is not set ++# CONFIG_ISO_PARTITION is not set ++CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++# CONFIG_USB_FUNCTION_FASTBOOT is not set ++CONFIG_SPL_FIRMWARE=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DM_ETH=y ++CONFIG_PHY_GIGE=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_RGMII=y ++CONFIG_MII=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_ROCKCHIP_SDRAM_COMMON=y ++CONFIG_DM_RESET=y ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_DM_USB_GADGET=y ++CONFIG_SPL_DM_USB_GADGET=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC2=y ++CONFIG_USB_DWC3=y ++CONFIG_ROCKCHIP_USB2_PHY=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DWC2_OTG=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_EXT4_WRITE=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_LZO=y ++CONFIG_ERRNO_STR=y ++# CONFIG_EFI_LOADER is not set diff --git a/patch/u-boot/u-boot-media/0060-add-board-tinker-board-2.patch b/patch/u-boot/u-boot-media/0060-add-board-tinker-board-2.patch new file mode 100644 index 000000000..9d2472ff8 --- /dev/null +++ b/patch/u-boot/u-boot-media/0060-add-board-tinker-board-2.patch @@ -0,0 +1,897 @@ +From 967e0da33c720f06e59473680e2ba08eb9fa769d Mon Sep 17 00:00:00 2001 +From: tonymac32 +Date: Tue, 2 Mar 2021 15:49:01 -0500 +Subject: [PATCH] Patching something + +Signed-off-by: tonymac32 +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3399-tinker-2-u-boot.dtsi | 60 ++ + arch/arm/dts/rk3399-tinker-2.dts | 511 ++++++++++++++++++ + arch/arm/mach-rockchip/rk3399/Kconfig | 8 +- + board/rockchip/tinker-2_rk3399/Kconfig | 15 + + board/rockchip/tinker-2_rk3399/Makefile | 7 + + .../tinker-2_rk3399/tinker-2-rk3399.c | 56 ++ + configs/tinker-2-rk3399_defconfig | 79 +++ + drivers/power/pmic/fan53555.c | 1 + + drivers/power/regulator/fan53555.c | 2 + + include/configs/tinker-2_rk3399.h | 22 + + include/power/fan53555.h | 1 + + 14 files changed, 767 insertions(+), 3 deletions(-) + create mode 100644 arch/arm/dts/rk3399-tinker-2-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3399-tinker-2.dts + create mode 100644 board/rockchip/tinker-2_rk3399/Kconfig + create mode 100644 board/rockchip/tinker-2_rk3399/Makefile + create mode 100644 board/rockchip/tinker-2_rk3399/tinker-2-rk3399.c + create mode 100644 configs/tinker-2-rk3399_defconfig + create mode 100644 include/configs/tinker-2_rk3399.h + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 06ccc03e..2919b8b2 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -145,6 +145,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + rk3399-rock-pi-4c.dtb \ + rk3399-rock960.dtb \ + rk3399-rockpro64.dtb \ ++ rk3399-tinker-2.dtb \ + rk3399pro-rock-pi-n10.dtb + + dtb-$(CONFIG_ROCKCHIP_RV1108) += \ +diff --git a/arch/arm/dts/rk3399-tinker-2-u-boot.dtsi b/arch/arm/dts/rk3399-tinker-2-u-boot.dtsi +new file mode 100644 +index 00000000..02a8f9f5 +--- /dev/null ++++ b/arch/arm/dts/rk3399-tinker-2-u-boot.dtsi +@@ -0,0 +1,60 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2021 Thomas McKahan ++ */ ++ ++#include "rk3399-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc ; ++ }; ++}; ++ ++ ++ ++&i2c0 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&i2c2 { ++ u-boot,dm-pre-reloc; ++ ++}; ++ ++&rk808 { ++ u-boot,dm-pre-reloc; ++}; ++ ++&rng { ++ status = "okay"; ++}; ++ ++&sdhci { ++ max-frequency = <25000000>; ++ u-boot,dm-pre-reloc; ++}; ++ ++&sdmmc { ++ max-frequency = <20000000>; ++ u-boot,dm-pre-reloc; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&vdd_center { ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <950000>; ++}; ++ ++&vdd_log { ++ regulator-init-microvolt = <950000>; ++}; +diff --git a/arch/arm/dts/rk3399-tinker-2.dts b/arch/arm/dts/rk3399-tinker-2.dts +new file mode 100644 +index 00000000..7372f25a +--- /dev/null ++++ b/arch/arm/dts/rk3399-tinker-2.dts +@@ -0,0 +1,511 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd ++ */ ++ ++/dts-v1/; ++#include ++#include "rk3399.dtsi" ++#include "rk3399-op1-opp.dtsi" ++ ++/ { ++ model = "Asus Tinker Board 2"; ++ compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_phy: vcc-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_phy"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ regulator-name = "vdd_log"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ /* for rockchip boot on */ ++ rockchip,pwm_id= <2>; ++ rockchip,pwm_voltage = <900000>; ++ }; ++ ++ xin32k: xin32k { ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++ clock-output-names = "xin32k"; ++ #clock-cells = <0>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_phy>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 16000 72000>; ++ tx_delay = <0x25>; ++ rx_delay = <0x20>; ++ wakeup-enable = "0"; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <18 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ #clock-cells = <1>; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ vcc10-supply = <&vcc3v3_sys>; ++ vcc11-supply = <&vcc3v3_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc1v8_pmu>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc3v3_dsi: LDO_REG1 { ++ regulator-name = "vcc3v3_dsi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_hdmi: LDO_REG2 { ++ regulator-name = "vcca1v8_hdmi"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu: LDO_REG3 { ++ regulator-name = "vcc1v8_pmu"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG4 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_csi: LDO_REG5 { ++ regulator-name = "vcc3v3_csi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca0v9_hdmi: LDO_REG7 { ++ regulator-name = "vcca0v9_hdmi"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: vdd_cpu_b { ++ compatible = "fcs,fan53200"; ++ reg = <0x60>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-compatible = "fan53555-regulator"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel1_gpio>; ++ vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1250000>; ++ regulator-ramp-delay = <1000>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ status = "okay"; ++ ++ regulator-initial-state = <3>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c4 { ++ ++ status = "okay"; ++ i2c-scl-rising-time-ns = <475>; ++ i2c-scl-falling-time-ns = <26>; ++ fusb0: fusb30x@22 { ++ compatible = "fairchild,fusb302"; ++ reg = <0x22>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; ++ //vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ vdd_gpu: vdd_gpu { ++ compatible = "fcs,fan53200"; ++ reg = <0x60>; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-compatible = "fan53555-regulator"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel2_gpio>; ++ vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-ramp-delay = <1000>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ status = "okay"; ++ ++ regulator-initial-state = <3>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&pcie_phy { ++ status = "disabled"; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; ++ num-lanes = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_clkreqn_cpm>; ++ status = "disabled"; ++}; ++ ++&pwm0 { ++ status = "disabled"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++ pinctrl-names = "active"; ++ pinctrl-0 = <&pwm2_pin_pull_down>; ++}; ++ ++&pwm3 { ++ status = "disabled"; ++}; ++ ++&saradc { ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ supports-emmc; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ keep-power-in-suspend; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ clock-frequency = <150000000>; ++ clock-freq-min-max = <100000 150000000>; ++ supports-sd; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ disable-wp; ++ num-slots = <1>; ++ //sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_s3>; ++ vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <1 18 RK_FUNC_GPIO &pcfg_pull_up>, ++ <0 9 RK_FUNC_GPIO &pcfg_pull_none>; /* GPIO0_B1 */ ++ }; ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = ++ <1 17 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = ++ <1 14 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = ++ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb30x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; +diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig +index 7890bafe..8215116e 100644 +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -105,7 +105,12 @@ config TARGET_ROCKPRO64_RK3399 + * USB Type C power and data + * GPIO expansion ports + * DC 12V/2A +- ++ ++config TARGET_TINKER-2_RK3399 ++ bool "Asus Tinker Board 2" ++ help ++ Tinker Board 2 ++ + config TARGET_ROC_PC_RK3399 + bool "Firefly ROC-RK3399-PC board" + help +@@ -175,5 +180,6 @@ source "board/pine64/rockpro64_rk3399/Kconfig" + source "board/rockchip/evb_rk3399/Kconfig" + source "board/theobroma-systems/puma_rk3399/Kconfig" + source "board/vamrs/rock960_rk3399/Kconfig" ++source "board/rockchip/tinker-2_rk3399/Kconfig" + + endif +diff --git a/board/rockchip/tinker-2_rk3399/Kconfig b/board/rockchip/tinker-2_rk3399/Kconfig +new file mode 100644 +index 00000000..ce5d8b18 +--- /dev/null ++++ b/board/rockchip/tinker-2_rk3399/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_TINKER-2_RK3399 ++ ++config SYS_BOARD ++ default "tinker-2_rk3399" ++ ++config SYS_VENDOR ++ default "rockchip" ++ ++config SYS_CONFIG_NAME ++ default "tinker-2_rk3399" ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ ++endif +diff --git a/board/rockchip/tinker-2_rk3399/Makefile b/board/rockchip/tinker-2_rk3399/Makefile +new file mode 100644 +index 00000000..21218f2a +--- /dev/null ++++ b/board/rockchip/tinker-2_rk3399/Makefile +@@ -0,0 +1,7 @@ ++# ++# (C) Copyright 2019 Vasily Khoruzhick ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += tinker-2-rk3399.o +diff --git a/board/rockchip/tinker-2_rk3399/tinker-2-rk3399.c b/board/rockchip/tinker-2_rk3399/tinker-2-rk3399.c +new file mode 100644 +index 00000000..d7908461 +--- /dev/null ++++ b/board/rockchip/tinker-2_rk3399/tinker-2-rk3399.c +@@ -0,0 +1,56 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2019 Vasily Khoruzhick ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define GRF_IO_VSEL_BT565_SHIFT 0 ++#define PMUGRF_CON0_VSEL_SHIFT 8 ++ ++#ifdef CONFIG_MISC_INIT_R ++static void setup_iodomain(void) ++{ ++ struct rk3399_grf_regs *grf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ struct rk3399_pmugrf_regs *pmugrf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); ++ ++ /* BT565 is in 1.8v domain */ ++ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_BT565_SHIFT); ++ ++ /* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL */ ++ rk_setreg(&pmugrf->soc_con0, 1 << PMUGRF_CON0_VSEL_SHIFT); ++} ++ ++int misc_init_r(void) ++{ ++ const u32 cpuid_offset = 0x7; ++ const u32 cpuid_length = 0x10; ++ u8 cpuid[cpuid_length]; ++ int ret; ++ ++ setup_iodomain(); ++ ++ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_cpuid_set(cpuid, cpuid_length); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_setup_macaddr(); ++ ++ return ret; ++} ++ ++#endif +diff --git a/configs/tinker-2-rk3399_defconfig b/configs/tinker-2-rk3399_defconfig +new file mode 100644 +index 00000000..de9c2692 +--- /dev/null ++++ b/configs/tinker-2-rk3399_defconfig +@@ -0,0 +1,79 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x8000 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_TINKER-2_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++ ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-tinker-2" ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-tinker-2.dtb" ++CONFIG_MISC_INIT_R=y ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++ ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_ROCKUSB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_PMIC_FAN53555=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_DM_RESET=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++# CONFIG_VIDEO_BPP8 is not set ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y +diff --git a/drivers/power/pmic/fan53555.c b/drivers/power/pmic/fan53555.c +index 4d1e686d..8fba05ff 100644 +--- a/drivers/power/pmic/fan53555.c ++++ b/drivers/power/pmic/fan53555.c +@@ -73,6 +73,7 @@ static struct dm_pmic_ops pmic_fan53555_ops = { + + static const struct udevice_id pmic_fan53555_match[] = { + { .compatible = "fcs,fan53555", .data = FAN53555_VENDOR_FAIRCHILD, }, ++ { .compatible = "fcs,fan53200", .data = FAN53200_VENDOR_FAIRCHILD, }, + { .compatible = "silergy,syr827", .data = FAN53555_VENDOR_SILERGY, }, + { .compatible = "silergy,syr828", .data = FAN53555_VENDOR_SILERGY, }, + { }, +diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c +index b407f555..89ba851f 100644 +--- a/drivers/power/regulator/fan53555.c ++++ b/drivers/power/regulator/fan53555.c +@@ -55,6 +55,8 @@ static const struct { + { FAN53555_VENDOR_FAIRCHILD, 0x8, 0x1, true, 600000, 10000 }, + /* Option 08 */ + { FAN53555_VENDOR_FAIRCHILD, 0x8, 0xf, true, 600000, 10000 }, ++ /* FAN53200 */ ++ { FAN53200_VENDOR_FAIRCHILD, 0x0, 0x0, false, 600000, 12500 }, + /* Option 09 */ + { FAN53555_VENDOR_FAIRCHILD, 0xc, 0xf, true, 603000, 12826 }, + /* SYL82X */ +diff --git a/include/configs/tinker-2_rk3399.h b/include/configs/tinker-2_rk3399.h +new file mode 100644 +index 00000000..36315602 +--- /dev/null ++++ b/include/configs/tinker-2_rk3399.h +@@ -0,0 +1,22 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2021 Thomas McKahan ++ */ ++ ++#ifndef __TINKER_2_RK3399_H ++#define __TINKER_2_RK3399_H ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdin=serial,usbkbd\0" \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#include ++ ++#define SDRAM_BANK_SIZE (2UL << 30) ++ ++#define CONFIG_USB_OHCI_NEW ++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 ++ ++ ++#endif +diff --git a/include/power/fan53555.h b/include/power/fan53555.h +index c039f060..8a50593c 100644 +--- a/include/power/fan53555.h ++++ b/include/power/fan53555.h +@@ -7,6 +7,7 @@ + #define _FAN53555_H_ + + enum fan53555_vendor { ++ FAN53200_VENDOR_FAIRCHILD, + FAN53555_VENDOR_FAIRCHILD, + FAN53555_VENDOR_SILERGY, + }; +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/u-boot/u-boot-media/010-add-trust-ini.patch b/patch/u-boot/u-boot-media/0070-add-trust-ini.patch similarity index 100% rename from patch/u-boot/u-boot-media/010-add-trust-ini.patch rename to patch/u-boot/u-boot-media/0070-add-trust-ini.patch diff --git a/patch/u-boot/u-boot-media/0080-board-pinebook-pro-0003-spi-flash-support.patch b/patch/u-boot/u-boot-media/0080-board-pinebook-pro-0003-spi-flash-support.patch new file mode 100644 index 000000000..9675edb17 --- /dev/null +++ b/patch/u-boot/u-boot-media/0080-board-pinebook-pro-0003-spi-flash-support.patch @@ -0,0 +1,65 @@ +From 662f6044341d0435cf238cfa683ec6b8868ecb22 Mon Sep 17 00:00:00 2001 +From: pcm720 +Date: Sun, 28 Jun 2020 21:00:59 +0300 +Subject: [PATCH 3/4] support SPI flash boot + +Port dhivael's commit to current upstream + +Original commit contents: +From: dhivael +Date: Thu, 6 Feb 2020 22:34:34 +0100 +Subject: support SPI flash boot + +SPI uboot images can be built with + + tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl-dtb.bin:spl/u-boot-spl-dtb.bin spl.bin + cat <(dd if=spl.bin bs=512K conv=sync) u-boot.itb >spiflash.bin + +and written to spi flash with uboot sf commands, any hardware flasher +available, rkdeveloptool, or possibly other methods. +--- + arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 6 +++++- + configs/pinebook-pro-rk3399_defconfig | 9 +++++++++ + 2 files changed, 14 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +index 1a2e24d3ef..4a5a0969b5 100644 +--- a/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi +@@ -12,7 +12,7 @@ + }; + + chosen { +- u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc; ++ u-boot,spl-boot-order = "same-as-spl", &spiflash, &sdhci, &sdmmc; + }; + }; + +@@ -41,3 +41,7 @@ + &vdd_log { + regulator-init-microvolt = <950000>; + }; ++ ++&pcie0 { ++ u-boot,dm-pre-reloc; ++}; +diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig +index 0c129b9aeb..76e5f36d58 100644 +--- a/configs/pinebook-pro-rk3399_defconfig ++++ b/configs/pinebook-pro-rk3399_defconfig +@@ -78,3 +78,12 @@ CONFIG_VIDEO_ROCKCHIP=y + CONFIG_DISPLAY_ROCKCHIP_EDP=y + CONFIG_SPL_TINY_MEMSET=y + CONFIG_ERRNO_STR=y ++CONFIG_CMD_NVME=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPL_DM_SPI=y ++CONFIG_SPL_SPI_FLASH_TINY=n ++CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +-- +2.27.0 + diff --git a/patch/u-boot/u-boot-media/0090-board-pinebook-pro-0005-panel-reset.patch b/patch/u-boot/u-boot-media/0090-board-pinebook-pro-0005-panel-reset.patch new file mode 100644 index 000000000..59f21c9e8 --- /dev/null +++ b/patch/u-boot/u-boot-media/0090-board-pinebook-pro-0005-panel-reset.patch @@ -0,0 +1,62 @@ +From 352cb7b28bf4a16330f148043e8d10b0141bbfcb Mon Sep 17 00:00:00 2001 +From: Arnaud Patard +Date: Wed, 8 Jul 2020 21:43:36 -0400 +Subject: [PATCH 4/4] PBP: Fix panel reset + +On warm reset, the pinebook pro panel is not working correctly. +The issue is not yet debugged so, for now, this hack seems to be +enough. It toggles the GPIO1_C6 gpio [ LCDVCC_EN signal in the +schematics ] used by the vcc3v3_panel regulator. + +There's no gpio_request, since the gpio is already in use at this +stage, so it can only fail. + +Origin: http://people.hupstream.com/~rtp/pbp/20200706/patches/hack-reset.patch +--- + board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c +index 516292aaa59..ff9c916bcb7 100644 +--- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c ++++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c +@@ -7,13 +7,15 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include ++#include + #include + #include + #include +- + #define GRF_IO_VSEL_BT565_SHIFT 0 + #define PMUGRF_CON0_VSEL_SHIFT 8 + +@@ -59,6 +61,7 @@ int misc_init_r(void) + const u32 cpuid_length = 0x10; + u8 cpuid[cpuid_length]; + int ret; ++ unsigned int gpio; + + setup_iodomain(); + +@@ -70,6 +73,11 @@ int misc_init_r(void) + if (ret) + return ret; + ++ gpio_lookup_name("B22", NULL, NULL, &gpio); ++ gpio_direction_output(gpio, 0); ++ udelay(500000); ++ gpio_direction_output(gpio, 1); ++ + return ret; + } + #endif +-- +2.25.4 + diff --git a/patch/u-boot/u-boot-media/0100-board-pinebook-pro-0007-increase-nvme-timeout.patch b/patch/u-boot/u-boot-media/0100-board-pinebook-pro-0007-increase-nvme-timeout.patch new file mode 100644 index 000000000..9939df048 --- /dev/null +++ b/patch/u-boot/u-boot-media/0100-board-pinebook-pro-0007-increase-nvme-timeout.patch @@ -0,0 +1,31 @@ +From 656ccd6ac62714b11b163b6eb62370a78c7bc808 Mon Sep 17 00:00:00 2001 +From: pcm720 +Date: Mon, 20 Jul 2020 20:33:26 +0300 +Subject: [PATCH] drivers: nvme: address NVMe instability for Pinebook Pro + +Apparently, some NVMe SSDs on Pinebook Pro don't become ready before timeout specified in drive's CAP register expires. +The workaround is to increase timeout. Tested and confirmed to work on Intel 660p. +--- + drivers/nvme/nvme.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c +index fc64d93ab8..138b9f8fbb 100644 +--- a/drivers/nvme/nvme.c ++++ b/drivers/nvme/nvme.c +@@ -61,6 +61,12 @@ static int nvme_wait_ready(struct nvme_dev *dev, bool enabled) + + /* Timeout field in the CAP register is in 500 millisecond units */ + timeout = NVME_CAP_TIMEOUT(dev->cap) * 500; ++ ++ #ifdef CONFIG_TARGET_PINEBOOK_PRO_RK3399 ++ /* Some NVMe SSDs on Pinebook Pro don't become ready before timeout expires. ++ Workaround: increase timeout */ ++ timeout *= 2; ++ #endif + + start = get_timer(0); + while (get_timer(start) < timeout) { +-- +2.27.0 + diff --git a/patch/u-boot/u-boot-media/0110-board-rockpro64-advanced-recovery.patch b/patch/u-boot/u-boot-media/0110-board-rockpro64-advanced-recovery.patch new file mode 100644 index 000000000..c5e0a7ea7 --- /dev/null +++ b/patch/u-boot/u-boot-media/0110-board-rockpro64-advanced-recovery.patch @@ -0,0 +1,27 @@ +diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig +index ad0c6ab2..57e129ac 100644 +--- a/configs/rockpro64-rk3399_defconfig ++++ b/configs/rockpro64-rk3399_defconfig +@@ -24,6 +24,11 @@ CONFIG_CMD_GPT=y + CONFIG_CMD_MMC=y + CONFIG_CMD_PCI=y + CONFIG_CMD_USB=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_ROCKUSB=y ++CONFIG_CMD_USB_MASS_STORAGE=y + # CONFIG_CMD_SETEXPR is not set + CONFIG_CMD_TIME=y + CONFIG_SPL_OF_CONTROL=y +@@ -71,6 +76,10 @@ CONFIG_USB_EHCI_HCD=y + CONFIG_USB_DWC3=y + CONFIG_USB_DWC3_GENERIC=y + CONFIG_USB_KEYBOARD=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_FUNCTION_ROCKUSB=y ++CONFIG_ROCKCHIP_ADVANCED_RECOVERY=y ++CONFIG_ROCKCHIP_ADVANCED_RECOVERY_LED="work" + CONFIG_USB_HOST_ETHER=y + CONFIG_USB_ETHER_ASIX=y + CONFIG_USB_ETHER_ASIX88179=y diff --git a/patch/u-boot/u-boot-media/160-enable-DT-overlays-support.patch b/patch/u-boot/u-boot-media/0120-enable-DT-overlays-support.patch similarity index 100% rename from patch/u-boot/u-boot-media/160-enable-DT-overlays-support.patch rename to patch/u-boot/u-boot-media/0120-enable-DT-overlays-support.patch diff --git a/patch/u-boot/u-boot-media/170-general-add-xtx-spi-nor-chips.patch b/patch/u-boot/u-boot-media/0130-general-add-xtx-spi-nor-chips.patch similarity index 100% rename from patch/u-boot/u-boot-media/170-general-add-xtx-spi-nor-chips.patch rename to patch/u-boot/u-boot-media/0130-general-add-xtx-spi-nor-chips.patch diff --git a/patch/u-boot/u-boot-media/0140-general-set-eth1addr.patch b/patch/u-boot/u-boot-media/0140-general-set-eth1addr.patch new file mode 100644 index 000000000..422cbc3f9 --- /dev/null +++ b/patch/u-boot/u-boot-media/0140-general-set-eth1addr.patch @@ -0,0 +1,16 @@ +diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c +index 6dbb9bde..89f3a918 100644 +--- a/arch/arm/mach-rockchip/misc.c ++++ b/arch/arm/mach-rockchip/misc.c +@@ -50,6 +50,11 @@ int rockchip_setup_macaddr(void) + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_env_set_enetaddr("ethaddr", mac_addr); ++ ++ /* Make a valid MAC address for eth1 too */ ++ mac_addr[5] += 0x20; ++ mac_addr[5] &= 0xff; ++ eth_env_set_enetaddr("eth1addr", mac_addr); + #endif + return 0; + } diff --git a/patch/u-boot/u-boot-media/0150-general-support-recovery-button.patch b/patch/u-boot/u-boot-media/0150-general-support-recovery-button.patch new file mode 100644 index 000000000..4916885c7 --- /dev/null +++ b/patch/u-boot/u-boot-media/0150-general-support-recovery-button.patch @@ -0,0 +1,224 @@ +From ff72515d3f6e65e22baa8cb1fbefe15540256310 Mon Sep 17 00:00:00 2001 +From: Piotr Szczepanik +Date: Sun, 4 Oct 2020 18:19:02 +0200 +Subject: [PATCH] Enabled advanced recovery button support for rockchip + +It allows to enter either ums, fastboot or rockusb based on the time the +button is pressed. +SD (mmc0) is preferred if present with eMMC (mmc1) set as fallback. + +Based on: + https://github.com/ayufan-rock64/linux-u-boot/commit/ea6efecdfecc57c853a6f32f78469d1b2417329b + https://github.com/ayufan-rock64/linux-u-boot/commit/1abc9ab51306200880c434c2069eceb4be7789e9 + +Signed-off-by: Piotr Szczepanik + +diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig +index 0cb1f23d..09807cdc 100644 +--- a/arch/arm/mach-rockchip/Kconfig ++++ b/arch/arm/mach-rockchip/Kconfig +@@ -366,6 +366,31 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM + config SPL_MMC_SUPPORT + default y if !SPL_ROCKCHIP_BACK_TO_BROM + ++config ROCKCHIP_ADVANCED_RECOVERY ++ bool "Advanced recovery button for Rockchip boards" ++ default n ++ ++config ROCKCHIP_ADVANCED_RECOVERY_LED ++ string "Advanced recovery button for Rockchip boards - toggled led label" ++ depends on ROCKCHIP_ADVANCED_RECOVERY ++ ++config ROCKCHIP_ADVANCED_RECOVERY_UMS ++ bool "Advanced recovery for Rockchip boards - UMS support" ++ depends on ROCKCHIP_ADVANCED_RECOVERY ++ depends on CMD_USB_MASS_STORAGE ++ default y if ROCKCHIP_ADVANCED_RECOVERY ++ ++config ROCKCHIP_ADVANCED_RECOVERY_ROCKUSB ++ bool "Advanced recovery for Rockchip boards - ROCKUSB support" ++ depends on ROCKCHIP_ADVANCED_RECOVERY ++ depends on CMD_ROCKUSB ++ default y if ROCKCHIP_ADVANCED_RECOVERY ++ ++config ROCKCHIP_ADVANCED_RECOVERY_MASKROM ++ bool "Advanced recovery for Rockchip boards - MASKROM support" ++ depends on ROCKCHIP_ADVANCED_RECOVERY ++ default y if ROCKCHIP_ADVANCED_RECOVERY ++ + source "arch/arm/mach-rockchip/px30/Kconfig" + source "arch/arm/mach-rockchip/rk3036/Kconfig" + source "arch/arm/mach-rockchip/rk3128/Kconfig" +diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c +index 21589341..c4dcb15e 100644 +--- a/arch/arm/mach-rockchip/boot_mode.c ++++ b/arch/arm/mach-rockchip/boot_mode.c +@@ -8,6 +8,9 @@ + #include + #include ++#include + #include ++#include ++#include + #include + #include + #include +@@ -70,13 +71,158 @@ __weak int rockchip_dnl_key_pressed(void) + return false; + } + ++#if defined(CONFIG_ROCKCHIP_ADVANCED_RECOVERY) ++#define RECOVERY_LED_BY_LABEL(dev) led_get_by_label(CONFIG_ROCKCHIP_ADVANCED_RECOVERY_LED, dev) ++void rockchip_blink_recovery_led(int times) ++{ ++ struct udevice *dev; ++ RECOVERY_LED_BY_LABEL(&dev); ++ for (int i = 0; i < times; ++i) { ++ led_set_state(dev, LEDST_ON); ++ mdelay(100); ++ led_set_state(dev, LEDST_OFF); ++ mdelay(100); ++ } ++} ++ ++int rockchip_dnl_mode(int num_modes) ++{ ++ int mode = 0; ++ const char *mode_names[5] = { ++ "none", ++ "ums", ++ "rockusb", ++ "fastboot", ++ "maskrom" ++ }; ++ ++ const int modes_enabled[5] = { ++ 1, ++#if defined(CONFIG_ROCKCHIP_ADVANCED_RECOVERY_UMS) ++ 1, ++#else ++ 0, ++#endif ++#if defined(CONFIG_ROCKCHIP_ADVANCED_RECOVERY_ROCKUSB) ++ 1, ++#else ++ 0, ++#endif ++#if defined(CONFIG_ROCKCHIP_ADVANCED_RECOVERY_FASTBOOT) ++ 1, ++#else ++ 0, ++#endif ++#if defined(CONFIG_ROCKCHIP_ADVANCED_RECOVERY_MASKROM) ++ 1, ++#else ++ 0, ++#endif ++ }; ++ ++ while(mode < num_modes) { ++ ++mode; ++ ++ if (modes_enabled[mode]) { ++ printf("rockchip_dnl_mode = %s mode\n", mode_names[mode]); ++ rockchip_blink_recovery_led(mode); ++ ++ // return early ++ if (mode == num_modes) { ++ goto end; ++ } ++ ++ // wait 2 seconds ++ for (int i = 0; i < 100; ++i) { ++ if (!rockchip_dnl_key_pressed()) { ++ goto end; ++ } ++ mdelay(20); ++ } ++ } ++ } ++ ++end: ++ return mode; ++} ++ ++__weak void rockchip_prepare_download_mode(void) ++{ ++} ++ ++int rockchip_has_mmc_device(int devnum) ++{ ++ struct mmc *mmc; ++ mmc = find_mmc_device(devnum); ++ if (!mmc || mmc_init(mmc)) ++ return 0; ++ else ++ return 1; ++} ++#endif ++ + void rockchip_dnl_mode_check(void) + { ++#if defined(CONFIG_ROCKCHIP_ADVANCED_RECOVERY) ++ int mmc_device = 0; ++ int ret = 0; ++ char cmd[32]; ++ ++ if (!rockchip_dnl_key_pressed()) { ++ return 0; ++ } ++ ++ if (rockchip_has_mmc_device(0)) { ++ mmc_device = 0; ++ } else if (rockchip_has_mmc_device(1)) { ++ mmc_device = 1; ++ } else { ++ printf("no mmc device suitable for download mode!\n"); ++ return 0; ++ } ++ ++ printf("using mmc%d device for download mode\n", mmc_device); ++ ++ switch(rockchip_dnl_mode(4)) { ++ case 0: ++ return; ++ ++ case 1: ++ printf("entering ums mode...\n"); ++ rockchip_prepare_download_mode(); ++ sprintf(cmd, "ums 0 mmc %d", mmc_device); ++ cli_simple_run_command(cmd, 0); ++ break; ++ ++ case 2: ++ printf("entering rockusb mode...\n"); ++ rockchip_prepare_download_mode(); ++ sprintf(cmd, "rockusb 0 mmc %d", mmc_device); ++ cli_simple_run_command(cmd, 0); ++ break; ++ ++ case 3: ++ printf("entering fastboot mode...\n"); ++ rockchip_prepare_download_mode(); ++ sprintf(cmd, "mmc dev %d; fastboot usb 0", mmc_device); ++ cli_simple_run_command(cmd, 0); ++ break; ++ ++ case 4: ++ printf("entering maskrom mode...\n"); ++ rockchip_prepare_download_mode(); ++ break; ++ } ++ ++ set_back_to_bootrom_dnl_flag(); ++ do_reset(NULL, 0, 0, NULL); ++#else + if (rockchip_dnl_key_pressed()) { + printf("download key pressed, entering download mode..."); + set_back_to_bootrom_dnl_flag(); + do_reset(NULL, 0, 0, NULL); + } ++#endif + } + + int setup_boot_mode(void) diff --git a/patch/u-boot/u-boot-media/0160-general-support-rmii-integrated-phy.patch b/patch/u-boot/u-boot-media/0160-general-support-rmii-integrated-phy.patch new file mode 100644 index 000000000..97ca6684a --- /dev/null +++ b/patch/u-boot/u-boot-media/0160-general-support-rmii-integrated-phy.patch @@ -0,0 +1,849 @@ +diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts +index 632cdc9bc3..f868524ae1 100644 +--- a/arch/arm/dts/rk3229-evb.dts ++++ b/arch/arm/dts/rk3229-evb.dts +@@ -50,19 +50,25 @@ + }; + + &gmac { +- assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; +- assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; +- clock_in_out = "input"; +- phy-supply = <&vcc_phy>; +- phy-mode = "rgmii"; +- pinctrl-names = "default"; +- pinctrl-0 = <&rgmii_pins>; +- snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- snps,reset-delays-us = <0 10000 1000000>; +- tx_delay = <0x30>; +- rx_delay = <0x10>; +- status = "okay"; ++ assigned-clocks = <&cru SCLK_MAC_SRC>; ++ assigned-clock-rates = <50000000>; ++ clock_in_out = "output"; ++ phy-supply = <&vcc_phy>; ++ phy-mode = "rmii"; ++ phy-handle = <&phy>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy: phy@0 { ++ compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ phy-is-integrated; ++ }; ++ }; + }; + + &emmc { +diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi +index 4a8be5dabb..3c2861f271 100644 +--- a/arch/arm/dts/rk322x.dtsi ++++ b/arch/arm/dts/rk322x.dtsi +@@ -448,13 +448,13 @@ + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, +- <&cru PCLK_GMAC>; ++ <&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", +- "pclk_mac"; +- resets = <&cru SRST_GMAC>; +- reset-names = "stmmaceth"; ++ "pclk_mac", "clk_macphy"; ++ resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>; ++ reset-names = "stmmaceth", "mac-phy"; + rockchip,grf = <&grf>; + status = "disabled"; + }; +diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +index c87c830716..15039c87be 100644 +--- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h ++++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +@@ -12,6 +12,7 @@ + + #define APLL_HZ (600 * MHz) + #define GPLL_HZ (594 * MHz) ++#define CPLL_HZ (500 * MHz) + + #define CORE_PERI_HZ 150000000 + #define CORE_ACLK_HZ 300000000 +diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig +index f8e648bbb4..5fd2bd3ba2 100644 +--- a/configs/evb-rk3229_defconfig ++++ b/configs/evb-rk3229_defconfig +@@ -58,6 +58,8 @@ CONFIG_GMAC_ROCKCHIP=y + CONFIG_PHY=y + CONFIG_PINCTRL=y + CONFIG_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_RESET_ROCKCHIP=y + CONFIG_SPL_RAM=y + CONFIG_TPL_RAM=y + CONFIG_BAUDRATE=1500000 +diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig +index 5bbdc00214..19c09e4503 100644 +--- a/configs/evb-rk3328_defconfig ++++ b/configs/evb-rk3328_defconfig +@@ -71,6 +71,8 @@ CONFIG_DM_REGULATOR_FIXED=y + CONFIG_REGULATOR_RK8XX=y + CONFIG_PWM_ROCKCHIP=y + CONFIG_RAM=y ++CONFIG_DM_RESET=y ++CONFIG_RESET_ROCKCHIP=y + CONFIG_SPL_RAM=y + CONFIG_TPL_RAM=y + CONFIG_BAUDRATE=1500000 +diff --git a/doc/device-tree-bindings/net/phy.txt b/doc/device-tree-bindings/net/phy.txt +index 6599c667b5..ca1a4a8526 100644 +--- a/doc/device-tree-bindings/net/phy.txt ++++ b/doc/device-tree-bindings/net/phy.txt +@@ -8,6 +8,19 @@ Required properties: + + - reg : The ID number for the phy, usually a small integer + ++Optional Properties: ++ ++- compatible: Compatible list, may contain ++ "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for ++ PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45 ++ specifications. If neither of these are specified, the default is to ++ assume clause 22. ++ ++- phy-is-integrated: If set, indicates that the PHY is integrated into the same ++ physical package as the Ethernet MAC. If needed, muxers should be configured ++ to ensure the integrated PHY is used. The absence of this property indicates ++ the muxers should be configured so that the external PHY is used. ++ + Example: + + ethernet-phy@0 { +diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c +index ef33adbf29..c427e0438b 100644 +--- a/drivers/clk/rockchip/clk_rk322x.c ++++ b/drivers/clk/rockchip/clk_rk322x.c +@@ -38,6 +38,7 @@ enum { + /* use integer mode*/ + static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); + static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); ++static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 3, 1); + + static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div) +@@ -87,11 +88,13 @@ static void rkclk_init(struct rk322x_cru *cru) + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | APLL_MODE_MASK, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | +- APLL_MODE_SLOW << APLL_MODE_SHIFT); ++ APLL_MODE_SLOW << APLL_MODE_SHIFT | ++ CPLL_MODE_SLOW << CPLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); ++ rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg); + + /* + * select apll as cpu/core clock pll source and +@@ -164,7 +167,8 @@ static void rkclk_init(struct rk322x_cru *cru) + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | APLL_MODE_MASK, + GPLL_MODE_NORM << GPLL_MODE_SHIFT | +- APLL_MODE_NORM << APLL_MODE_SHIFT); ++ APLL_MODE_NORM << APLL_MODE_SHIFT | ++ CPLL_MODE_NORM << CPLL_MODE_SHIFT); + } + + /* Get pll rate by id */ +@@ -254,11 +258,10 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) + ulong pll_rate; + u8 div; + +- if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) ++ if (con & MAC_PLL_SEL_MASK) + pll_rate = GPLL_HZ; + else +- /* CPLL is not set */ +- return -EPERM; ++ pll_rate = CPLL_HZ; + + div = DIV_ROUND_UP(pll_rate, freq) - 1; + if (div <= 0x1f) +@@ -387,6 +390,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) + case CLK_DDR: + new_rate = rk322x_ddr_set_clk(priv->cru, rate); + break; ++ case SCLK_MAC_SRC: + case SCLK_MAC: + new_rate = rk322x_mac_set_clk(priv->cru, rate); + break; +diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c +index 8e867c58df..ba2b34c626 100644 +--- a/drivers/clk/rockchip/clk_rk3328.c ++++ b/drivers/clk/rockchip/clk_rk3328.c +@@ -93,6 +93,14 @@ enum { + PCLK_DBG_DIV_SHIFT = 0, + PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT, + ++ /* CLKSEL_CON26 */ ++ GMAC2PHY_PLL_SEL_SHIFT = 7, ++ GMAC2PHY_PLL_SEL_MASK = 1 << GMAC2PHY_PLL_SEL_SHIFT, ++ GMAC2PHY_PLL_SEL_CPLL = 0, ++ GMAC2PHY_PLL_SEL_GPLL = 1, ++ GMAC2PHY_CLK_DIV_MASK = 0x1f, ++ GMAC2PHY_CLK_DIV_SHIFT = 0, ++ + /* CLKSEL_CON27 */ + GMAC2IO_PLL_SEL_SHIFT = 7, + GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT, +@@ -440,6 +448,39 @@ static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate) + return ret; + } + ++static ulong rk3328_gmac2phy_src_set_clk(struct rk3328_cru *cru, ulong rate) ++{ ++ u32 con = readl(&cru->clksel_con[26]); ++ ulong pll_rate; ++ u8 div; ++ ++ if ((con >> GMAC2PHY_PLL_SEL_SHIFT) & GMAC2PHY_PLL_SEL_GPLL) ++ pll_rate = GPLL_HZ; ++ else ++ pll_rate = CPLL_HZ; ++ ++ div = DIV_ROUND_UP(pll_rate, rate) - 1; ++ if (div <= 0x1f) ++ rk_clrsetreg(&cru->clksel_con[26], GMAC2PHY_CLK_DIV_MASK, ++ div << GMAC2PHY_CLK_DIV_SHIFT); ++ else ++ debug("Unsupported div for gmac:%d\n", div); ++ ++ return DIV_TO_RATE(pll_rate, div); ++} ++ ++static ulong rk3328_gmac2phy_set_clk(struct rk3328_cru *cru, ulong rate) ++{ ++ struct rk3328_grf_regs *grf; ++ ++ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ if (readl(&grf->mac_con[2]) & BIT(10)) ++ /* An external clock will always generate the right rate... */ ++ return rate; ++ else ++ return rk3328_gmac2phy_src_set_clk(cru, rate); ++} ++ + static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) + { + u32 div, con, con_id; +@@ -608,6 +649,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) + case SCLK_MAC2IO: + ret = rk3328_gmac2io_set_clk(priv->cru, rate); + break; ++ case SCLK_MAC2PHY: ++ ret = rk3328_gmac2phy_set_clk(priv->cru, rate); ++ break; ++ case SCLK_MAC2PHY_SRC: ++ ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate); ++ break; + case SCLK_PWM: + ret = rk3328_pwm_set_clk(priv->cru, rate); + break; +@@ -728,6 +775,43 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent) + return -EINVAL; + } + ++static int rk3328_gmac2phy_set_parent(struct clk *clk, struct clk *parent) ++{ ++ struct rk3328_grf_regs *grf; ++ const char *clock_output_name; ++ int ret; ++ ++ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ ++ /* ++ * If the requested parent is in the same clock-controller and the id ++ * is SCLK_MAC2PHY_SRC ("clk_mac2phy_src"), switch to the internal clock. ++ */ ++ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2PHY_SRC)) { ++ debug("%s: switching MAC CLK to SCLK_MAC2IO_PHY\n", __func__); ++ rk_clrreg(&grf->mac_con[2], BIT(10)); ++ return 0; ++ } ++ ++ /* ++ * Otherwise, we need to check the clock-output-names of the ++ * requested parent to see if the requested id is "phy_50m_out". ++ */ ++ ret = dev_read_string_index(parent->dev, "clock-output-names", ++ parent->id, &clock_output_name); ++ if (ret < 0) ++ return -ENODATA; ++ ++ /* If this is "phy_50m_out", switch to the external clock input */ ++ if (!strcmp(clock_output_name, "phy_50m_out")) { ++ debug("%s: switching MAC CLK to PHY_50M_OUT\n", __func__); ++ rk_setreg(&grf->mac_con[2], BIT(10)); ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ + static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) + { + switch (clk->id) { +@@ -735,6 +819,8 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) + return rk3328_gmac2io_set_parent(clk, parent); + case SCLK_MAC2IO_EXT: + return rk3328_gmac2io_ext_set_parent(clk, parent); ++ case SCLK_MAC2PHY: ++ return rk3328_gmac2phy_set_parent(clk, parent); + case DCLK_LCDC: + case SCLK_PDM: + case SCLK_RTC32K: +diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c +index e152faf083..d3f6973043 100644 +--- a/drivers/net/gmac_rockchip.c ++++ b/drivers/net/gmac_rockchip.c +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -23,6 +24,8 @@ + #include + #include + #include ++#include ++#include + #include + #include "designware.h" + +@@ -39,21 +41,29 @@ DECLARE_GLOBAL_DATA_PTR; + struct gmac_rockchip_plat { + struct dw_eth_pdata dw_eth_pdata; + bool clock_input; ++ bool integrated_phy; ++ struct reset_ctl phy_reset; + int tx_delay; + int rx_delay; + }; + + struct rk_gmac_ops { +- int (*fix_mac_speed)(struct dw_eth_dev *priv); ++ int (*fix_rmii_speed)(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv); ++ int (*fix_rgmii_speed)(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv); + void (*set_to_rmii)(struct gmac_rockchip_plat *pdata); + void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata); ++ void (*integrated_phy_powerup)(struct gmac_rockchip_plat *pdata); + }; + + + static int gmac_rockchip_of_to_plat(struct udevice *dev) + { + struct gmac_rockchip_plat *pdata = dev_get_plat(dev); ++ struct ofnode_phandle_args args; + const char *string; ++ int ret; + + string = dev_read_string(dev, "clock_in_out"); + if (!strcmp(string, "input")) +@@ -61,6 +71,25 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev) + else + pdata->clock_input = false; + ++ /* If phy-handle property is passed from DT, use it as the PHY */ ++ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); ++ if (ret) { ++ debug("Cannot get phy phandle: ret=%d\n", ret); ++ pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); ++ } else { ++ debug("Found phy-handle subnode\n"); ++ pdata->integrated_phy = ofnode_read_bool(args.node, ++ "phy-is-integrated"); ++ } ++ ++ if (pdata->integrated_phy) { ++ ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); ++ if (ret) { ++ debug("No PHY reset control found: ret=%d\n", ret); ++ return ret; ++ } ++ } ++ + /* Check the new naming-style first... */ + pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); + pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); +@@ -74,7 +103,8 @@ static int gmac_rockchip_of_to_plat(struct udevice *dev) + return designware_eth_of_to_plat(dev); + } + +-static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv) ++static int px30_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) + { + struct px30_grf *grf; + struct clk clk_speed; +@@ -115,7 +145,43 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv) + return 0; + } + +-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) ++static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) ++{ ++ struct rk322x_grf *grf; ++ int clk; ++ enum { ++ RK3228_GMAC_RMII_CLK_MASK = BIT(7), ++ RK3228_GMAC_RMII_CLK_2_5M = 0, ++ RK3228_GMAC_RMII_CLK_25M = BIT(7), ++ ++ RK3228_GMAC_RMII_SPEED_MASK = BIT(2), ++ RK3228_GMAC_RMII_SPEED_10 = 0, ++ RK3228_GMAC_RMII_SPEED_100 = BIT(2), ++ }; ++ ++ switch (priv->phydev->speed) { ++ case 10: ++ clk = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10; ++ break; ++ case 100: ++ clk = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100; ++ break; ++ default: ++ debug("Unknown phy speed: %d\n", priv->phydev->speed); ++ return -EINVAL; ++ } ++ ++ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ rk_clrsetreg(&grf->mac_con[1], ++ RK3228_GMAC_RMII_CLK_MASK | RK3228_GMAC_RMII_SPEED_MASK, ++ clk); ++ ++ return 0; ++} ++ ++static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) + { + struct rk322x_grf *grf; + int clk; +@@ -148,7 +214,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) + return 0; + } + +-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) ++static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) + { + struct rk3288_grf *grf; + int clk; +@@ -174,7 +241,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) + return 0; + } + +-static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv) ++static int rk3308_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) + { + struct rk3308_grf *grf; + struct clk clk_speed; +@@ -215,7 +283,43 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv) + return 0; + } + +-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) ++static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) ++{ ++ struct rk3328_grf_regs *grf; ++ int clk; ++ enum { ++ RK3328_GMAC_RMII_CLK_MASK = BIT(7), ++ RK3328_GMAC_RMII_CLK_2_5M = 0, ++ RK3328_GMAC_RMII_CLK_25M = BIT(7), ++ ++ RK3328_GMAC_RMII_SPEED_MASK = BIT(2), ++ RK3328_GMAC_RMII_SPEED_10 = 0, ++ RK3328_GMAC_RMII_SPEED_100 = BIT(2), ++ }; ++ ++ switch (priv->phydev->speed) { ++ case 10: ++ clk = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10; ++ break; ++ case 100: ++ clk = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100; ++ break; ++ default: ++ debug("Unknown phy speed: %d\n", priv->phydev->speed); ++ return -EINVAL; ++ } ++ ++ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], ++ RK3328_GMAC_RMII_CLK_MASK | RK3328_GMAC_RMII_SPEED_MASK, ++ clk); ++ ++ return 0; ++} ++ ++static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) + { + struct rk3328_grf_regs *grf; + int clk; +@@ -248,7 +352,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) + return 0; + } + +-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) ++static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) + { + struct rk3368_grf *grf; + int clk; +@@ -280,7 +385,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) + return 0; + } + +-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) ++static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) + { + struct rk3399_grf_regs *grf; + int clk; +@@ -306,7 +412,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) + return 0; + } + +-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) ++static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_plat *pdata, ++ struct dw_eth_dev *priv) + { + struct rv1108_grf *grf; + int clk, speed; +@@ -357,6 +464,28 @@ static void px30_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) + PX30_GMAC_PHY_INTF_SEL_RMII); + } + ++static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) ++{ ++ struct rk322x_grf *grf; ++ enum { ++ RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), ++ RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), ++ RK3228_RMII_MODE_MASK = BIT(10), ++ RK3228_RMII_MODE_SEL = BIT(10), ++ RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), ++ RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), ++ }; ++ ++ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ rk_clrsetreg(&grf->mac_con[1], ++ RK3228_GRF_CON_RMII_MODE_MASK | ++ RK3228_RMII_MODE_MASK | ++ RK3228_GMAC_PHY_INTF_SEL_MASK, ++ RK3228_GRF_CON_RMII_MODE_SEL | ++ RK3228_RMII_MODE_SEL | ++ RK3228_GMAC_PHY_INTF_SEL_RMII); ++} ++ + static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata) + { + struct rk322x_grf *grf; +@@ -435,6 +564,25 @@ static void rk3308_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) + RK3308_GMAC_PHY_INTF_SEL_RMII); + } + ++static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) ++{ ++ struct rk3328_grf_regs *grf; ++ enum { ++ RK3328_RMII_MODE_MASK = BIT(9), ++ RK3328_RMII_MODE = BIT(9), ++ ++ RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), ++ RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), ++ }; ++ ++ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], ++ RK3328_RMII_MODE_MASK | ++ RK3328_GMAC_PHY_INTF_SEL_MASK, ++ RK3328_GMAC_PHY_INTF_SEL_RMII | ++ RK3328_RMII_MODE); ++} ++ + static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_plat *pdata) + { + struct rk3328_grf_regs *grf; +@@ -550,6 +698,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_plat *pdata) + RV1108_GMAC_PHY_INTF_SEL_RMII); + } + ++static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_plat *pdata) ++{ ++ struct rk322x_grf *grf; ++ enum { ++ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), ++ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), ++ }; ++ enum { ++ RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), ++ RK3228_MACPHY_CFG_CLK_50M = BIT(14), ++ ++ RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), ++ RK3228_MACPHY_RMII_MODE = BIT(6), ++ ++ RK3228_MACPHY_ENABLE_MASK = BIT(0), ++ RK3228_MACPHY_DISENABLE = 0, ++ RK3228_MACPHY_ENABLE = BIT(0), ++ }; ++ enum { ++ RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), ++ RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, ++ }; ++ enum { ++ RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), ++ RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, ++ }; ++ ++ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ rk_clrsetreg(&grf->con_iomux, ++ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, ++ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); ++ ++ rk_clrsetreg(&grf->macphy_con[2], ++ RK3228_RK_GRF_CON2_MACPHY_ID_MASK, ++ RK3228_RK_GRF_CON2_MACPHY_ID); ++ ++ rk_clrsetreg(&grf->macphy_con[3], ++ RK3228_RK_GRF_CON3_MACPHY_ID_MASK, ++ RK3228_RK_GRF_CON3_MACPHY_ID); ++ ++ /* disabled before trying to reset it */ ++ rk_clrsetreg(&grf->macphy_con[0], ++ RK3228_MACPHY_CFG_CLK_50M_MASK | ++ RK3228_MACPHY_RMII_MODE_MASK | ++ RK3228_MACPHY_ENABLE_MASK, ++ RK3228_MACPHY_CFG_CLK_50M | ++ RK3228_MACPHY_RMII_MODE | ++ RK3228_MACPHY_DISENABLE); ++ ++ reset_assert(&pdata->phy_reset); ++ udelay(10); ++ reset_deassert(&pdata->phy_reset); ++ udelay(10); ++ ++ rk_clrsetreg(&grf->macphy_con[0], ++ RK3228_MACPHY_ENABLE_MASK, ++ RK3228_MACPHY_ENABLE); ++ udelay(30 * 1000); ++} ++ ++static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_plat *pdata) ++{ ++ struct rk3328_grf_regs *grf; ++ enum { ++ RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), ++ RK3328_GRF_CON_RMII_MODE = BIT(9), ++ }; ++ enum { ++ RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), ++ RK3328_MACPHY_CFG_CLK_50M = BIT(14), ++ ++ RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), ++ RK3328_MACPHY_RMII_MODE = BIT(6), ++ ++ RK3328_MACPHY_ENABLE_MASK = BIT(0), ++ RK3328_MACPHY_DISENABLE = 0, ++ RK3328_MACPHY_ENABLE = BIT(0), ++ }; ++ enum { ++ RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), ++ RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, ++ }; ++ enum { ++ RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), ++ RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, ++ }; ++ ++ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ rk_clrsetreg(&grf->macphy_con[1], ++ RK3328_GRF_CON_RMII_MODE_MASK, ++ RK3328_GRF_CON_RMII_MODE); ++ ++ rk_clrsetreg(&grf->macphy_con[2], ++ RK3328_RK_GRF_CON2_MACPHY_ID_MASK, ++ RK3328_RK_GRF_CON2_MACPHY_ID); ++ ++ rk_clrsetreg(&grf->macphy_con[3], ++ RK3328_RK_GRF_CON3_MACPHY_ID_MASK, ++ RK3328_RK_GRF_CON3_MACPHY_ID); ++ ++ /* disabled before trying to reset it */ ++ rk_clrsetreg(&grf->macphy_con[0], ++ RK3328_MACPHY_CFG_CLK_50M_MASK | ++ RK3328_MACPHY_RMII_MODE_MASK | ++ RK3328_MACPHY_ENABLE_MASK, ++ RK3328_MACPHY_CFG_CLK_50M | ++ RK3328_MACPHY_RMII_MODE | ++ RK3328_MACPHY_DISENABLE); ++ ++ reset_assert(&pdata->phy_reset); ++ udelay(10); ++ reset_deassert(&pdata->phy_reset); ++ udelay(10); ++ ++ rk_clrsetreg(&grf->macphy_con[0], ++ RK3328_MACPHY_ENABLE_MASK, ++ RK3328_MACPHY_ENABLE); ++ udelay(30 * 1000); ++} ++ + static int gmac_rockchip_probe(struct udevice *dev) + { + struct gmac_rockchip_plat *pdata = dev_get_plat(dev); +@@ -569,6 +837,9 @@ static int gmac_rockchip_probe(struct udevice *dev) + if (ret) + return ret; + ++ if (pdata->integrated_phy && ops->integrated_phy_powerup) ++ ops->integrated_phy_powerup(pdata); ++ + switch (eth_pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + /* Set to RGMII mode */ +@@ -652,7 +923,7 @@ static int gmac_rockchip_probe(struct udevice *dev) + break; + + default: +- debug("NO interface defined!\n"); ++ debug("%s: no interface defined!\n", __func__); + return -ENXIO; + } + +@@ -661,18 +932,33 @@ static int gmac_rockchip_probe(struct udevice *dev) + + static int gmac_rockchip_eth_start(struct udevice *dev) + { +- struct eth_pdata *pdata = dev_get_plat(dev); ++ struct eth_pdata *eth_pdata = dev_get_plat(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + struct rk_gmac_ops *ops = + (struct rk_gmac_ops *)dev_get_driver_data(dev); ++ struct gmac_rockchip_plat *pdata = dev_get_plat(dev); + int ret; + +- ret = designware_eth_init(priv, pdata->enetaddr); +- if (ret) +- return ret; +- ret = ops->fix_mac_speed(priv); ++ ret = designware_eth_init(priv, eth_pdata->enetaddr); + if (ret) + return ret; ++ ++ switch (eth_pdata->phy_interface) { ++ case PHY_INTERFACE_MODE_RGMII: ++ ret = ops->fix_rgmii_speed(pdata, priv); ++ if (ret) ++ return ret; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ ret = ops->fix_rmii_speed(pdata, priv); ++ if (ret) ++ return ret; ++ break; ++ default: ++ debug("%s: no interface defined!\n", __func__); ++ return -ENXIO; ++ } ++ + ret = designware_eth_enable(priv); + if (ret) + return ret; +@@ -690,42 +976,48 @@ const struct eth_ops gmac_rockchip_eth_ops = { + }; + + const struct rk_gmac_ops px30_gmac_ops = { +- .fix_mac_speed = px30_gmac_fix_mac_speed, ++ .fix_rmii_speed = px30_gmac_fix_rmii_speed, + .set_to_rmii = px30_gmac_set_to_rmii, + }; + + const struct rk_gmac_ops rk3228_gmac_ops = { +- .fix_mac_speed = rk3228_gmac_fix_mac_speed, ++ .fix_rmii_speed = rk3228_gmac_fix_rmii_speed, ++ .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, ++ .set_to_rmii = rk3228_gmac_set_to_rmii, + .set_to_rgmii = rk3228_gmac_set_to_rgmii, ++ .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, + }; + + const struct rk_gmac_ops rk3288_gmac_ops = { +- .fix_mac_speed = rk3288_gmac_fix_mac_speed, ++ .fix_rgmii_speed = rk3288_gmac_fix_rgmii_speed, + .set_to_rgmii = rk3288_gmac_set_to_rgmii, + }; + + const struct rk_gmac_ops rk3308_gmac_ops = { +- .fix_mac_speed = rk3308_gmac_fix_mac_speed, ++ .fix_rmii_speed = rk3308_gmac_fix_rmii_speed, + .set_to_rmii = rk3308_gmac_set_to_rmii, + }; + + const struct rk_gmac_ops rk3328_gmac_ops = { +- .fix_mac_speed = rk3328_gmac_fix_mac_speed, ++ .fix_rmii_speed = rk3328_gmac_fix_rmii_speed, ++ .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, ++ .set_to_rmii = rk3328_gmac_set_to_rmii, + .set_to_rgmii = rk3328_gmac_set_to_rgmii, ++ .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, + }; + + const struct rk_gmac_ops rk3368_gmac_ops = { +- .fix_mac_speed = rk3368_gmac_fix_mac_speed, ++ .fix_rgmii_speed = rk3368_gmac_fix_rgmii_speed, + .set_to_rgmii = rk3368_gmac_set_to_rgmii, + }; + + const struct rk_gmac_ops rk3399_gmac_ops = { +- .fix_mac_speed = rk3399_gmac_fix_mac_speed, ++ .fix_rgmii_speed = rk3399_gmac_fix_rgmii_speed, + .set_to_rgmii = rk3399_gmac_set_to_rgmii, + }; + + const struct rk_gmac_ops rv1108_gmac_ops = { +- .fix_mac_speed = rv1108_set_rmii_speed, ++ .fix_rmii_speed = rv1108_gmac_fix_rmii_speed, + .set_to_rmii = rv1108_gmac_set_to_rmii, + }; + +diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c +index ae9fe9da..92514af1 100644 +--- a/drivers/net/gmac_rockchip.c ++++ b/drivers/net/gmac_rockchip.c +@@ -891,7 +891,7 @@ static int gmac_rockchip_probe(struct udevice *dev) + + if (!pdata->clock_input) { + rate = clk_set_rate(&clk, 50000000); +- if (rate != 50000000) ++ if (rate != 50000000 && rate != 49500000) + return -EINVAL; + } + break; diff --git a/patch/u-boot/u-boot-media/020-rk3328-efuse-driver.patch b/patch/u-boot/u-boot-media/0170-rk3328-efuse-driver.patch similarity index 100% rename from patch/u-boot/u-boot-media/020-rk3328-efuse-driver.patch rename to patch/u-boot/u-boot-media/0170-rk3328-efuse-driver.patch diff --git a/patch/u-boot/u-boot-media/180-rk3399-always-init-rkclk.patch b/patch/u-boot/u-boot-media/0180-rk3399-always-init-rkclk.patch similarity index 100% rename from patch/u-boot/u-boot-media/180-rk3399-always-init-rkclk.patch rename to patch/u-boot/u-boot-media/0180-rk3399-always-init-rkclk.patch diff --git a/patch/u-boot/u-boot-media/190-rk3399-enable-stable-mac.patch b/patch/u-boot/u-boot-media/0190-rk3399-enable-stable-mac.patch similarity index 100% rename from patch/u-boot/u-boot-media/190-rk3399-enable-stable-mac.patch rename to patch/u-boot/u-boot-media/0190-rk3399-enable-stable-mac.patch diff --git a/patch/u-boot/u-boot-media/200-rk3399-populate-child-node-of-syscon.patch b/patch/u-boot/u-boot-media/0200-rk3399-populate-child-node-of-syscon.patch similarity index 100% rename from patch/u-boot/u-boot-media/200-rk3399-populate-child-node-of-syscon.patch rename to patch/u-boot/u-boot-media/0200-rk3399-populate-child-node-of-syscon.patch diff --git a/patch/u-boot/u-boot-media/210-sdmmc-force-fifo-mode-in-spl.patch b/patch/u-boot/u-boot-media/0210-sdmmc-force-fifo-mode-in-spl.patch similarity index 100% rename from patch/u-boot/u-boot-media/210-sdmmc-force-fifo-mode-in-spl.patch rename to patch/u-boot/u-boot-media/0210-sdmmc-force-fifo-mode-in-spl.patch diff --git a/patch/u-boot/u-boot-media/040-u-boot-0010-rk-usb-start.patch b/patch/u-boot/u-boot-media/0220-u-boot-0010-rk-usb-start.patch similarity index 100% rename from patch/u-boot/u-boot-media/040-u-boot-0010-rk-usb-start.patch rename to patch/u-boot/u-boot-media/0220-u-boot-0010-rk-usb-start.patch diff --git a/patch/u-boot/u-boot-media/220-u-boot-rk3399-roc-pc-plus.patch b/patch/u-boot/u-boot-media/0230-u-boot-rk3399-roc-pc-plus.patch similarity index 100% rename from patch/u-boot/u-boot-media/220-u-boot-rk3399-roc-pc-plus.patch rename to patch/u-boot/u-boot-media/0230-u-boot-rk3399-roc-pc-plus.patch diff --git a/patch/u-boot/u-boot-media/060-u-boot-rk3399-roc-pc-plus-dts.patch b/patch/u-boot/u-boot-media/0240-u-boot-rk3399-roc-pc-plus-dts.patch similarity index 100% rename from patch/u-boot/u-boot-media/060-u-boot-rk3399-roc-pc-plus-dts.patch rename to patch/u-boot/u-boot-media/0240-u-boot-rk3399-roc-pc-plus-dts.patch diff --git a/patch/u-boot/u-boot-media/070-u-boot-rk-rk3328-dtsi.patch b/patch/u-boot/u-boot-media/0250-u-boot-rk-rk3328-dtsi.patch similarity index 100% rename from patch/u-boot/u-boot-media/070-u-boot-rk-rk3328-dtsi.patch rename to patch/u-boot/u-boot-media/0250-u-boot-rk-rk3328-dtsi.patch diff --git a/patch/u-boot/u-boot-media/080-u-boot-rk-rk3328-roc-cc-dts.patch b/patch/u-boot/u-boot-media/0260-u-boot-rk-rk3328-roc-cc-dts.patch similarity index 100% rename from patch/u-boot/u-boot-media/080-u-boot-rk-rk3328-roc-cc-dts.patch rename to patch/u-boot/u-boot-media/0260-u-boot-rk-rk3328-roc-cc-dts.patch diff --git a/patch/u-boot/u-boot-media/090-u-boot-rk-rk3328-roc-pc-config.patch b/patch/u-boot/u-boot-media/0270-u-boot-rk-rk3328-roc-pc-config.patch similarity index 100% rename from patch/u-boot/u-boot-media/090-u-boot-rk-rk3328-roc-pc-config.patch rename to patch/u-boot/u-boot-media/0270-u-boot-rk-rk3328-roc-pc-config.patch diff --git a/patch/u-boot/u-boot-media/100-u-boot-rk-rk3328-roc-pc-dts.patch b/patch/u-boot/u-boot-media/0280-u-boot-rk-rk3328-roc-pc-dts.patch similarity index 100% rename from patch/u-boot/u-boot-media/100-u-boot-rk-rk3328-roc-pc-dts.patch rename to patch/u-boot/u-boot-media/0280-u-boot-rk-rk3328-roc-pc-dts.patch diff --git a/patch/u-boot/u-boot-media/110-u-boot-rk-rk3328-roc-pc-include.patch b/patch/u-boot/u-boot-media/0290-u-boot-rk-rk3328-roc-pc-include.patch similarity index 100% rename from patch/u-boot/u-boot-media/110-u-boot-rk-rk3328-roc-pc-include.patch rename to patch/u-boot/u-boot-media/0290-u-boot-rk-rk3328-roc-pc-include.patch diff --git a/patch/u-boot/u-boot-media/120-u-boot-rk-rk3328-roc-pc-make-dts.patch b/patch/u-boot/u-boot-media/0300-u-boot-rk-rk3328-roc-pc-make-dts.patch similarity index 100% rename from patch/u-boot/u-boot-media/120-u-boot-rk-rk3328-roc-pc-make-dts.patch rename to patch/u-boot/u-boot-media/0300-u-boot-rk-rk3328-roc-pc-make-dts.patch diff --git a/patch/u-boot/u-boot-media/050-u-boot-rk3399-roc-pc-plus.patch b/patch/u-boot/u-boot-media/0310-u-boot-rk-rk3399-opi800-config.patch similarity index 76% rename from patch/u-boot/u-boot-media/050-u-boot-rk3399-roc-pc-plus.patch rename to patch/u-boot/u-boot-media/0310-u-boot-rk-rk3399-opi800-config.patch index d290940a5..fe2d4ec91 100644 --- a/patch/u-boot/u-boot-media/050-u-boot-rk3399-roc-pc-plus.patch +++ b/patch/u-boot/u-boot-media/0310-u-boot-rk-rk3399-opi800-config.patch @@ -1,57 +1,50 @@ new file mode 100644 -index 00000000..cf3462ea +index 00000000..18ec369f --- /dev/null -+++ b/configs/roc-pc-plus-rk3399_defconfig -@@ -0,0 +1,90 @@ ++++ b/configs/orangepi-800-rk3399_defconfig +@@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ENV_SECT_SIZE=0x1000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-plus" ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi-800" +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_ROC_PC_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI=y -+CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x800800 +# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-plus.dtb" ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi-800.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000 -+CONFIG_SPL_ENV_SUPPORT=y -+CONFIG_SPL_SPI_LOAD=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y ++CONFIG_CMD_REGULATOR=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_SPI_FLASH=y ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y ++CONFIG_ROCKCHIP_EFUSE=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_SF_DEFAULT_BUS=1 -+CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y @@ -63,12 +56,10 @@ index 00000000..cf3462ea +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y -+# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_RAM_RK3399_LPDDR4=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y diff --git a/patch/u-boot/u-boot-media/0320-u-boot-rk-rk3399-opi800-dts.patch b/patch/u-boot/u-boot-media/0320-u-boot-rk-rk3399-opi800-dts.patch new file mode 100644 index 000000000..f44d8a774 --- /dev/null +++ b/patch/u-boot/u-boot-media/0320-u-boot-rk-rk3399-opi800-dts.patch @@ -0,0 +1,983 @@ +new file mode 100644 +index 00000000..65e9c44b +--- /dev/null ++++ b/arch/arm/dts/rk3399-orangepi-800.dts +@@ -0,0 +1,977 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 Akash Gajjar ++ * Copyright (c) 2019 Pragnesh Patel ++ * Copyright (c) 2022 Furkan Kardame ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "Orange Pi 800 Keyboard"; ++ compatible = "rockchip,rk3399-orangepi-800", "rockchip,rk3399"; ++ ++ aliases { ++ mmc0 = &sdio0; ++ mmc1 = &sdmmc; ++ mmc2 = &sdhci; ++ }; ++ ++ cpuinfo { ++ compatible = "rockchip,cpuinfo"; ++ nvmem-cells = <&cpu_id>; ++ nvmem-cell-names = "id"; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ aliases { ++ spi2 = &spi2; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_reg_on_h>; ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ usb_vbus: usb-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_vbus"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ usb3_vbus: usb3-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb3_vbus"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v0_sd: vcc3v0-sd { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_pwr_h>; ++ regulator-name = "vcc3v0_sd"; ++ regulator-always-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_sys>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc_sys>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_sys: vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ regulator-name = "vdd_log"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pwr_en>; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ /* Audio components */ ++ es8316-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "rockchip,es8316-codec"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ simple-audio-card,routing = ++ "MIC1", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s0>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&es8316>; ++ }; ++ }; ++ ++ hdmi_sound: hdmi-sound { ++ status = "okay"; ++ }; ++ ++ hdmi_dp_sound: hdmi-dp-sound { ++ status = "okay"; ++ compatible = "rockchip,rk3399-hdmi-dp"; ++ rockchip,cpu = <&i2s2>; ++ rockchip,codec = <&hdmi>, <&cdn_dp>; ++ }; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ poll-interval = <100>; ++ keyup-threshold-microvolt = <1800000>; ++ ++ button-up { ++ label = "Volume Up"; ++ linux,code = ; ++ press-threshold-microvolt = <100000>; ++ }; ++ ++ button-down { ++ label = "Volume Down"; ++ linux,code = ; ++ press-threshold-microvolt = <300000>; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ autorepeat; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&power_key>; ++ ++ button@0 { ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ label = "GPIO Key Power"; ++ linux,input-type = <1>; ++ gpio-key,wakeup = <1>; ++ debounce-interval = <100>; ++ }; ++ }; ++ ++ leds: gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 =<&leds_gpio>; ++ ++ power { ++ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ label = "power_led"; ++ linux,default-trigger = "none"; ++ linux,default-trigger-delay-ms = <0>; ++ default-state = "on"; ++ }; ++ ++ num { ++ gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; ++ label = "num_led"; ++ linux,default-trigger = "kbd-numlock"; ++ linux,default-trigger-delay-ms = <0>; ++ default-state = "off"; ++ }; ++ ++ caps { ++ gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; ++ label = "caps_led"; ++ linux,default-trigger = "kbd-capslock"; ++ linux,default-trigger-delay-ms = <0>; ++ default-state = "off"; ++ }; ++ }; ++ ++ sprd-wlan { ++ compatible = "sprd,uwe5622-wifi"; ++ status = "okay"; ++ }; ++ ++ unisoc_uwe_bsp: uwe-bsp { ++ compatible = "unisoc,uwe_bsp"; ++ wl-reg-on = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; ++ bt-reg-on = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ wl-wake-host-gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; ++ bt-wake-host-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ sdio-ext-int-gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; ++ unisoc,btwf-file-name = "/lib/firmware/wcnmodem.bin"; ++ //adma-tx; ++ //adma-rx; ++ data-irq; ++ blksz-512; ++ keep-power-on; ++ status = "okay"; ++ }; ++ ++ sprd-mtty { ++ compatible = "sprd,mtty"; ++ sprd,name = "ttyBT"; ++ status = "okay"; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc3v3_s3>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x24>; ++ rx_delay = <0x18>; ++ status = "okay"; ++}; ++ ++&gpu { ++ status = "okay"; ++ mali-supply = <&vdd_gpu>; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c7>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ #clock-cells = <1>; ++ clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ vcc10-supply = <&vcc3v3_sys>; ++ vcc11-supply = <&vcc3v3_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vcc13-supply = <&vcc3v3_sys>; ++ vcc14-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc1v8_pmu>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <700000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v0_tp: LDO_REG2 { ++ regulator-name = "vcc3v0_tp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu: LDO_REG3 { ++ regulator-name = "vcc1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sdio: LDO_REG4 { ++ regulator-name = "vcc_sdio"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-name = "vcca3v0_codec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-name = "vcca1v8_codec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cpu_b_sleep>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpu_sleep>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ ++ es8316: codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ clock-names = "mclk"; ++ //pinctrl-names = "default"; ++ //pinctrl-0 = <&i2s_8ch_mclk>; ++ hp-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; ++ spk-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; ++ #sound-dai-cells = <0>; ++ }; ++ ++ rtc@32 { ++ compatible = "ricoh,rs5c372a"; ++ reg = <0x32>; ++ }; ++}; ++ ++&i2c2 { ++ status = "disabled"; ++}; ++ ++&i2c3 { ++ status = "disabled"; ++}; ++ ++&i2c4 { ++ status = "disabled"; ++}; ++ ++&spdif { ++ status = "disabled"; ++}; ++ ++&i2c7 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2s0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_2ch_bus>; ++// assigned-clocks = <&cru SCLK_I2SOUT_SRC>; ++ assigned-clock-parents = <&cru SCLK_I2S0_8CH>; ++ rockchip,capture-channels = <2>; ++ rockchip,playback-channels = <2>; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&i2s1 { ++// assigned-clocks = <&cru SCLK_I2SOUT_SRC>; ++ assigned-clock-parents = <&cru SCLK_I2S1_8CH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1_2ch_bus>; ++ rockchip,playback-channels = <2>; ++ rockchip,capture-channels = <2>; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&i2s2 { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ ++ audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ ++ sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ ++ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ pmu1830-supply = <&vcc1v8_pmu>; ++}; ++ ++&pinctrl { ++ gmac { ++ phy_intb: phy-intb { ++ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ phy_rstb: phy-rstb { ++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie { ++ pcie_pwr_en: pcie-pwr-en { ++ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ cpu_b_sleep: cpu-b-sleep { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ gpu_sleep: gpu-sleep { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sd { ++ sdmmc0_pwr_h: sdmmc0-pwr-h { ++ rockchip,pins = ++ <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = ++ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_typec_en: vcc5v0-typec-en { ++ rockchip,pins = ++ <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdio-pwrseq { ++ wifi_reg_on_h: wifi-reg-on-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ bluetooth { ++ bt_reg_on_h: bt-enable-h { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb302 { ++ chg_cc_int_l: chg-cc-int-l { ++ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-leds { ++ leds_gpio: leds-gpio { ++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, ++ <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, ++ <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ rockchip-key { ++ power_key: power-key { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ spi2 { ++ spi2_gpio: spi2-gpio { ++ rockchip,pins = ++ <2 RK_PA1 RK_FUNC_GPIO &pcfg_output_low>, ++ <2 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>, ++ <2 RK_PA3 RK_FUNC_GPIO &pcfg_output_low>, ++ <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm1 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vcc_1v8>; /* TBD */ ++}; ++ ++&sdhci { ++ assigned-clock-rates = <150000000>; ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ supports-emmc; ++ non-removable; ++ keep-power-in-suspend; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&sdio0 { ++ clock-frequency = <150000000>; ++ clock-freq-min-max = <200000 50000000>; ++ supports-sdio; ++ bus-width = <4>; ++ disable-wp; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ num-slots = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v0_sd>; ++ vqmmc-supply = <&vcc_sdio>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&usb3_vbus>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&usb_vbus>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ status = "okay"; ++ ++// bluetooth { ++// compatible = "brcm,bcm4345c5"; ++// clocks = <&rk808 1>; ++// clock-names = "lpo"; ++// device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; ++// host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++// shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++// max-speed = <1500000>; ++// pinctrl-names = "default"; ++// pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; ++// }; ++ ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; ++ ++&spi2 { ++ status = "okay"; ++ pinctrl-names = "default", "sleep"; ++ pinctrl-1 = <&spi2_gpio>; ++ ++ spidev0: spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ status = "okay"; ++ }; ++}; ++ ++//&edp { ++// status = "okay"; ++// hpd-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; ++// enable-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; ++//}; ++ ++//&edp_hpd { ++// rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++//}; ++ ++//&edp_in_vopb { ++// status = "disabled"; ++//}; ++ ++//&hdmi_in_vopb { ++// status = "okay"; ++//}; + diff --git a/patch/u-boot/u-boot-media/0330-u-boot-rk-rk3399-opi800-makefile.patch b/patch/u-boot/u-boot-media/0330-u-boot-rk-rk3399-opi800-makefile.patch new file mode 100644 index 000000000..519ebda12 --- /dev/null +++ b/patch/u-boot/u-boot-media/0330-u-boot-rk-rk3399-opi800-makefile.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -155,6 +155,7 @@ + rk3399-nanopi-r4s.dtb \ + rk3399-orangepi.dtb \ + rk3399-orangepi-4.dtb \ ++ rk3399-orangepi-800.dtb \ + rk3399-pinebook-pro.dtb \ + rk3399-puma-haikou.dtb \ + rk3399-roc-pc.dtb \ + diff --git a/patch/u-boot/u-boot-media/0340-u-boot-rk-rk3399-opi800-uboot-dtsi.patch b/patch/u-boot/u-boot-media/0340-u-boot-rk-rk3399-opi800-uboot-dtsi.patch new file mode 100644 index 000000000..1e3610c62 --- /dev/null +++ b/patch/u-boot/u-boot-media/0340-u-boot-rk-rk3399-opi800-uboot-dtsi.patch @@ -0,0 +1,18 @@ +new file mode 100644 +index 00000000..5bd86966 +--- /dev/null ++++ b/arch/arm/dts/rk3399-orangepi-800-u-boot.dtsi +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019 Jagan Teki ++ */ ++ ++#include "rk3399-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; ++ }; ++}; diff --git a/patch/u-boot/u-boot-media/130-u-boot-rk-rk3399-usb-start.patch b/patch/u-boot/u-boot-media/0350-u-boot-rk-rk3399-usb-start.patch similarity index 87% rename from patch/u-boot/u-boot-media/130-u-boot-rk-rk3399-usb-start.patch rename to patch/u-boot/u-boot-media/0350-u-boot-rk-rk3399-usb-start.patch index d84088aec..c3e421270 100644 --- a/patch/u-boot/u-boot-media/130-u-boot-rk-rk3399-usb-start.patch +++ b/patch/u-boot/u-boot-media/0350-u-boot-rk-rk3399-usb-start.patch @@ -1,13 +1,12 @@ --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h -@@ -61,10 +61,10 @@ +@@ -55,9 +55,9 @@ #ifdef CONFIG_ROCKCHIP_RK3399 #define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_USB(func) \ BOOT_TARGET_MMC(func) \ BOOT_TARGET_NVME(func) \ - BOOT_TARGET_SCSI(func) \ - BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) \ diff --git a/patch/u-boot/u-boot-media/140-u-boot-rk-rk3399-usb-start-firefly-rk3399.patch b/patch/u-boot/u-boot-media/0360-u-boot-rk-rk3399-usb-start-firefly-rk3399.patch similarity index 100% rename from patch/u-boot/u-boot-media/140-u-boot-rk-rk3399-usb-start-firefly-rk3399.patch rename to patch/u-boot/u-boot-media/0360-u-boot-rk-rk3399-usb-start-firefly-rk3399.patch diff --git a/patch/u-boot/u-boot-media/150-u-boot-rk-rk3399-usb-start-nanopc-t4.patch b/patch/u-boot/u-boot-media/0370-u-boot-rk-rk3399-usb-start-nanopc-t4.patch similarity index 100% rename from patch/u-boot/u-boot-media/150-u-boot-rk-rk3399-usb-start-nanopc-t4.patch rename to patch/u-boot/u-boot-media/0370-u-boot-rk-rk3399-usb-start-nanopc-t4.patch diff --git a/patch/u-boot/u-boot-media/230-u-boot-rk3399-roc-pc-plus-dts.patch b/patch/u-boot/u-boot-media/230-u-boot-rk3399-roc-pc-plus-dts.patch deleted file mode 100644 index 2166cd083..000000000 --- a/patch/u-boot/u-boot-media/230-u-boot-rk3399-roc-pc-plus-dts.patch +++ /dev/null @@ -1,111 +0,0 @@ -new file mode 100644 -index 00000000..02a8f9f5 ---- /dev/null -+++ b/arch/arm/dts/rk3399-roc-pc-plus.dts -@@ -0,0 +1,92 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd -+ */ -+ -+/dts-v1/; -+#include "rk3399-roc-pc.dtsi" -+ -+/ { -+ model = "Firefly ROC-RK3399-PC-PLUS Board"; -+ compatible = "firefly,roc-rk3399-pc-plus", "rockchip,rk3399"; -+ -+ vcc3v3_ngff: vcc3v3-ngff { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_ngff"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc3v3_ngff_en>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ vcc3v3_pcie: vcc3v3-pcie { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc3v3_pcie_en>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&dc_12v>; -+ }; -+}; -+ -+&pcie_phy { -+ status = "okay"; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; -+ num-lanes = <4>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_perst>; -+ vpcie3v3-supply = <&vcc3v3_pcie>; -+ vpcie1v8-supply = <&vcc1v8_pmu>; -+ vpcie0v9-supply = <&vcca_0v9>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ ngff { -+ vcc3v3_ngff_en: vcc3v3-ngff-en { -+ rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ vcc3v3_pcie_en: vcc3v3-pcie-en { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_perst: pcie-perst { -+ rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_ngff>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -+ status = "okay"; -+}; - - -new file mode 100644 -index 00000000..02a8f9f5 ---- /dev/null -+++ b/arch/arm/dts/rk3399-roc-pc-plus-u-boot.dtsi -@@ -0,0 +1,6 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+#include "rk3399-roc-pc-u-boot.dtsi" - diff --git a/patch/u-boot/u-boot-media/board_nanopi-r4s/0001-rockchip-rk3399-Add-Nanopi-R4S-board-support.patch b/patch/u-boot/u-boot-media/board_nanopi-r4s/0001-rockchip-rk3399-Add-Nanopi-R4S-board-support.patch new file mode 100644 index 000000000..5edb89111 --- /dev/null +++ b/patch/u-boot/u-boot-media/board_nanopi-r4s/0001-rockchip-rk3399-Add-Nanopi-R4S-board-support.patch @@ -0,0 +1,452 @@ +From a86eb090b22ce1b83493e6ac833265955063da97 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Tue, 15 Dec 2020 18:02:38 +0800 +Subject: [PATCH 1/4] rockchip: rk3399: Add Nanopi R4S board support + +Add initial support for Nanopi R4S board. + +Specification +- Rockchip RK3399 +- LPDDR4 4GiB, 1GB DDR3-1866 +- SD card slot +- RTL8211E 1Gbps +- RTL8111H 1Gbps +- USB 3.0 x2 +- USB Type C power + +Signed-off-by: hmz007 +--- + arch/arm/dts/Makefile | 1 + + .../arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi | 8 ++ + arch/arm/dts/rk3399-nanopi-r4s-4gb.dts | 114 ++++++++++++++++++ + arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 7 ++ + arch/arm/dts/rk3399-nanopi-r4s.dts | 114 ++++++++++++++++++ + configs/nanopi-r4s-4gb-rk3399_defconfig | 63 ++++++++++ + configs/nanopi-r4s-rk3399_defconfig | 62 ++++++++++ + 7 files changed, 370 insertions(+) + create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-4gb.dts + create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts + create mode 100644 configs/nanopi-r4s-4gb-rk3399_defconfig + create mode 100644 configs/nanopi-r4s-rk3399_defconfig + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index f8f529435b..55ca25bb22 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -131,6 +131,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ + rk3399-nanopi-m4.dtb \ + rk3399-nanopi-m4-2gb.dtb \ + rk3399-nanopi-neo4.dtb \ ++ rk3399-nanopi-r4s.dtb \ + rk3399-orangepi.dtb \ + rk3399-pinebook-pro.dtb \ + rk3399-puma-haikou.dtb \ +diff --git a/arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi +new file mode 100644 +index 0000000000..b291830640 +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019 Jagan Teki ++ * Copyright (C) 2020 Deepak Das ++ */ ++ ++#include "rk3399-nanopi4-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" +diff --git a/arch/arm/dts/rk3399-nanopi-r4s-4gb.dts b/arch/arm/dts/rk3399-nanopi-r4s-4gb.dts +new file mode 100644 +index 0000000000..3072880c77 +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-r4s-4gb.dts +@@ -0,0 +1,114 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * FriendlyElec NanoPi R4S board device tree source ++ * ++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2018 Collabora Ltd. ++ * Copyright (c) 2019 Arm Ltd. ++ */ ++ ++/dts-v1/; ++#include "rk3399-nanopi4.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R4S"; ++ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc5v0_usb1: vcc5v0-usb1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb1"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vdd_5v>; ++ }; ++ ++ vcc5v0_usb2: vcc5v0-usb2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb2"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vdd_5v>; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* ++ * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels ++ * work out to 0, ~1200, ~3000, and 5000RPM respectively. ++ */ ++ cooling-levels = <0 12 18 255>; ++ #cooling-cells = <2>; ++ fan-supply = <&vdd_5v>; ++ pwms = <&pwm1 0 50000 0>; ++ }; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_warm: cpu_warm { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu_hot { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map2 { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map3 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&emmc_phy { ++ status = "disabled"; ++}; ++ ++&fusb0 { ++ status = "disabled"; ++}; ++ ++&pcie0 { ++ num-lanes = <1>; ++ vpcie3v3-supply = <&vcc3v3_sys>; ++}; ++ ++&sdhci { ++ status = "disabled"; ++}; ++ ++&sdio0 { ++ status = "disabled"; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vdd_5v>; ++}; ++ ++&u2phy1_host { ++ status = "disabled"; ++}; ++ ++&vcc3v3_sys { ++ vin-supply = <&vcc5v0_sys>; ++}; +diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi +new file mode 100644 +index 0000000000..eb0aca4758 +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2019 Jagan Teki ++ */ ++ ++#include "rk3399-nanopi4-u-boot.dtsi" ++#include "rk3399-sdram-ddr3-1866.dtsi" +diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts +new file mode 100644 +index 0000000000..3072880c77 +--- /dev/null ++++ b/arch/arm/dts/rk3399-nanopi-r4s.dts +@@ -0,0 +1,114 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * FriendlyElec NanoPi R4S board device tree source ++ * ++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * Copyright (c) 2018 Collabora Ltd. ++ * Copyright (c) 2019 Arm Ltd. ++ */ ++ ++/dts-v1/; ++#include "rk3399-nanopi4.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R4S"; ++ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc5v0_usb1: vcc5v0-usb1 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb1"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vdd_5v>; ++ }; ++ ++ vcc5v0_usb2: vcc5v0-usb2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb2"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vdd_5v>; ++ }; ++ ++ fan: pwm-fan { ++ compatible = "pwm-fan"; ++ /* ++ * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels ++ * work out to 0, ~1200, ~3000, and 5000RPM respectively. ++ */ ++ cooling-levels = <0 12 18 255>; ++ #cooling-cells = <2>; ++ fan-supply = <&vdd_5v>; ++ pwms = <&pwm1 0 50000 0>; ++ }; ++}; ++ ++&cpu_thermal { ++ trips { ++ cpu_warm: cpu_warm { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu_hot { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map2 { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map3 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ ++&emmc_phy { ++ status = "disabled"; ++}; ++ ++&fusb0 { ++ status = "disabled"; ++}; ++ ++&pcie0 { ++ num-lanes = <1>; ++ vpcie3v3-supply = <&vcc3v3_sys>; ++}; ++ ++&sdhci { ++ status = "disabled"; ++}; ++ ++&sdio0 { ++ status = "disabled"; ++}; ++ ++&u2phy0_host { ++ phy-supply = <&vdd_5v>; ++}; ++ ++&u2phy1_host { ++ status = "disabled"; ++}; ++ ++&vcc3v3_sys { ++ vin-supply = <&vcc5v0_sys>; ++}; +diff --git a/configs/nanopi-r4s-4gb-rk3399_defconfig b/configs/nanopi-r4s-4gb-rk3399_defconfig +new file mode 100644 +index 0000000000..dcac8d426f +--- /dev/null ++++ b/configs/nanopi-r4s-4gb-rk3399_defconfig +@@ -0,0 +1,63 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_EVB_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s-4gb" ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s-4gb.dtb" ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y +diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig +new file mode 100644 +index 0000000000..034241f209 +--- /dev/null ++++ b/configs/nanopi-r4s-rk3399_defconfig +@@ -0,0 +1,62 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SYS_TEXT_BASE=0x00200000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_EVB_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=1 ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_SPL_TINY_MEMSET=y ++CONFIG_ERRNO_STR=y +-- +2.25.1 + diff --git a/patch/u-boot/u-boot-media/board_nanopi-r4s/0002-rockchip-rk3399-split-nanopi-r4s-out-of-evb_rk3399.patch b/patch/u-boot/u-boot-media/board_nanopi-r4s/0002-rockchip-rk3399-split-nanopi-r4s-out-of-evb_rk3399.patch new file mode 100644 index 000000000..ea49fdbdf --- /dev/null +++ b/patch/u-boot/u-boot-media/board_nanopi-r4s/0002-rockchip-rk3399-split-nanopi-r4s-out-of-evb_rk3399.patch @@ -0,0 +1,656 @@ +From 244492a7a5451eca042d3ec7ccff8de6e23dd288 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Fri, 18 Dec 2020 17:10:35 +0800 +Subject: [PATCH 2/4] rockchip: rk3399: split nanopi-r4s out of evb_rk3399 + +Signed-off-by: hmz007 +--- + arch/arm/mach-rockchip/rk3399/Kconfig | 6 + + board/friendlyarm/nanopi4/Kconfig | 15 +++ + board/friendlyarm/nanopi4/MAINTAINERS | 6 + + board/friendlyarm/nanopi4/Makefile | 8 ++ + board/friendlyarm/nanopi4/README | 122 +++++++++++++++++++ + board/friendlyarm/nanopi4/hwrev.c | 149 ++++++++++++++++++++++++ + board/friendlyarm/nanopi4/hwrev.h | 27 +++++ + board/friendlyarm/nanopi4/nanopi4.c | 148 +++++++++++++++++++++++ + configs/nanopi-r4s-4gb-rk3399_defconfig | 4 +- + configs/nanopi-r4s-rk3399_defconfig | 4 +- + drivers/clk/rockchip/clk_rk3399.c | 2 + + include/configs/nanopi4.h | 24 ++++ + 12 files changed, 511 insertions(+), 4 deletions(-) + create mode 100644 board/friendlyarm/nanopi4/Kconfig + create mode 100644 board/friendlyarm/nanopi4/MAINTAINERS + create mode 100644 board/friendlyarm/nanopi4/Makefile + create mode 100644 board/friendlyarm/nanopi4/README + create mode 100644 board/friendlyarm/nanopi4/hwrev.c + create mode 100644 board/friendlyarm/nanopi4/hwrev.h + create mode 100644 board/friendlyarm/nanopi4/nanopi4.c + create mode 100644 include/configs/nanopi4.h + +diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig +index 17628f9171..2a44aae43c 100644 +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -109,6 +109,11 @@ config TARGET_ROC_PC_RK3399 + * wide voltage input(5V-15V), dual cell battery + * Wifi/BT accessible via expansion board M.2 + ++config TARGET_NANOPI4 ++ bool "FriendlyElec NanoPi 4 Series" ++ help ++ Support for FriendlyElec boards based on RK3399. ++ + endchoice + + config ROCKCHIP_BOOT_MODE_REG +@@ -152,6 +157,7 @@ config SYS_BOOTCOUNT_ADDR + endif # BOOTCOUNT_LIMIT + + source "board/firefly/roc-pc-rk3399/Kconfig" ++source "board/friendlyarm/nanopi4/Kconfig" + source "board/google/gru/Kconfig" + source "board/pine64/pinebook-pro-rk3399/Kconfig" + source "board/pine64/rockpro64_rk3399/Kconfig" +diff --git a/board/friendlyarm/nanopi4/Kconfig b/board/friendlyarm/nanopi4/Kconfig +new file mode 100644 +index 0000000000..f3f9dd7b56 +--- /dev/null ++++ b/board/friendlyarm/nanopi4/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_NANOPI4 ++ ++config SYS_BOARD ++ default "nanopi4" ++ ++config SYS_VENDOR ++ default "friendlyarm" ++ ++config SYS_CONFIG_NAME ++ default "nanopi4" ++ ++config BOARD_SPECIFIC_OPTIONS ++ def_bool y ++ ++endif +diff --git a/board/friendlyarm/nanopi4/MAINTAINERS b/board/friendlyarm/nanopi4/MAINTAINERS +new file mode 100644 +index 0000000000..b4c35701d6 +--- /dev/null ++++ b/board/friendlyarm/nanopi4/MAINTAINERS +@@ -0,0 +1,6 @@ ++NanoPi 4 Series ++M: ++S: Maintained ++F: board/friendlyarm/nanopi4/ ++F: include/configs/nanopi4.h ++F: configs/nanopi4_defconfig +diff --git a/board/friendlyarm/nanopi4/Makefile b/board/friendlyarm/nanopi4/Makefile +new file mode 100644 +index 0000000000..33a1466567 +--- /dev/null ++++ b/board/friendlyarm/nanopi4/Makefile +@@ -0,0 +1,8 @@ ++# ++# Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd. ++# (http://www.friendlyarm.com) ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += nanopi4.o hwrev.o +diff --git a/board/friendlyarm/nanopi4/README b/board/friendlyarm/nanopi4/README +new file mode 100644 +index 0000000000..c6f58203eb +--- /dev/null ++++ b/board/friendlyarm/nanopi4/README +@@ -0,0 +1,122 @@ ++Introduction ++============ ++ ++RK3399 key features we might use in U-Boot: ++* CPU: ARMv8 64bit Big-Little architecture, ++* Big: dual-core Cortex-A72 ++* Little: quad-core Cortex-A53 ++* IRAM: 200KB ++* DRAM: 4GB-128MB dual-channel ++* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50 ++* SD/MMC: support SD 3.0, MMC 4.51 ++* USB: USB3.0 type-C port *2 with dwc3 controller ++* USB2.0 EHCI host port *2 ++* Display: RGB/HDMI/DP/MIPI/EDP ++ ++evb key features: ++* regulator: pwm regulator for CPU B/L ++* PMIC: rk808 ++* debug console: UART2 ++ ++In order to support Arm Trust Firmware(ATF), we can use either SPL or ++miniloader from rockchip to do: ++* do DRAM init ++* load and verify ATF image ++* load and verify U-Boot image ++ ++Here is the step-by-step to boot to U-Boot on rk3399. ++ ++Get the Source and prebuild binary ++================================== ++ ++ > mkdir ~/evb_rk3399 ++ > cd ~/evb_rk3399 ++ > git clone https://github.com/ARM-software/arm-trusted-firmware.git ++ > git clone https://github.com/rockchip-linux/rkbin.git ++ > git clone https://github.com/rockchip-linux/rkdeveloptool.git ++ ++ ++Compile ATF ++=========== ++ ++ > cd arm-trusted-firmware ++ > make realclean ++ > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 ++ ++ Get bl31.elf in this step, copy it to U-Boot root dir: ++ > cp build/rk3399/release/bl31/bl31.elf ../u-boot/ ++ ++ Or you can get the bl31.elf directly from Rockchip: ++ > cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf ++ ++ ++Compile U-Boot ++============== ++ ++ > cd ../u-boot ++ > export CROSS_COMPILE=aarch64-linux-gnu- ++ > make evb-rk3399_defconfig ++ for firefly-rk3399, use below instead: ++ > make firefly-rk3399_defconfig ++ > make ++ > make u-boot.itb ++ ++ Get spl/u-boot-spl.bin and u-boot.itb in this step. ++ ++Compile rkdeveloptool ++===================== ++ ++Get rkdeveloptool installed on your Host in this step. ++ ++Follow instructions in latest README, example: ++ > cd ../rkdeveloptool ++ > autoreconf -i ++ > ./configure ++ > make ++ > sudo make install ++ ++Both origin binaries and Tool are ready now, choose either option 1 or ++option 2 to deploy U-Boot. ++ ++Package the image ++================= ++ ++Package the image for U-Boot SPL(option 1) ++-------------------------------- ++ > cd .. ++ > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img ++ ++ Get idbspl.img in this step. ++ ++Package the image for Rockchip miniloader(option 2) ++------------------------------------------ ++ > cd .. ++ > cp arm-trusted-firmware/build/rk3399/release/bl31.elf rkbin/rk33 ++ > ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini ++ > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img ++ ++ Get trust.img and uboot.img in this step. ++ ++Flash the image to eMMC ++======================= ++ ++Flash the image with U-Boot SPL(option 1) ++------------------------------- ++Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: ++ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin ++ > rkdeveloptool wl 64 u-boot/idbspl.img ++ > rkdeveloptool wl 0x4000 u-boot/u-boot.itb ++ > rkdeveloptool rd ++ ++Flash the image with Rockchip miniloader(option 2) ++---------------------------------------- ++Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: ++ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin ++ > rkdeveloptool ul rkbin/rk33/rk3399_loader_v1.08.106.bin ++ > rkdeveloptool wl 0x4000 u-boot/uboot.img ++ > rkdeveloptool wl 0x6000 u-boot/trust.img ++ > rkdeveloptool rd ++ ++You should be able to get U-Boot log in console/UART2(baurdrate 1500000) ++For more detail, please reference to: ++http://opensource.rock-chips.com/wiki_Boot_option +diff --git a/board/friendlyarm/nanopi4/hwrev.c b/board/friendlyarm/nanopi4/hwrev.c +new file mode 100644 +index 0000000000..9199a927ee +--- /dev/null ++++ b/board/friendlyarm/nanopi4/hwrev.c +@@ -0,0 +1,149 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * ID info: ++ * ID : Volts : ADC value : Bucket ++ * == ===== ========= =========== ++ * 0 : 0.102V: 58 : 0 - 81 ++ * 1 : 0.211V: 120 : 82 - 150 ++ * 2 : 0.319V: 181 : 151 - 211 ++ * 3 : 0.427V: 242 : 212 - 274 ++ * 4 : 0.542V: 307 : 275 - 342 ++ * 5 : 0.666V: 378 : 343 - 411 ++ * 6 : 0.781V: 444 : 412 - 477 ++ * 7 : 0.900V: 511 : 478 - 545 ++ * 8 : 1.023V: 581 : 546 - 613 ++ * 9 : 1.137V: 646 : 614 - 675 ++ * 10 : 1.240V: 704 : 676 - 733 ++ * 11 : 1.343V: 763 : 734 - 795 ++ * 12 : 1.457V: 828 : 796 - 861 ++ * 13 : 1.576V: 895 : 862 - 925 ++ * 14 : 1.684V: 956 : 926 - 989 ++ * 15 : 1.800V: 1023 : 990 - 1023 ++ */ ++static const int id_readings[] = { ++ 81, 150, 211, 274, 342, 411, 477, 545, ++ 613, 675, 733, 795, 861, 925, 989, 1023 ++}; ++ ++static int cached_board_id = -1; ++ ++#define SARADC_BASE 0xFF100000 ++#define SARADC_DATA (SARADC_BASE + 0) ++#define SARADC_CTRL (SARADC_BASE + 8) ++ ++static u32 get_saradc_value(int chn) ++{ ++ int timeout = 0; ++ u32 adc_value = 0; ++ ++ writel(0, SARADC_CTRL); ++ udelay(2); ++ ++ writel(0x28 | chn, SARADC_CTRL); ++ udelay(50); ++ ++ timeout = 0; ++ do { ++ if (readl(SARADC_CTRL) & 0x40) { ++ adc_value = readl(SARADC_DATA) & 0x3FF; ++ goto stop_adc; ++ } ++ ++ udelay(10); ++ } while (timeout++ < 100); ++ ++stop_adc: ++ writel(0, SARADC_CTRL); ++ ++ return adc_value; ++} ++ ++static uint32_t get_adc_index(int chn) ++{ ++ int i; ++ int adc_reading; ++ ++ if (cached_board_id != -1) ++ return cached_board_id; ++ ++ adc_reading = get_saradc_value(chn); ++ for (i = 0; i < ARRAY_SIZE(id_readings); i++) { ++ if (adc_reading <= id_readings[i]) { ++ debug("ADC reading %d, ID %d\n", adc_reading, i); ++ cached_board_id = i; ++ return i; ++ } ++ } ++ ++ /* should die for impossible value */ ++ return 0; ++} ++ ++/* ++ * Board revision list: ++ * 0b00 - NanoPC-T4 ++ * 0b01 - NanoPi M4 ++ * ++ * Extended by ADC_IN4 ++ * Group A: ++ * 0x04 - NanoPi NEO4 ++ * 0x06 - SOC-RK3399 ++ * ++ * Group B: ++ * 0x21 - NanoPi M4 Ver2.0 ++ */ ++static int pcb_rev = -1; ++ ++void bd_hwrev_init(void) ++{ ++#define GPIO4_BASE 0xff790000 ++ struct rockchip_gpio_regs *regs = (void *)GPIO4_BASE; ++ ++#ifdef CONFIG_SPL_BUILD ++ struct udevice *dev; ++ ++ if (uclass_get_device_by_driver(UCLASS_CLK, ++ DM_GET_DRIVER(clk_rk3399), &dev)) ++ return; ++#endif ++ ++ if (pcb_rev >= 0) ++ return; ++ ++ /* D1, D0: input mode */ ++ clrbits_le32(®s->swport_ddr, (0x3 << 24)); ++ pcb_rev = (readl(®s->ext_port) >> 24) & 0x3; ++ ++ if (pcb_rev == 0x3) { ++ /* Revision group A: 0x04 ~ 0x13 */ ++ pcb_rev = 0x4 + get_adc_index(4); ++ ++ } else if (pcb_rev == 0x1) { ++ int idx = get_adc_index(4); ++ ++ /* Revision group B: 0x21 ~ 0x2f */ ++ if (idx > 0) { ++ pcb_rev = 0x20 + idx; ++ } ++ } ++} ++ ++/* To override __weak symbols */ ++u32 get_board_rev(void) ++{ ++ return pcb_rev; ++} ++ +diff --git a/board/friendlyarm/nanopi4/hwrev.h b/board/friendlyarm/nanopi4/hwrev.h +new file mode 100644 +index 0000000000..23b3c7a557 +--- /dev/null ++++ b/board/friendlyarm/nanopi4/hwrev.h +@@ -0,0 +1,27 @@ ++/* ++ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, you can access it online at ++ * http://www.gnu.org/licenses/gpl-2.0.html. ++ */ ++ ++#ifndef __BD_HW_REV_H__ ++#define __BD_HW_REV_H__ ++ ++extern void bd_hwrev_config_gpio(void); ++extern void bd_hwrev_init(void); ++extern u32 get_board_rev(void); ++ ++#endif /* __BD_HW_REV_H__ */ +diff --git a/board/friendlyarm/nanopi4/nanopi4.c b/board/friendlyarm/nanopi4/nanopi4.c +new file mode 100644 +index 0000000000..a140370ca2 +--- /dev/null ++++ b/board/friendlyarm/nanopi4/nanopi4.c +@@ -0,0 +1,148 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_MISC_INIT_R ++static void setup_iodomain(void) ++{ ++ struct rk3399_grf_regs *grf = ++ syscon_get_first_range(ROCKCHIP_SYSCON_GRF); ++ ++ /* BT565 and AUDIO is in 1.8v domain */ ++ rk_setreg(&grf->io_vsel, BIT(0) | BIT(1)); ++} ++ ++static int __maybe_unused mac_read_from_generic_eeprom(u8 *addr) ++{ ++ struct udevice *i2c_dev; ++ int ret; ++ ++ /* Microchip 24AA02xxx EEPROMs with EUI-48 Node Identity */ ++ ret = i2c_get_chip_for_busnum(2, 0x51, 1, &i2c_dev); ++ if (!ret) ++ ret = dm_i2c_read(i2c_dev, 0xfa, addr, 6); ++ ++ return ret; ++} ++ ++static void setup_macaddr(void) ++{ ++#if CONFIG_IS_ENABLED(CMD_NET) ++ int ret; ++ const char *cpuid = env_get("cpuid#"); ++ u8 hash[SHA256_SUM_LEN]; ++ int size = sizeof(hash); ++ u8 mac_addr[6]; ++ int from_eeprom = 0; ++ int lockdown = 0; ++ ++#ifndef CONFIG_ENV_IS_NOWHERE ++ lockdown = env_get_yesno("lockdown") == 1; ++#endif ++ if (lockdown && env_get("ethaddr")) ++ return; ++ ++ ret = mac_read_from_generic_eeprom(mac_addr); ++ if (!ret && is_valid_ethaddr(mac_addr)) { ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ from_eeprom = 1; ++ } ++ ++ if (!cpuid) { ++ debug("%s: could not retrieve 'cpuid#'\n", __func__); ++ return; ++ } ++ ++ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); ++ if (ret) { ++ debug("%s: failed to calculate SHA256\n", __func__); ++ return; ++ } ++ ++ /* Copy 6 bytes of the hash to base the MAC address on */ ++ memcpy(mac_addr, hash, 6); ++ ++ /* Make this a valid MAC address and set it */ ++ mac_addr[0] &= 0xfe; /* clear multicast bit */ ++ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ ++ ++ if (from_eeprom) { ++ eth_env_set_enetaddr("eth1addr", mac_addr); ++ } else { ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++ ++ if (lockdown && env_get("eth1addr")) ++ return; ++ ++ /* Ugly, copy another 4 bytes to generate a similar address */ ++ memcpy(mac_addr + 2, hash + 8, 4); ++ if (!memcmp(hash + 2, hash + 8, 4)) ++ mac_addr[5] ^= 0xff; ++ ++ eth_env_set_enetaddr("eth1addr", mac_addr); ++ } ++#endif ++ ++ return; ++} ++ ++int misc_init_r(void) ++{ ++ const u32 cpuid_offset = 0x7; ++ const u32 cpuid_length = 0x10; ++ u8 cpuid[cpuid_length]; ++ int ret; ++ ++ setup_iodomain(); ++ ++ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid); ++ if (ret) ++ return ret; ++ ++ ret = rockchip_cpuid_set(cpuid, cpuid_length); ++ if (ret) ++ return ret; ++ ++ setup_macaddr(); ++ bd_hwrev_init(); ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_SERIAL_TAG ++void get_board_serial(struct tag_serialnr *serialnr) ++{ ++ char *serial_string; ++ u64 serial = 0; ++ ++ serial_string = env_get("serial#"); ++ ++ if (serial_string) ++ serial = simple_strtoull(serial_string, NULL, 16); ++ ++ serialnr->high = (u32)(serial >> 32); ++ serialnr->low = (u32)(serial & 0xffffffff); ++} ++#endif +diff --git a/configs/nanopi-r4s-4gb-rk3399_defconfig b/configs/nanopi-r4s-4gb-rk3399_defconfig +index dcac8d426f..147bffad9d 100644 +--- a/configs/nanopi-r4s-4gb-rk3399_defconfig ++++ b/configs/nanopi-r4s-4gb-rk3399_defconfig +@@ -4,13 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0x3F8000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_TARGET_EVB_RK3399=y ++CONFIG_TARGET_NANOPI4=y + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s-4gb" + CONFIG_DEBUG_UART=y + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s-4gb.dtb" +-CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set + CONFIG_SPL_STACK_R=y + CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig +index 034241f209..b67f7c0dc9 100644 +--- a/configs/nanopi-r4s-rk3399_defconfig ++++ b/configs/nanopi-r4s-rk3399_defconfig +@@ -4,13 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x00200000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_ENV_OFFSET=0x3F8000 + CONFIG_ROCKCHIP_RK3399=y +-CONFIG_TARGET_EVB_RK3399=y ++CONFIG_TARGET_NANOPI4=y + CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" + CONFIG_DEBUG_UART=y + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" +-CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_MISC_INIT_R=y + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set + CONFIG_SPL_STACK_R=y + CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c +index 22c373a623..38975c0c65 100644 +--- a/drivers/clk/rockchip/clk_rk3399.c ++++ b/drivers/clk/rockchip/clk_rk3399.c +@@ -1351,6 +1351,8 @@ static void rkclk_init(struct rockchip_cru *cru) + pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | + HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); ++ ++ rk3399_saradc_set_clk(cru, 1000000); + } + #endif + +diff --git a/include/configs/nanopi4.h b/include/configs/nanopi4.h +new file mode 100644 +index 0000000000..a86d38976a +--- /dev/null ++++ b/include/configs/nanopi4.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd. ++ * (http://www.friendlyarm.com) ++ * ++ * (C) Copyright 2016 Rockchip Electronics Co., Ltd ++ */ ++ ++#ifndef __CONFIG_NANOPI4_H__ ++#define __CONFIG_NANOPI4_H__ ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdin=serial,usbkbd\0" \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#include ++ ++#define SDRAM_BANK_SIZE (2UL << 30) ++ ++#define CONFIG_SERIAL_TAG ++#define CONFIG_REVISION_TAG ++ ++#endif +-- +2.25.1 + diff --git a/patch/u-boot/u-boot-media/board_nanopi-r4s/0003-ram-rk3399-Add-support-for-multiple-DDR-types.patch b/patch/u-boot/u-boot-media/board_nanopi-r4s/0003-ram-rk3399-Add-support-for-multiple-DDR-types.patch new file mode 100644 index 000000000..b9fbb7519 --- /dev/null +++ b/patch/u-boot/u-boot-media/board_nanopi-r4s/0003-ram-rk3399-Add-support-for-multiple-DDR-types.patch @@ -0,0 +1,275 @@ +From 1bc90230df5cd55513268f2f7a43abdbad1161b5 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Sat, 19 Dec 2020 19:39:14 +0800 +Subject: [PATCH 3/4] ram: rk3399: Add support for multiple DDR types + +Move rockchip,sdram-params to named subnode to include +multiple sdram parameters, and then read the parameters +(by subnode name, first subnode or current node) before +rk3399_dmc_init(). + +Signed-off-by: hmz007 +--- + arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi | 6 ++- + arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi | 5 +- + arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi | 6 ++- + .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 3 ++ + .../arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi | 3 ++ + .../rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi | 3 ++ + arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 3 ++ + drivers/ram/rockchip/sdram_rk3399.c | 49 +++++++++++++++---- + 8 files changed, 64 insertions(+), 14 deletions(-) + +diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi +index 7fae249536..dad5b7fbd4 100644 +--- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1333 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,5 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +- +diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi +index 23c7c34a9a..238f667a76 100644 +--- a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1600 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,4 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi +index ea029ca90a..7f6b95fe42 100644 +--- a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi ++++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi +@@ -4,7 +4,9 @@ + */ + + &dmc { +- rockchip,sdram-params = < ++ ddr3-1866 { ++ u-boot,dm-pre-reloc; ++ rockchip,sdram-params = < + 0x1 + 0xa + 0x3 +@@ -1536,5 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +- +diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi +index 7296dbb80e..a83564794e 100644 +--- a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi +@@ -5,6 +5,8 @@ + */ + + &dmc { ++ lpddr3-2GB-1600 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x1 + 0xa +@@ -1537,4 +1539,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi +index bf429c21e4..537936c6fb 100644 +--- a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi +@@ -4,6 +4,8 @@ + */ + + &dmc { ++ lpddr3-4GB-1600 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1536,4 +1538,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi +index 96f459fd0b..a0acdb5add 100644 +--- a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi +@@ -4,6 +4,8 @@ + */ + + &dmc { ++ lpddr3-samsung-4GB-1866 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1543,4 +1545,5 @@ + 0x01010000 /* DENALI_PHY_957_DATA */ + 0x00000000 /* DENALI_PHY_958_DATA */ + >; ++ }; + }; +diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi +index f0c478d189..21d212236f 100644 +--- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi ++++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi +@@ -6,6 +6,8 @@ + */ + + &dmc { ++ lpddr4-100 { ++ u-boot,dm-pre-reloc; + rockchip,sdram-params = < + 0x2 + 0xa +@@ -1538,4 +1540,5 @@ + 0x01010000 + 0x00000000 + >; ++ }; + }; +diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c +index 530c8a2f40..db30105989 100644 +--- a/drivers/ram/rockchip/sdram_rk3399.c ++++ b/drivers/ram/rockchip/sdram_rk3399.c +@@ -1625,7 +1625,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) + rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10); + } + +-#if !defined(CONFIG_RAM_RK3399_LPDDR4) + static int data_training_first(struct dram_info *dram, u32 channel, u8 rank, + struct rk3399_sdram_params *params) + { +@@ -1715,8 +1714,8 @@ void modify_param(const struct chan_info *chan, + clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24); + clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1); + } +-#else + ++#if defined(CONFIG_RAM_RK3399_LPDDR4) + struct rk3399_sdram_params dfs_cfgs_lpddr4[] = { + #include "sdram-rk3399-lpddr4-400.inc" + #include "sdram-rk3399-lpddr4-800.inc" +@@ -3011,20 +3010,40 @@ static int sdram_init(struct dram_info *dram, + return 0; + } + ++__weak const char *rk3399_get_ddrtype(void) ++{ ++ return NULL; ++} ++ + static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) + { + #if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rockchip_dmc_plat *plat = dev_get_platdata(dev); ++ ofnode node = { .np = NULL }; ++ const char *name; + int ret; + +- ret = dev_read_u32_array(dev, "rockchip,sdram-params", +- (u32 *)&plat->sdram_params, +- sizeof(plat->sdram_params) / sizeof(u32)); ++ name = rk3399_get_ddrtype(); ++ if (name) ++ node = dev_read_subnode(dev, name); ++ if (!ofnode_valid(node)) { ++ debug("Failed to read subnode %s\n", name); ++ node = dev_read_first_subnode(dev); ++ } ++ ++ /* fallback to current node */ ++ if (!ofnode_valid(node)) ++ node = dev_ofnode(dev); ++ ++ ret = ofnode_read_u32_array(node, "rockchip,sdram-params", ++ (u32 *)&plat->sdram_params, ++ sizeof(plat->sdram_params) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params %d\n", + __func__, ret); + return ret; + } ++ + ret = regmap_init_mem(dev_ofnode(dev), &plat->map); + if (ret) + printf("%s: regmap failed %d\n", __func__, ret); +@@ -3051,18 +3070,20 @@ static int conv_of_platdata(struct udevice *dev) + #endif + + static const struct sdram_rk3399_ops rk3399_ops = { +-#if !defined(CONFIG_RAM_RK3399_LPDDR4) + .data_training_first = data_training_first, + .set_rate_index = switch_to_phy_index1, + .modify_param = modify_param, + .get_phy_index_params = get_phy_index_params, +-#else ++}; ++ ++#if defined(CONFIG_RAM_RK3399_LPDDR4) ++static const struct sdram_rk3399_ops lpddr4_ops = { + .data_training_first = lpddr4_mr_detect, + .set_rate_index = lpddr4_set_rate, + .modify_param = lpddr4_modify_param, + .get_phy_index_params = lpddr4_get_phy_index_params, +-#endif + }; ++#endif + + static int rk3399_dmc_init(struct udevice *dev) + { +@@ -3081,7 +3102,17 @@ static int rk3399_dmc_init(struct udevice *dev) + return ret; + #endif + +- priv->ops = &rk3399_ops; ++ if (params->base.dramtype == LPDDR4) { ++#if defined(CONFIG_RAM_RK3399_LPDDR4) ++ priv->ops = &lpddr4_ops; ++#else ++ printf("LPDDR4 support is disable\n"); ++ return -EINVAL; ++#endif ++ } else { ++ priv->ops = &rk3399_ops; ++ } ++ + priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); +-- +2.25.1 + diff --git a/patch/u-boot/u-boot-media/board_nanopi-r4s/0004-board-nanopi4-unify-1GB-4GB-variants-of-R4S.patch b/patch/u-boot/u-boot-media/board_nanopi-r4s/0004-board-nanopi4-unify-1GB-4GB-variants-of-R4S.patch new file mode 100644 index 000000000..25574cf96 --- /dev/null +++ b/patch/u-boot/u-boot-media/board_nanopi-r4s/0004-board-nanopi4-unify-1GB-4GB-variants-of-R4S.patch @@ -0,0 +1,304 @@ +From 317331b3d7ddcf2a5e7b5a9002ac559627000032 Mon Sep 17 00:00:00 2001 +From: hmz007 +Date: Sat, 19 Dec 2020 20:39:29 +0800 +Subject: [PATCH 4/4] board: nanopi4: unify 1GB/4GB variants of R4S + +Signed-off-by: hmz007 +--- + .../arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi | 8 -- + arch/arm/dts/rk3399-nanopi-r4s-4gb.dts | 114 ------------------ + arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 2 + + board/friendlyarm/nanopi4/hwrev.c | 36 ++++++ + configs/nanopi-r4s-4gb-rk3399_defconfig | 63 ---------- + configs/nanopi-r4s-rk3399_defconfig | 1 + + 6 files changed, 39 insertions(+), 185 deletions(-) + delete mode 100644 arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi + delete mode 100644 arch/arm/dts/rk3399-nanopi-r4s-4gb.dts + delete mode 100644 configs/nanopi-r4s-4gb-rk3399_defconfig + +diff --git a/arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi +deleted file mode 100644 +index b291830640..0000000000 +--- a/arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi ++++ /dev/null +@@ -1,8 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Copyright (C) 2019 Jagan Teki +- * Copyright (C) 2020 Deepak Das +- */ +- +-#include "rk3399-nanopi4-u-boot.dtsi" +-#include "rk3399-sdram-lpddr4-100.dtsi" +diff --git a/arch/arm/dts/rk3399-nanopi-r4s-4gb.dts b/arch/arm/dts/rk3399-nanopi-r4s-4gb.dts +deleted file mode 100644 +index 3072880c77..0000000000 +--- a/arch/arm/dts/rk3399-nanopi-r4s-4gb.dts ++++ /dev/null +@@ -1,114 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +-/* +- * FriendlyElec NanoPi R4S board device tree source +- * +- * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. +- * (http://www.friendlyarm.com) +- * +- * Copyright (c) 2018 Collabora Ltd. +- * Copyright (c) 2019 Arm Ltd. +- */ +- +-/dts-v1/; +-#include "rk3399-nanopi4.dtsi" +- +-/ { +- model = "FriendlyElec NanoPi R4S"; +- compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; +- +- vdd_5v: vdd-5v { +- compatible = "regulator-fixed"; +- regulator-name = "vdd_5v"; +- regulator-always-on; +- regulator-boot-on; +- }; +- +- vcc5v0_usb1: vcc5v0-usb1 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb1"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_5v>; +- }; +- +- vcc5v0_usb2: vcc5v0-usb2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb2"; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <&vdd_5v>; +- }; +- +- fan: pwm-fan { +- compatible = "pwm-fan"; +- /* +- * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels +- * work out to 0, ~1200, ~3000, and 5000RPM respectively. +- */ +- cooling-levels = <0 12 18 255>; +- #cooling-cells = <2>; +- fan-supply = <&vdd_5v>; +- pwms = <&pwm1 0 50000 0>; +- }; +-}; +- +-&cpu_thermal { +- trips { +- cpu_warm: cpu_warm { +- temperature = <55000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- +- cpu_hot: cpu_hot { +- temperature = <65000>; +- hysteresis = <2000>; +- type = "active"; +- }; +- }; +- +- cooling-maps { +- map2 { +- trip = <&cpu_warm>; +- cooling-device = <&fan THERMAL_NO_LIMIT 1>; +- }; +- +- map3 { +- trip = <&cpu_hot>; +- cooling-device = <&fan 2 THERMAL_NO_LIMIT>; +- }; +- }; +-}; +- +-&emmc_phy { +- status = "disabled"; +-}; +- +-&fusb0 { +- status = "disabled"; +-}; +- +-&pcie0 { +- num-lanes = <1>; +- vpcie3v3-supply = <&vcc3v3_sys>; +-}; +- +-&sdhci { +- status = "disabled"; +-}; +- +-&sdio0 { +- status = "disabled"; +-}; +- +-&u2phy0_host { +- phy-supply = <&vdd_5v>; +-}; +- +-&u2phy1_host { +- status = "disabled"; +-}; +- +-&vcc3v3_sys { +- vin-supply = <&vcc5v0_sys>; +-}; +diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi +index eb0aca4758..9369a7022a 100644 +--- a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi ++++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi +@@ -4,4 +4,6 @@ + */ + + #include "rk3399-nanopi4-u-boot.dtsi" ++#include "rk3399-sdram-lpddr4-100.dtsi" ++#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" + #include "rk3399-sdram-ddr3-1866.dtsi" +diff --git a/board/friendlyarm/nanopi4/hwrev.c b/board/friendlyarm/nanopi4/hwrev.c +index 9199a927ee..812fcef9c7 100644 +--- a/board/friendlyarm/nanopi4/hwrev.c ++++ b/board/friendlyarm/nanopi4/hwrev.c +@@ -101,9 +101,13 @@ static uint32_t get_adc_index(int chn) + * Group A: + * 0x04 - NanoPi NEO4 + * 0x06 - SOC-RK3399 ++ * 0x07 - SOC-RK3399 V2 ++ * 0x09 - NanoPi R4S 1GB ++ * 0x0A - NanoPi R4S 4GB + * + * Group B: + * 0x21 - NanoPi M4 Ver2.0 ++ * 0x22 - NanoPi M4B + */ + static int pcb_rev = -1; + +@@ -141,6 +145,38 @@ void bd_hwrev_init(void) + } + } + ++#ifdef CONFIG_SPL_BUILD ++static struct board_ddrtype { ++ int rev; ++ const char *type; ++} ddrtypes[] = { ++ { 0x00, "lpddr3-samsung-4GB-1866" }, ++ { 0x01, "lpddr3-samsung-4GB-1866" }, ++ { 0x04, "ddr3-1866" }, ++ { 0x06, "ddr3-1866" }, ++ { 0x07, "lpddr4-100" }, ++ { 0x09, "ddr3-1866" }, ++ { 0x0a, "lpddr4-100" }, ++ { 0x21, "lpddr4-100" }, ++ { 0x22, "ddr3-1866" }, ++}; ++ ++const char *rk3399_get_ddrtype(void) { ++ int i; ++ ++ bd_hwrev_init(); ++ printf("Board: rev%02x\n", pcb_rev); ++ ++ for (i = 0; i < ARRAY_SIZE(ddrtypes); i++) { ++ if (ddrtypes[i].rev == pcb_rev) ++ return ddrtypes[i].type; ++ } ++ ++ /* fallback to first subnode (ie, first included dtsi) */ ++ return NULL; ++} ++#endif ++ + /* To override __weak symbols */ + u32 get_board_rev(void) + { +diff --git a/configs/nanopi-r4s-4gb-rk3399_defconfig b/configs/nanopi-r4s-4gb-rk3399_defconfig +deleted file mode 100644 +index 147bffad9d..0000000000 +--- a/configs/nanopi-r4s-4gb-rk3399_defconfig ++++ /dev/null +@@ -1,63 +0,0 @@ +-CONFIG_ARM=y +-CONFIG_ARCH_ROCKCHIP=y +-CONFIG_SYS_TEXT_BASE=0x00200000 +-CONFIG_NR_DRAM_BANKS=1 +-CONFIG_ENV_OFFSET=0x3F8000 +-CONFIG_ROCKCHIP_RK3399=y +-CONFIG_TARGET_NANOPI4=y +-CONFIG_DEBUG_UART_BASE=0xFF1A0000 +-CONFIG_DEBUG_UART_CLOCK=24000000 +-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s-4gb" +-CONFIG_DEBUG_UART=y +-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s-4gb.dtb" +-CONFIG_MISC_INIT_R=y +-# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +-CONFIG_SPL_STACK_R=y +-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +-CONFIG_TPL=y +-CONFIG_CMD_BOOTZ=y +-CONFIG_CMD_GPT=y +-CONFIG_CMD_MMC=y +-CONFIG_CMD_USB=y +-# CONFIG_CMD_SETEXPR is not set +-CONFIG_CMD_TIME=y +-CONFIG_SPL_OF_CONTROL=y +-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +-CONFIG_ENV_IS_IN_MMC=y +-CONFIG_SYS_RELOC_GD_ENV_ADDR=y +-CONFIG_SYS_MMC_ENV_DEV=1 +-CONFIG_ROCKCHIP_GPIO=y +-CONFIG_SYS_I2C_ROCKCHIP=y +-CONFIG_MMC_DW=y +-CONFIG_MMC_DW_ROCKCHIP=y +-CONFIG_MMC_SDHCI=y +-CONFIG_MMC_SDHCI_ROCKCHIP=y +-CONFIG_DM_ETH=y +-CONFIG_ETH_DESIGNWARE=y +-CONFIG_GMAC_ROCKCHIP=y +-CONFIG_PMIC_RK8XX=y +-CONFIG_REGULATOR_PWM=y +-CONFIG_REGULATOR_RK8XX=y +-CONFIG_PWM_ROCKCHIP=y +-CONFIG_RAM_RK3399_LPDDR4=y +-CONFIG_BAUDRATE=1500000 +-CONFIG_DEBUG_UART_SHIFT=2 +-CONFIG_SYSRESET=y +-CONFIG_USB=y +-CONFIG_USB_XHCI_HCD=y +-CONFIG_USB_XHCI_DWC3=y +-CONFIG_USB_EHCI_HCD=y +-CONFIG_USB_EHCI_GENERIC=y +-CONFIG_USB_KEYBOARD=y +-CONFIG_USB_HOST_ETHER=y +-CONFIG_USB_ETHER_ASIX=y +-CONFIG_USB_ETHER_ASIX88179=y +-CONFIG_USB_ETHER_MCS7830=y +-CONFIG_USB_ETHER_RTL8152=y +-CONFIG_USB_ETHER_SMSC95XX=y +-CONFIG_DM_VIDEO=y +-CONFIG_DISPLAY=y +-CONFIG_VIDEO_ROCKCHIP=y +-CONFIG_DISPLAY_ROCKCHIP_HDMI=y +-CONFIG_SPL_TINY_MEMSET=y +-CONFIG_ERRNO_STR=y +diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig +index b67f7c0dc9..f1776eee73 100644 +--- a/configs/nanopi-r4s-rk3399_defconfig ++++ b/configs/nanopi-r4s-rk3399_defconfig +@@ -39,6 +39,7 @@ CONFIG_PMIC_RK8XX=y + CONFIG_REGULATOR_PWM=y + CONFIG_REGULATOR_RK8XX=y + CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_RK3399_LPDDR4=y + CONFIG_BAUDRATE=1500000 + CONFIG_DEBUG_UART_SHIFT=2 + CONFIG_SYSRESET=y +-- +2.25.1 +