move kernel media current 6.1 and edge 6.2 (#4781)
* move kernel media current 6.1 and edge 6.2 add board quartz64b * fix nanopc-t4
This commit is contained in:
Oleg
GitHub
parent
133c595539
commit
20ee08325f
12
config/boards/quartz64b.wip
Normal file
12
config/boards/quartz64b.wip
Normal file
@ -0,0 +1,12 @@
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# Rockchip RK3566 quad core 4GB-8GB GBE PCIe USB3
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BOARD_NAME="Pine Quartz64 B"
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BOARDFAMILY="media"
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BOOT_SOC="rk3568"
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BOOTCONFIG="quartz64-b-rk3566_defconfig"
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KERNEL_TARGET="current,edge"
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FULL_DESKTOP="yes"
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BOOT_LOGO="desktop"
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BOOT_FDT_FILE="rockchip/rk3566-quartz64-b.dtb"
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SRC_EXTLINUX="yes"
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SRC_CMDLINE="console=ttyS02,1500000 console=tty0"
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IMAGE_PARTITION_TABLE="gpt"
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File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
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#
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# Automatically generated file; DO NOT EDIT.
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# Linux/arm64 6.1.6 Kernel Configuration
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# Linux/arm64 6.2.0-rc6 Kernel Configuration
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#
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CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
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CONFIG_CC_IS_GCC=y
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@ -59,7 +59,6 @@ CONFIG_IRQ_SIM=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_GENERIC_IRQ_IPI=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_IRQ_MSI_IOMMU=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_SPARSE_IRQ=y
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@ -227,6 +226,7 @@ CONFIG_INITRAMFS_PRESERVE_MTIME=y
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CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
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# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
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CONFIG_LD_ORPHAN_WARN=y
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CONFIG_LD_ORPHAN_WARN_LEVEL="warn"
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CONFIG_SYSCTL=y
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CONFIG_HAVE_UID16=y
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CONFIG_SYSCTL_EXCEPTION_TRACE=y
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@ -253,6 +253,7 @@ CONFIG_IO_URING=y
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CONFIG_ADVISE_SYSCALLS=y
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CONFIG_MEMBARRIER=y
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CONFIG_KALLSYMS=y
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# CONFIG_KALLSYMS_SELFTEST is not set
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CONFIG_KALLSYMS_ALL=y
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CONFIG_KALLSYMS_BASE_RELATIVE=y
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CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
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@ -277,7 +278,7 @@ CONFIG_TRACEPOINTS=y
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# end of General setup
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CONFIG_ARM64=y
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CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
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CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
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CONFIG_64BIT=y
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CONFIG_MMU=y
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CONFIG_ARM64_PAGE_SHIFT=12
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@ -380,6 +381,7 @@ CONFIG_ARM64_ERRATUM_2054223=y
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CONFIG_ARM64_ERRATUM_2067961=y
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CONFIG_ARM64_ERRATUM_2441009=y
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CONFIG_ARM64_ERRATUM_2457168=y
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CONFIG_ARM64_ERRATUM_2645198=y
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CONFIG_CAVIUM_ERRATUM_22375=y
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CONFIG_CAVIUM_ERRATUM_23144=y
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CONFIG_CAVIUM_ERRATUM_23154=y
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@ -503,7 +505,6 @@ CONFIG_ARM64_MODULE_PLTS=y
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CONFIG_RELOCATABLE=y
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CONFIG_RANDOMIZE_BASE=y
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CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
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CONFIG_ARCH_NR_GPIO=0
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# end of Kernel Features
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#
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@ -606,6 +607,7 @@ CONFIG_ACPI_CCA_REQUIRED=y
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CONFIG_ACPI_TABLE_LIB=y
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# CONFIG_ACPI_DEBUGGER is not set
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CONFIG_ACPI_SPCR_TABLE=y
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# CONFIG_ACPI_FPDT is not set
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# CONFIG_ACPI_EC_DEBUGFS is not set
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CONFIG_ACPI_AC=m
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CONFIG_ACPI_BATTERY=m
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@ -650,8 +652,10 @@ CONFIG_ACPI_CONFIGFS=m
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# CONFIG_ACPI_PFRUT is not set
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CONFIG_ACPI_IORT=y
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CONFIG_ACPI_GTDT=y
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CONFIG_ACPI_APMT=y
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CONFIG_ACPI_PPTT=y
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CONFIG_ACPI_PCC=y
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# CONFIG_ACPI_FFH is not set
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CONFIG_PMIC_OPREGION=y
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CONFIG_ACPI_VIOT=y
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CONFIG_ACPI_PRMT=y
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@ -660,6 +664,9 @@ CONFIG_HAVE_KVM=y
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CONFIG_HAVE_KVM_IRQCHIP=y
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CONFIG_HAVE_KVM_IRQFD=y
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CONFIG_HAVE_KVM_IRQ_ROUTING=y
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CONFIG_HAVE_KVM_DIRTY_RING=y
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CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y
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CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y
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CONFIG_HAVE_KVM_EVENTFD=y
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CONFIG_KVM_MMIO=y
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CONFIG_HAVE_KVM_MSI=y
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@ -716,6 +723,7 @@ CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
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CONFIG_MMU_GATHER_TABLE_FREE=y
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CONFIG_MMU_GATHER_RCU_TABLE_FREE=y
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CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
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CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y
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CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
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CONFIG_HAVE_CMPXCHG_LOCAL=y
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CONFIG_HAVE_CMPXCHG_DOUBLE=y
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@ -789,6 +797,7 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
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CONFIG_HAVE_GCC_PLUGINS=y
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CONFIG_GCC_PLUGINS=y
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# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
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CONFIG_FUNCTION_ALIGNMENT=0
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# end of General architecture-dependent options
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CONFIG_RT_MUTEXES=y
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@ -945,7 +954,8 @@ CONFIG_ZSMALLOC=y
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#
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# CONFIG_SLAB is not set
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CONFIG_SLUB=y
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# CONFIG_SLOB is not set
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# CONFIG_SLOB_DEPRECATED is not set
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# CONFIG_SLUB_TINY is not set
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CONFIG_SLAB_MERGE_DEFAULT=y
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CONFIG_SLAB_FREELIST_RANDOM=y
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# CONFIG_SLAB_FREELIST_HARDENED is not set
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@ -1225,6 +1235,7 @@ CONFIG_NF_NAT_SIP=m
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CONFIG_NF_NAT_TFTP=m
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CONFIG_NF_NAT_REDIRECT=y
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CONFIG_NF_NAT_MASQUERADE=y
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CONFIG_NF_NAT_OVS=y
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CONFIG_NETFILTER_SYNPROXY=m
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CONFIG_NF_TABLES=m
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CONFIG_NF_TABLES_INET=y
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@ -1239,7 +1250,6 @@ CONFIG_NFT_MASQ=m
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CONFIG_NFT_REDIR=m
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CONFIG_NFT_NAT=m
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CONFIG_NFT_TUNNEL=m
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CONFIG_NFT_OBJREF=m
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CONFIG_NFT_QUEUE=m
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CONFIG_NFT_QUOTA=m
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CONFIG_NFT_REJECT=m
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@ -1579,6 +1589,7 @@ CONFIG_BRIDGE_VLAN_FILTERING=y
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CONFIG_BRIDGE_MRP=y
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CONFIG_BRIDGE_CFM=y
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CONFIG_NET_DSA=m
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CONFIG_NET_DSA_TAG_NONE=m
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CONFIG_NET_DSA_TAG_AR9331=m
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CONFIG_NET_DSA_TAG_BRCM_COMMON=m
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CONFIG_NET_DSA_TAG_BRCM=m
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@ -1821,6 +1832,7 @@ CONFIG_BT_BNEP_PROTO_FILTER=y
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CONFIG_BT_HIDP=m
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CONFIG_BT_HS=y
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CONFIG_BT_LE=y
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CONFIG_BT_LE_L2CAP_ECRED=y
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CONFIG_BT_6LOWPAN=m
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CONFIG_BT_LEDS=y
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# CONFIG_BT_MSFTEXT is not set
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@ -1841,6 +1853,7 @@ CONFIG_BT_QCA=m
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CONFIG_BT_MTK=m
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CONFIG_BT_HCIBTUSB=m
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# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set
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CONFIG_BT_HCIBTUSB_POLL_SYNC=y
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CONFIG_BT_HCIBTUSB_BCM=y
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CONFIG_BT_HCIBTUSB_MTK=y
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CONFIG_BT_HCIBTUSB_RTL=y
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@ -1860,6 +1873,7 @@ CONFIG_BT_HCIUART_QCA=y
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CONFIG_BT_HCIUART_AG6XX=y
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CONFIG_BT_HCIUART_MRVL=y
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CONFIG_BT_HCIBCM203X=m
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# CONFIG_BT_HCIBCM4377 is not set
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CONFIG_BT_HCIBPA10X=m
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CONFIG_BT_HCIBFUSB=m
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CONFIG_BT_HCIDTL1=m
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@ -1880,6 +1894,7 @@ CONFIG_AF_RXRPC=m
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# CONFIG_AF_RXRPC_INJECT_LOSS is not set
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# CONFIG_AF_RXRPC_DEBUG is not set
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CONFIG_RXKAD=y
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# CONFIG_RXPERF is not set
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CONFIG_AF_KCM=m
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CONFIG_STREAM_PARSER=y
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# CONFIG_MCTP is not set
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@ -2020,7 +2035,6 @@ CONFIG_PCIE_DPC=y
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CONFIG_PCIE_PTM=y
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CONFIG_PCIE_EDR=y
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CONFIG_PCI_MSI=y
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CONFIG_PCI_MSI_IRQ_DOMAIN=y
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CONFIG_PCI_QUIRKS=y
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# CONFIG_PCI_DEBUG is not set
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CONFIG_PCI_REALLOC_ENABLE_AUTO=y
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@ -2121,6 +2135,7 @@ CONFIG_CXL_MEM=m
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CONFIG_CXL_PORT=m
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CONFIG_CXL_SUSPEND=y
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CONFIG_CXL_REGION=y
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# CONFIG_CXL_REGION_INVALIDATION_TEST is not set
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CONFIG_PCCARD=m
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CONFIG_PCMCIA=m
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CONFIG_PCMCIA_LOAD_CIS=y
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@ -2264,7 +2279,7 @@ CONFIG_FW_CFG_SYSFS=m
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CONFIG_SYSFB=y
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CONFIG_SYSFB_SIMPLEFB=y
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# CONFIG_ARM_FFA_TRANSPORT is not set
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CONFIG_CS_DSP=m
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CONFIG_FW_CS_DSP=m
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# CONFIG_GOOGLE_FIRMWARE is not set
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#
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@ -2279,7 +2294,6 @@ CONFIG_EFI_RUNTIME_WRAPPERS=y
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CONFIG_EFI_GENERIC_STUB=y
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# CONFIG_EFI_ZBOOT is not set
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CONFIG_EFI_ARMSTUB_DTB_LOADER=y
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CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
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CONFIG_EFI_BOOTLOADER_CONTROL=m
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CONFIG_EFI_CAPSULE_LOADER=m
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# CONFIG_EFI_TEST is not set
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@ -2536,6 +2550,7 @@ CONFIG_ZRAM_DEF_COMP_LZORLE=y
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CONFIG_ZRAM_DEF_COMP="lzo-rle"
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CONFIG_ZRAM_WRITEBACK=y
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# CONFIG_ZRAM_MEMORY_TRACKING is not set
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# CONFIG_ZRAM_MULTI_COMP is not set
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
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CONFIG_BLK_DEV_DRBD=m
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@ -3225,6 +3240,7 @@ CONFIG_I40EVF=m
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CONFIG_FM10K=m
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# CONFIG_IGC is not set
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CONFIG_NET_VENDOR_WANGXUN=y
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CONFIG_LIBWX=m
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CONFIG_NGBE=m
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# CONFIG_TXGBE is not set
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CONFIG_JME=m
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@ -3282,13 +3298,13 @@ CONFIG_ENC28J60_WRITEVERIFY=y
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# CONFIG_ENCX24J600 is not set
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# CONFIG_LAN743X is not set
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# CONFIG_LAN966X_SWITCH is not set
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# CONFIG_VCAP is not set
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CONFIG_NET_VENDOR_MICROSEMI=y
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CONFIG_MSCC_OCELOT_SWITCH_LIB=m
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CONFIG_MSCC_OCELOT_SWITCH=m
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CONFIG_NET_VENDOR_MICROSOFT=y
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CONFIG_NET_VENDOR_MYRI=y
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CONFIG_MYRI10GE=m
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CONFIG_FEALNX=m
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CONFIG_NET_VENDOR_NI=y
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# CONFIG_NI_XGE_MANAGEMENT_ENET is not set
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CONFIG_NET_VENDOR_NATSEMI=y
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@ -3364,6 +3380,7 @@ CONFIG_STMMAC_PLATFORM=y
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CONFIG_DWMAC_GENERIC=y
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CONFIG_DWMAC_ROCKCHIP=y
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# CONFIG_DWMAC_INTEL_PLAT is not set
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CONFIG_DWMAC_TEGRA=m
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CONFIG_DWMAC_LOONGSON=m
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# CONFIG_STMMAC_PCI is not set
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CONFIG_NET_VENDOR_SUN=y
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@ -3827,6 +3844,7 @@ CONFIG_MT7921_COMMON=m
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CONFIG_MT7921E=m
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CONFIG_MT7921S=m
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CONFIG_MT7921U=m
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CONFIG_MT7996E=m
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CONFIG_WLAN_VENDOR_MICROCHIP=y
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CONFIG_WILC1000=m
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CONFIG_WILC1000_SDIO=m
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@ -3889,22 +3907,29 @@ CONFIG_RTL8XXXU_UNTESTED=y
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CONFIG_RTW88=m
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CONFIG_RTW88_CORE=m
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CONFIG_RTW88_PCI=m
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CONFIG_RTW88_USB=m
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CONFIG_RTW88_8822B=m
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CONFIG_RTW88_8822C=m
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CONFIG_RTW88_8723D=m
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CONFIG_RTW88_8821C=m
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CONFIG_RTW88_8822BE=m
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CONFIG_RTW88_8822BU=m
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CONFIG_RTW88_8822CE=m
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CONFIG_RTW88_8822CU=m
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CONFIG_RTW88_8723DE=m
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# CONFIG_RTW88_8723DU is not set
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CONFIG_RTW88_8821CE=m
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CONFIG_RTW88_8821CU=m
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# CONFIG_RTW88_DEBUG is not set
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# CONFIG_RTW88_DEBUGFS is not set
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CONFIG_RTW89=m
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CONFIG_RTW89_CORE=m
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CONFIG_RTW89_PCI=m
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CONFIG_RTW89_8852A=m
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CONFIG_RTW89_8852B=m
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CONFIG_RTW89_8852C=m
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CONFIG_RTW89_8852AE=m
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CONFIG_RTW89_8852BE=m
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CONFIG_RTW89_8852CE=m
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# CONFIG_RTW89_DEBUGMSG is not set
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# CONFIG_RTW89_DEBUGFS is not set
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@ -3929,7 +3954,6 @@ CONFIG_WL18XX=m
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CONFIG_WLCORE=m
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CONFIG_WLCORE_SPI=m
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CONFIG_WLCORE_SDIO=m
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CONFIG_WILINK_PLATFORM_DATA=y
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CONFIG_RTL8723DU=m
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CONFIG_RTL8723DS=m
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CONFIG_RTL8822CS=m
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@ -4151,6 +4175,7 @@ CONFIG_TOUCHSCREEN_CYTTSP_SPI=m
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CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
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CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
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CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m
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# CONFIG_TOUCHSCREEN_CYTTSP5 is not set
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CONFIG_TOUCHSCREEN_DYNAPRO=m
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CONFIG_TOUCHSCREEN_HAMPSHIRE=m
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CONFIG_TOUCHSCREEN_EETI=m
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@ -4161,6 +4186,7 @@ CONFIG_TOUCHSCREEN_FUJITSU=m
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CONFIG_TOUCHSCREEN_GOODIX=m
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CONFIG_TOUCHSCREEN_HIDEEP=m
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CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
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# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
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CONFIG_TOUCHSCREEN_ILI210X=m
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CONFIG_TOUCHSCREEN_ILITEK=m
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CONFIG_TOUCHSCREEN_S6SY761=m
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@ -4232,6 +4258,7 @@ CONFIG_TOUCHSCREEN_COLIBRI_VF50=m
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CONFIG_TOUCHSCREEN_ROHM_BU21023=m
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CONFIG_TOUCHSCREEN_IQS5XX=m
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CONFIG_TOUCHSCREEN_ZINITIX=m
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# CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set
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CONFIG_INPUT_MISC=y
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CONFIG_INPUT_AD714X=m
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CONFIG_INPUT_AD714X_I2C=m
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@ -4328,6 +4355,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
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CONFIG_UNIX98_PTYS=y
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CONFIG_LEGACY_PTYS=y
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CONFIG_LEGACY_PTY_COUNT=16
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CONFIG_LEGACY_TIOCSTI=y
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CONFIG_LDISC_AUTOLOAD=y
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#
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@ -4432,6 +4460,7 @@ CONFIG_IPMI_SI=m
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CONFIG_IPMI_IPMB=m
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# CONFIG_IPMI_WATCHDOG is not set
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# CONFIG_IPMI_POWEROFF is not set
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# CONFIG_SSIF_IPMI_BMC is not set
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# CONFIG_IPMB_DEVICE_INTERFACE is not set
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_TIMERIOMEM=m
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@ -4474,8 +4503,6 @@ CONFIG_TCG_CRB=y
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CONFIG_XILLYBUS_CLASS=m
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# CONFIG_XILLYBUS is not set
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CONFIG_XILLYUSB=m
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CONFIG_RANDOM_TRUST_CPU=y
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# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
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# end of Character devices
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#
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@ -4623,12 +4650,14 @@ CONFIG_SPI_FSL_SPI=m
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CONFIG_SPI_MICROCHIP_CORE=m
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CONFIG_SPI_MICROCHIP_CORE_QSPI=m
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CONFIG_SPI_OC_TINY=m
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# CONFIG_SPI_PCI1XXXX is not set
|
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CONFIG_SPI_PL022=y
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# CONFIG_SPI_PXA2XX is not set
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CONFIG_SPI_ROCKCHIP=y
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CONFIG_SPI_ROCKCHIP_SFC=m
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# CONFIG_SPI_SC18IS602 is not set
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# CONFIG_SPI_SIFIVE is not set
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# CONFIG_SPI_SN_F_OSPI is not set
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CONFIG_SPI_MXIC=m
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CONFIG_SPI_TEGRA210_QUAD=m
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CONFIG_SPI_TEGRA20_SFLASH=y
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@ -4739,6 +4768,7 @@ CONFIG_GPIO_CDEV=y
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CONFIG_GPIO_CDEV_V1=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_MAX730X=m
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CONFIG_GPIO_IDIO_16=m
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#
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# Memory mapped GPIO drivers
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@ -4824,6 +4854,7 @@ CONFIG_GPIO_XRA1403=m
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# Virtual GPIO drivers
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#
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CONFIG_GPIO_AGGREGATOR=m
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# CONFIG_GPIO_LATCH is not set
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||||
CONFIG_GPIO_MOCKUP=m
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CONFIG_GPIO_VIRTIO=m
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# CONFIG_GPIO_SIM is not set
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||||
@ -5278,6 +5309,7 @@ CONFIG_BCMA_DEBUG=y
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_ACT8945A is not set
|
||||
CONFIG_MFD_AS3711=y
|
||||
# CONFIG_MFD_SMPRO is not set
|
||||
CONFIG_MFD_AS3722=m
|
||||
CONFIG_PMIC_ADP5520=y
|
||||
CONFIG_MFD_AAT2870_CORE=y
|
||||
@ -5304,7 +5336,6 @@ CONFIG_MFD_CROS_EC_DEV=y
|
||||
CONFIG_MFD_HI6421_PMIC=y
|
||||
# CONFIG_MFD_HI6421_SPMI is not set
|
||||
# CONFIG_HTC_PASIC3 is not set
|
||||
# CONFIG_HTC_I2CPLD is not set
|
||||
# CONFIG_LPC_ICH is not set
|
||||
CONFIG_LPC_SCH=m
|
||||
CONFIG_MFD_IQS62X=m
|
||||
@ -5366,6 +5397,7 @@ CONFIG_MFD_SYSCON=y
|
||||
# CONFIG_MFD_TI_LP873X is not set
|
||||
# CONFIG_MFD_TI_LP87565 is not set
|
||||
# CONFIG_MFD_TPS65218 is not set
|
||||
# CONFIG_MFD_TPS65219 is not set
|
||||
# CONFIG_MFD_TPS6586X is not set
|
||||
# CONFIG_MFD_TPS65910 is not set
|
||||
# CONFIG_MFD_TPS65912_I2C is not set
|
||||
@ -5484,6 +5516,7 @@ CONFIG_REGULATOR_RT5120=m
|
||||
# CONFIG_REGULATOR_RT5190A is not set
|
||||
CONFIG_REGULATOR_RT5759=m
|
||||
CONFIG_REGULATOR_RT6160=m
|
||||
# CONFIG_REGULATOR_RT6190 is not set
|
||||
CONFIG_REGULATOR_RT6245=m
|
||||
CONFIG_REGULATOR_RTQ2134=m
|
||||
# CONFIG_REGULATOR_RTMV20 is not set
|
||||
@ -5894,7 +5927,6 @@ CONFIG_VIDEO_MUX=m
|
||||
#
|
||||
# Aspeed media platform drivers
|
||||
#
|
||||
CONFIG_VIDEO_ASPEED=m
|
||||
|
||||
#
|
||||
# Atmel media platform drivers
|
||||
@ -5923,6 +5955,10 @@ CONFIG_VIDEO_CAFE_CCIC=m
|
||||
# Mediatek media platform drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Microchip Technology, Inc. media platform drivers
|
||||
#
|
||||
|
||||
#
|
||||
# NVidia media platform drivers
|
||||
#
|
||||
@ -5992,6 +6028,7 @@ CONFIG_VIDEO_VIMC=m
|
||||
CONFIG_VIDEO_VIVID=m
|
||||
CONFIG_VIDEO_VIVID_CEC=y
|
||||
CONFIG_VIDEO_VIVID_MAX_DEVS=64
|
||||
# CONFIG_VIDEO_VISL is not set
|
||||
CONFIG_DVB_TEST_DRIVERS=y
|
||||
CONFIG_DVB_VIDTV=m
|
||||
|
||||
@ -6066,6 +6103,7 @@ CONFIG_VIDEO_NOON010PC30=m
|
||||
# CONFIG_VIDEO_OG01A1B is not set
|
||||
CONFIG_VIDEO_OV02A10=m
|
||||
# CONFIG_VIDEO_OV08D10 is not set
|
||||
# CONFIG_VIDEO_OV08X40 is not set
|
||||
CONFIG_VIDEO_OV13858=m
|
||||
CONFIG_VIDEO_OV13B10=m
|
||||
CONFIG_VIDEO_OV2640=m
|
||||
@ -6073,6 +6111,7 @@ CONFIG_VIDEO_OV2659=m
|
||||
CONFIG_VIDEO_OV2680=m
|
||||
CONFIG_VIDEO_OV2685=m
|
||||
CONFIG_VIDEO_OV2740=m
|
||||
# CONFIG_VIDEO_OV4689 is not set
|
||||
CONFIG_VIDEO_OV5640=m
|
||||
CONFIG_VIDEO_OV5645=m
|
||||
CONFIG_VIDEO_OV5647=m
|
||||
@ -6097,11 +6136,11 @@ CONFIG_VIDEO_RDACM20=m
|
||||
CONFIG_VIDEO_RDACM21=m
|
||||
CONFIG_VIDEO_RJ54N1=m
|
||||
CONFIG_VIDEO_S5C73M3=m
|
||||
CONFIG_VIDEO_S5K4ECGX=m
|
||||
CONFIG_VIDEO_S5K5BAF=m
|
||||
CONFIG_VIDEO_S5K6A3=m
|
||||
CONFIG_VIDEO_S5K6AA=m
|
||||
CONFIG_VIDEO_SR030PC30=m
|
||||
# CONFIG_VIDEO_ST_VGXY61 is not set
|
||||
CONFIG_VIDEO_VS6624=m
|
||||
CONFIG_VIDEO_CCS=m
|
||||
CONFIG_VIDEO_ET8EK8=m
|
||||
@ -6174,6 +6213,7 @@ CONFIG_VIDEO_SAA7110=m
|
||||
CONFIG_VIDEO_SAA711X=m
|
||||
CONFIG_VIDEO_TC358743=m
|
||||
CONFIG_VIDEO_TC358743_CEC=y
|
||||
# CONFIG_VIDEO_TC358746 is not set
|
||||
CONFIG_VIDEO_TVP514X=m
|
||||
CONFIG_VIDEO_TVP5150=m
|
||||
CONFIG_VIDEO_TVP7002=m
|
||||
@ -6458,6 +6498,7 @@ CONFIG_DVB_DUMMY_FE=m
|
||||
# Graphics support
|
||||
#
|
||||
CONFIG_APERTURE_HELPERS=y
|
||||
CONFIG_VIDEO_NOMODESET=y
|
||||
CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y
|
||||
CONFIG_TEGRA_HOST1X=m
|
||||
CONFIG_TEGRA_HOST1X_FIREWALL=y
|
||||
@ -6529,7 +6570,6 @@ CONFIG_ROCKCHIP_LVDS=y
|
||||
CONFIG_ROCKCHIP_RGB=y
|
||||
CONFIG_ROCKCHIP_RK3066_HDMI=y
|
||||
CONFIG_DRM_VMWGFX=m
|
||||
# CONFIG_DRM_VMWGFX_FBCON is not set
|
||||
CONFIG_DRM_UDL=m
|
||||
CONFIG_DRM_AST=m
|
||||
CONFIG_DRM_MGAG200=m
|
||||
@ -6565,6 +6605,7 @@ CONFIG_DRM_PANEL_ILITEK_ILI9341=m
|
||||
CONFIG_DRM_PANEL_ILITEK_ILI9881C=m
|
||||
CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m
|
||||
CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m
|
||||
# CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set
|
||||
CONFIG_DRM_PANEL_JDI_LT070ME05000=m
|
||||
# CONFIG_DRM_PANEL_JDI_R63452 is not set
|
||||
CONFIG_DRM_PANEL_KHADAS_TS050=m
|
||||
@ -6575,6 +6616,7 @@ CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m
|
||||
CONFIG_DRM_PANEL_LG_LB035Q02=m
|
||||
# CONFIG_DRM_PANEL_LG_LG4573 is not set
|
||||
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
|
||||
# CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set
|
||||
CONFIG_DRM_PANEL_NEWVISION_NV3052C=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT35510=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT35560=m
|
||||
@ -6715,7 +6757,6 @@ CONFIG_DRM_LEGACY=y
|
||||
# CONFIG_DRM_SAVAGE is not set
|
||||
CONFIG_DRM_EXPORT_FOR_TESTS=y
|
||||
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m
|
||||
CONFIG_DRM_NOMODESET=y
|
||||
CONFIG_DRM_LIB_RANDOM=y
|
||||
|
||||
#
|
||||
@ -6852,6 +6893,7 @@ CONFIG_LOGO_LINUX_VGA16=y
|
||||
CONFIG_LOGO_LINUX_CLUT224=y
|
||||
# end of Graphics support
|
||||
|
||||
# CONFIG_DRM_ACCEL is not set
|
||||
CONFIG_SOUND=m
|
||||
CONFIG_SND=m
|
||||
CONFIG_SND_TIMER=m
|
||||
@ -7309,6 +7351,7 @@ CONFIG_SND_SOC_RT1305=m
|
||||
CONFIG_SND_SOC_RT1308=m
|
||||
CONFIG_SND_SOC_RT1308_SDW=m
|
||||
CONFIG_SND_SOC_RT1316_SDW=m
|
||||
CONFIG_SND_SOC_RT1318_SDW=m
|
||||
CONFIG_SND_SOC_RT5514=m
|
||||
CONFIG_SND_SOC_RT5514_SPI=m
|
||||
CONFIG_SND_SOC_RT5616=m
|
||||
@ -7705,7 +7748,6 @@ CONFIG_USB_EHCI_TEGRA=m
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=m
|
||||
CONFIG_USB_OXU210HP_HCD=m
|
||||
CONFIG_USB_ISP116X_HCD=m
|
||||
CONFIG_USB_FOTG210_HCD=m
|
||||
CONFIG_USB_MAX3421_HCD=m
|
||||
CONFIG_USB_OHCI_HCD=m
|
||||
CONFIG_USB_OHCI_HCD_PCI=m
|
||||
@ -7767,6 +7809,10 @@ CONFIG_USBIP_VHCI_NR_HCS=1
|
||||
CONFIG_USBIP_HOST=m
|
||||
CONFIG_USBIP_VUDC=m
|
||||
# CONFIG_USBIP_DEBUG is not set
|
||||
|
||||
#
|
||||
# USB dual-mode controller drivers
|
||||
#
|
||||
CONFIG_USB_CDNS_SUPPORT=m
|
||||
CONFIG_USB_CDNS_HOST=y
|
||||
CONFIG_USB_CDNS3=m
|
||||
@ -7946,7 +7992,6 @@ CONFIG_U_SERIAL_CONSOLE=y
|
||||
#
|
||||
# USB Peripheral Controller
|
||||
#
|
||||
CONFIG_USB_FOTG210_UDC=m
|
||||
CONFIG_USB_GR_UDC=m
|
||||
CONFIG_USB_R8A66597=m
|
||||
CONFIG_USB_PXA27X=m
|
||||
@ -8476,9 +8521,10 @@ CONFIG_UIO_NETX=m
|
||||
CONFIG_UIO_PRUSS=m
|
||||
CONFIG_UIO_MF624=m
|
||||
CONFIG_VFIO=m
|
||||
CONFIG_VFIO_CONTAINER=y
|
||||
CONFIG_VFIO_IOMMU_TYPE1=m
|
||||
CONFIG_VFIO_VIRQFD=m
|
||||
# CONFIG_VFIO_NOIOMMU is not set
|
||||
CONFIG_VFIO_VIRQFD=y
|
||||
CONFIG_VFIO_PCI_CORE=m
|
||||
CONFIG_VFIO_PCI_MMAP=y
|
||||
CONFIG_VFIO_PCI_INTX=y
|
||||
@ -8697,6 +8743,7 @@ CONFIG_CROS_EC_DEBUGFS=y
|
||||
CONFIG_CROS_EC_SENSORHUB=y
|
||||
CONFIG_CROS_EC_SYSFS=y
|
||||
CONFIG_CROS_EC_TYPEC=m
|
||||
# CONFIG_CROS_HPS_I2C is not set
|
||||
CONFIG_CROS_USBPD_NOTIFY=y
|
||||
# CONFIG_CHROMEOS_PRIVACY_SCREEN is not set
|
||||
CONFIG_CROS_TYPEC_SWITCH=m
|
||||
@ -8750,6 +8797,7 @@ CONFIG_CLK_RK3328=y
|
||||
CONFIG_CLK_RK3368=y
|
||||
CONFIG_CLK_RK3399=y
|
||||
CONFIG_CLK_RK3568=y
|
||||
CONFIG_CLK_RK3588=y
|
||||
CONFIG_CLK_TEGRA_BPMP=y
|
||||
CONFIG_TEGRA_CLK_DFLL=y
|
||||
CONFIG_XILINX_VCU=m
|
||||
@ -8810,6 +8858,7 @@ CONFIG_IOMMU_DEFAULT_DMA_LAZY=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_IOMMU_DMA=y
|
||||
CONFIG_IOMMU_SVA=y
|
||||
CONFIG_IOMMUFD=m
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_TEGRA_IOMMU_SMMU=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
@ -9006,6 +9055,8 @@ CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m
|
||||
CONFIG_IIO_ST_ACCEL_3AXIS=m
|
||||
CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m
|
||||
CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m
|
||||
# CONFIG_IIO_KX022A_SPI is not set
|
||||
# CONFIG_IIO_KX022A_I2C is not set
|
||||
CONFIG_KXSD9=m
|
||||
CONFIG_KXSD9_SPI=m
|
||||
CONFIG_KXSD9_I2C=m
|
||||
@ -9032,6 +9083,7 @@ CONFIG_STK8BA50=m
|
||||
# Analog to digital converters
|
||||
#
|
||||
CONFIG_AD_SIGMA_DELTA=m
|
||||
# CONFIG_AD4130 is not set
|
||||
CONFIG_AD7091R5=m
|
||||
CONFIG_AD7124=m
|
||||
# CONFIG_AD7192 is not set
|
||||
@ -9069,12 +9121,14 @@ CONFIG_LTC2496=m
|
||||
# CONFIG_MAX11100 is not set
|
||||
# CONFIG_MAX1118 is not set
|
||||
CONFIG_MAX11205=m
|
||||
# CONFIG_MAX11410 is not set
|
||||
# CONFIG_MAX1241 is not set
|
||||
CONFIG_MAX1363=m
|
||||
CONFIG_MAX9611=m
|
||||
CONFIG_MCP320X=m
|
||||
CONFIG_MCP3422=m
|
||||
CONFIG_MCP3911=m
|
||||
# CONFIG_MEDIATEK_MT6370_ADC is not set
|
||||
# CONFIG_MEN_Z188_ADC is not set
|
||||
# CONFIG_NAU7802 is not set
|
||||
# CONFIG_QCOM_SPMI_IADC is not set
|
||||
@ -9106,6 +9160,7 @@ CONFIG_XILINX_XADC=m
|
||||
#
|
||||
# Analog to digital and digital to analog converters
|
||||
#
|
||||
# CONFIG_AD74115 is not set
|
||||
# CONFIG_AD74413R is not set
|
||||
# end of Analog to digital and digital to analog converters
|
||||
|
||||
@ -9254,6 +9309,7 @@ CONFIG_AD9523=m
|
||||
#
|
||||
# CONFIG_ADF4350 is not set
|
||||
CONFIG_ADF4371=m
|
||||
# CONFIG_ADF4377 is not set
|
||||
# CONFIG_ADMV1013 is not set
|
||||
# CONFIG_ADMV1014 is not set
|
||||
# CONFIG_ADMV4420 is not set
|
||||
@ -9550,6 +9606,7 @@ CONFIG_TMP007=m
|
||||
CONFIG_TMP117=m
|
||||
CONFIG_TSYS01=m
|
||||
CONFIG_TSYS02D=m
|
||||
CONFIG_MAX30208=m
|
||||
CONFIG_MAX31856=m
|
||||
CONFIG_MAX31865=m
|
||||
# end of Temperature sensors
|
||||
@ -9644,6 +9701,7 @@ CONFIG_PHY_TEGRA_XUSB=m
|
||||
|
||||
CONFIG_POWERCAP=y
|
||||
# CONFIG_IDLE_INJECT is not set
|
||||
CONFIG_ARM_SCMI_POWERCAP=m
|
||||
# CONFIG_DTPM is not set
|
||||
CONFIG_MCB=m
|
||||
CONFIG_MCB_PCI=m
|
||||
@ -9667,6 +9725,7 @@ CONFIG_ALIBABA_UNCORE_DRW_PMU=m
|
||||
CONFIG_HISI_PMU=y
|
||||
# CONFIG_HISI_PCIE_PMU is not set
|
||||
CONFIG_HNS3_PMU=m
|
||||
CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m
|
||||
# end of Performance monitor support
|
||||
|
||||
CONFIG_RAS=y
|
||||
@ -9685,6 +9744,7 @@ CONFIG_ND_BTT=m
|
||||
CONFIG_BTT=y
|
||||
CONFIG_OF_PMEM=m
|
||||
CONFIG_NVDIMM_KEYS=y
|
||||
# CONFIG_NVDIMM_SECURITY_TEST is not set
|
||||
CONFIG_DAX=y
|
||||
CONFIG_DEV_DAX=m
|
||||
CONFIG_DEV_DAX_HMEM=m
|
||||
@ -9960,9 +10020,11 @@ CONFIG_CRAMFS_MTD=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
|
||||
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set
|
||||
CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set
|
||||
# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_XATTR=y
|
||||
CONFIG_SQUASHFS_ZLIB=y
|
||||
CONFIG_SQUASHFS_LZ4=y
|
||||
@ -10014,27 +10076,6 @@ CONFIG_EROFS_FS_XATTR=y
|
||||
CONFIG_EROFS_FS_POSIX_ACL=y
|
||||
CONFIG_EROFS_FS_SECURITY=y
|
||||
# CONFIG_EROFS_FS_ZIP is not set
|
||||
CONFIG_AUFS_FS=m
|
||||
CONFIG_AUFS_BRANCH_MAX_127=y
|
||||
# CONFIG_AUFS_BRANCH_MAX_511 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
|
||||
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
|
||||
CONFIG_AUFS_SBILIST=y
|
||||
CONFIG_AUFS_HNOTIFY=y
|
||||
CONFIG_AUFS_HFSNOTIFY=y
|
||||
CONFIG_AUFS_EXPORT=y
|
||||
CONFIG_AUFS_INO_T_64=y
|
||||
CONFIG_AUFS_XATTR=y
|
||||
CONFIG_AUFS_FHSM=y
|
||||
CONFIG_AUFS_RDU=y
|
||||
CONFIG_AUFS_DIRREN=y
|
||||
CONFIG_AUFS_SHWH=y
|
||||
CONFIG_AUFS_BR_RAMFS=y
|
||||
CONFIG_AUFS_BR_FUSE=y
|
||||
CONFIG_AUFS_POLL=y
|
||||
CONFIG_AUFS_BR_HFSPLUS=y
|
||||
CONFIG_AUFS_BDEV_LOOP=y
|
||||
# CONFIG_AUFS_DEBUG is not set
|
||||
CONFIG_NETWORK_FILESYSTEMS=y
|
||||
CONFIG_NFS_FS=m
|
||||
CONFIG_NFS_V2=m
|
||||
@ -10057,7 +10098,7 @@ CONFIG_NFS_DEBUG=y
|
||||
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
|
||||
CONFIG_NFS_V4_2_READ_PLUS=y
|
||||
CONFIG_NFSD=m
|
||||
CONFIG_NFSD_V2_ACL=y
|
||||
# CONFIG_NFSD_V2 is not set
|
||||
CONFIG_NFSD_V3_ACL=y
|
||||
CONFIG_NFSD_V4=y
|
||||
CONFIG_NFSD_PNFS=y
|
||||
@ -10211,6 +10252,7 @@ CONFIG_SECURITY_APPARMOR_HASH=y
|
||||
CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y
|
||||
CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y
|
||||
CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y
|
||||
# CONFIG_SECURITY_APPARMOR_KUNIT_TEST is not set
|
||||
# CONFIG_SECURITY_LOADPIN is not set
|
||||
CONFIG_SECURITY_YAMA=y
|
||||
CONFIG_SECURITY_SAFESETID=y
|
||||
@ -10313,7 +10355,6 @@ CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_MANAGER2=y
|
||||
CONFIG_CRYPTO_USER=m
|
||||
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
|
||||
CONFIG_CRYPTO_GF128MUL=y
|
||||
CONFIG_CRYPTO_NULL=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_PCRYPT=m
|
||||
@ -10493,6 +10534,8 @@ CONFIG_CRYPTO_SM4_ARM64_CE=m
|
||||
# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
|
||||
# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
|
||||
# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
|
||||
# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
|
||||
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
|
||||
# end of Accelerated Cryptographic Algorithms for CPU (arm64)
|
||||
|
||||
@ -10512,6 +10555,7 @@ CONFIG_CRYPTO_DEV_NITROX=m
|
||||
CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m
|
||||
CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m
|
||||
CONFIG_CRYPTO_DEV_ROCKCHIP=m
|
||||
# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
|
||||
# CONFIG_CRYPTO_DEV_CHELSIO is not set
|
||||
CONFIG_CRYPTO_DEV_VIRTIO=m
|
||||
CONFIG_CRYPTO_DEV_SAFEXCEL=m
|
||||
@ -10575,6 +10619,7 @@ CONFIG_INDIRECT_PIO=y
|
||||
CONFIG_CRYPTO_LIB_UTILS=y
|
||||
CONFIG_CRYPTO_LIB_AES=y
|
||||
CONFIG_CRYPTO_LIB_ARC4=m
|
||||
CONFIG_CRYPTO_LIB_GF128MUL=y
|
||||
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
|
||||
CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m
|
||||
CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m
|
||||
@ -10655,6 +10700,7 @@ CONFIG_TEXTSEARCH_BM=m
|
||||
CONFIG_TEXTSEARCH_FSM=m
|
||||
CONFIG_BTREE=y
|
||||
CONFIG_INTERVAL_TREE=y
|
||||
CONFIG_INTERVAL_TREE_SPAN_ITER=y
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_ASSOCIATIVE_ARRAY=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
@ -10927,11 +10973,12 @@ CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0
|
||||
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
|
||||
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
|
||||
# CONFIG_LATENCYTOP is not set
|
||||
# CONFIG_DEBUG_CGROUP_REF is not set
|
||||
CONFIG_NOP_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
||||
CONFIG_HAVE_C_RECORDMCOUNT=y
|
||||
@ -11019,7 +11066,6 @@ CONFIG_ASYNC_RAID6_TEST=m
|
||||
# CONFIG_TEST_HEXDUMP is not set
|
||||
# CONFIG_STRING_SELFTEST is not set
|
||||
# CONFIG_TEST_STRING_HELPERS is not set
|
||||
CONFIG_TEST_STRSCPY=m
|
||||
# CONFIG_TEST_KSTRTOX is not set
|
||||
# CONFIG_TEST_PRINTF is not set
|
||||
# CONFIG_TEST_SCANF is not set
|
||||
@ -11028,7 +11074,6 @@ CONFIG_TEST_STRSCPY=m
|
||||
# CONFIG_TEST_XARRAY is not set
|
||||
# CONFIG_TEST_MAPLE_TREE is not set
|
||||
# CONFIG_TEST_RHASHTABLE is not set
|
||||
# CONFIG_TEST_SIPHASH is not set
|
||||
# CONFIG_TEST_IDA is not set
|
||||
# CONFIG_TEST_LKM is not set
|
||||
# CONFIG_TEST_BITOPS is not set
|
||||
@ -11054,6 +11099,8 @@ CONFIG_TEST_BPF=m
|
||||
# CONFIG_OVERFLOW_KUNIT_TEST is not set
|
||||
# CONFIG_STACKINIT_KUNIT_TEST is not set
|
||||
# CONFIG_FORTIFY_KUNIT_TEST is not set
|
||||
# CONFIG_STRSCPY_KUNIT_TEST is not set
|
||||
# CONFIG_SIPHASH_KUNIT_TEST is not set
|
||||
CONFIG_TEST_UDELAY=m
|
||||
# CONFIG_TEST_STATIC_KEYS is not set
|
||||
# CONFIG_TEST_KMOD is not set
|
||||
|
||||
@ -8,7 +8,7 @@ if [[ $BOARD == station-p2 || $BOARD == station-m2 || $BOARD == bananapir2pro ]]
|
||||
BOOTSOURCE='https://github.com/150balbes/u-boot-rk'
|
||||
BOOTBRANCH='branch:rk356x'
|
||||
BOOTPATCHDIR="u-boot-station-p2"
|
||||
elif [[ $BOARD == quartz64a ]]; then
|
||||
elif [[ $BOARD == quartz64a || $BOARD == quartz64b ]]; then
|
||||
BOOTSOURCE='https://github.com/150balbes/u-boot-rk'
|
||||
BOOTBRANCH='branch:rk35xx'
|
||||
BOOTPATCHDIR="u-boot-station-p2"
|
||||
@ -57,14 +57,15 @@ case $BRANCH in
|
||||
;;
|
||||
|
||||
current)
|
||||
KERNELBRANCH="branch:linux-6.0.y"
|
||||
KERNELBRANCH="branch:linux-6.1.y"
|
||||
LINUXCONFIG='linux-media-'$BRANCH
|
||||
KERNELPATCHDIR='media-'$BRANCH
|
||||
LINUXFAMILY=media
|
||||
;;
|
||||
|
||||
edge)
|
||||
KERNELBRANCH="branch:linux-6.1.y"
|
||||
# KERNELBRANCH="branch:linux-6.2.y"
|
||||
KERNELBRANCH="tag:v6.2-rc6"
|
||||
KERNELPATCHDIR='media-'$BRANCH
|
||||
LINUXFAMILY=media
|
||||
LINUXCONFIG='linux-media-'$BRANCH
|
||||
|
||||
@ -6,7 +6,8 @@
|
||||
export DISTRO_GENERIC_KERNEL=${DISTRO_GENERIC_KERNEL:-no} # if yes, does not build our own kernel, instead, uses generic one from distro
|
||||
export UEFI_GRUB_DISABLE_OS_PROBER="${UEFI_GRUB_DISABLE_OS_PROBER:-}" # 'true' will disable os-probing, useful for SD cards.
|
||||
export UEFI_GRUB_DISTRO_NAME="${UEFI_GRUB_DISTRO_NAME:-Armbian}" # Will be used on grub menu display
|
||||
export UEFI_GRUB_TIMEOUT=${UEFI_GRUB_TIMEOUT:-5} # Small timeout by default
|
||||
export UEFI_GRUB_TIMEOUT=${UEFI_GRUB_TIMEOUT:-3} # Small timeout by default
|
||||
export UEFI_GRUB_RECORDFAIL_TIMEOUT=${UEFI_GRUB_RECORDFAIL_TIMEOUT:-3}
|
||||
export GRUB_CMDLINE_LINUX_DEFAULT="${GRUB_CMDLINE_LINUX_DEFAULT:-}" # Cmdline by default
|
||||
export UEFI_ENABLE_BIOS_AMD64="${UEFI_ENABLE_BIOS_AMD64:-no}" # Enable BIOS too if target is amd64
|
||||
# User config overrides.
|
||||
@ -70,7 +71,6 @@ pre_umount_final_image__install_grub() {
|
||||
fi
|
||||
|
||||
umount_chroot "$chroot_target/"
|
||||
|
||||
}
|
||||
|
||||
configure_grub() {
|
||||
@ -84,6 +84,7 @@ configure_grub() {
|
||||
GRUB_CMDLINE_LINUX_DEFAULT="${GRUB_CMDLINE_LINUX_DEFAULT}"
|
||||
GRUB_TIMEOUT_STYLE=menu # Show the menu with Kernel options (Armbian or -generic)...
|
||||
GRUB_TIMEOUT=${UEFI_GRUB_TIMEOUT} # ... for ${UEFI_GRUB_TIMEOUT} seconds, then boot the Armbian default.
|
||||
GRUB_RECORDFAIL_TIMEOUT=${UEFI_GRUB_RECORDFAIL_TIMEOUT}
|
||||
GRUB_DISTRIBUTOR="${UEFI_GRUB_DISTRO_NAME}" # On GRUB menu will show up as "Armbian GNU/Linux" (will show up in some UEFI BIOS boot menu (F8?) as "armbian", not on others)
|
||||
GRUB_BACKGROUND="/boot/grub/grub.png"
|
||||
grubCfgFrag
|
||||
|
||||
@ -2,7 +2,7 @@ new file mode 100644
|
||||
index 000000000..fac2db500
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-firefly-roc-pc.dts
|
||||
@@ -0,0 +1,784 @@
|
||||
@@ -0,0 +1,773 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
@ -78,61 +78,62 @@ index 000000000..fac2db500
|
||||
+ vin-supply = <&vcc5v0_in>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb30_host: vcc5v0_usb30_host {
|
||||
+ vcc5v0_host: vcc5v0-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb30_host";
|
||||
+ regulator-name = "vcc5v0_host";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
|
||||
+ pinctrl-0 = <&vcc5v0_host_en>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: vcc5v0_usb_otg {
|
||||
+ vcc5v0_otg: vcc5v0-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-name = "vcc5v0_otg";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
|
||||
+ pinctrl-0 = <&vcc5v0_otg_en>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30_3v3: gpio-regulator {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ regulator-name = "pcie30_3v3";
|
||||
+ regulator-min-microvolt = <100000>;
|
||||
+ vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_enable_h>;
|
||||
+ regulator-name = "vcc3v3_pcie_p";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ gpios-states = <0x1>;
|
||||
+ states = <100000 0x0
|
||||
+ 3300000 0x1>;
|
||||
+ vin-supply = <&vcc_3v3>;
|
||||
+ };
|
||||
+
|
||||
+ firefly_leds: leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ power_led: power {
|
||||
+ label = "firefly:blue:power";
|
||||
+ linux,default-trigger = "ir-power-click";
|
||||
+ default-state = "on";
|
||||
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&led_power>;
|
||||
+ };
|
||||
+ label = "firefly:blue:power";
|
||||
+ linux,default-trigger = "ir-power-click";
|
||||
+ default-state = "on";
|
||||
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&led_power>;
|
||||
+ };
|
||||
+
|
||||
+ user_led: user {
|
||||
+ label = "firefly:yellow:user";
|
||||
+ linux,default-trigger = "ir-user-click";
|
||||
+ default-state = "off";
|
||||
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&led_user>;
|
||||
+ user_led: user {
|
||||
+ label = "firefly:yellow:user";
|
||||
+ linux,default-trigger = "ir-user-click";
|
||||
+ default-state = "off";
|
||||
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&led_user>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
@ -234,7 +235,6 @@ index 000000000..fac2db500
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint@0 {
|
||||
+// reg = <0>;
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
@ -533,16 +533,11 @@ index 000000000..fac2db500
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_reset_gpio>;
|
||||
+ vpcie3v3-supply = <&pcie30_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie30_3v3 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_reset_h>;
|
||||
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie_p>;
|
||||
+ status = "okay";
|
||||
+ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
@ -554,15 +549,15 @@ index 000000000..fac2db500
|
||||
+
|
||||
+ bt {
|
||||
+ bt_enable_h: bt-enable-h {
|
||||
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_host_wake_l: bt-host-wake-l {
|
||||
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ bt_wake_l: bt-wake-l {
|
||||
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
@ -574,19 +569,21 @@ index 000000000..fac2db500
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
|
||||
+ vcc5v0_host_en: vcc5v0-host-en {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
|
||||
+ vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+
|
||||
+
|
||||
+ pcie {
|
||||
+ pcie_reset_gpio: pcie-reset-gpio {
|
||||
+ pcie_enable_h: pcie-enable-h {
|
||||
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ pcie_reset_h: pcie-reset-h {
|
||||
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
@ -680,14 +677,14 @@ index 000000000..fac2db500
|
||||
+};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_xfer>;
|
||||
+// pinctrl-names = "default";
|
||||
+// pinctrl-0 = <&uart0_xfer>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
|
||||
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
|
||||
+ status = "okay";
|
||||
+ uart-has-rtscts;
|
||||
+
|
||||
@ -739,12 +736,12 @@ index 000000000..fac2db500
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_usb30_host>;
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ vbus-supply = <&vcc5v0_usb_otg>;
|
||||
+ vbus-supply = <&vcc5v0_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
@ -753,23 +750,15 @@ index 000000000..fac2db500
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_usb30_host>;
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_otg {
|
||||
+ phy-supply = <&vcc5v0_usb30_host>;
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+//&usbdrd30 {
|
||||
+// status = "okay";
|
||||
+//};
|
||||
+
|
||||
+//&usbhost30 {
|
||||
+// status = "okay";
|
||||
+//};
|
||||
+
|
||||
+&vop {
|
||||
+ compatible = "rockchip,rk3568-vop";
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
@ -56,39 +56,39 @@
|
||||
&combphy2 {
|
||||
/* used for SATA */
|
||||
status = "okay";
|
||||
+};
|
||||
+//};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+//&cpu0 {
|
||||
+// cpu-supply = <&vdd_cpu>;
|
||||
+//};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+//&cpu1 {
|
||||
+// cpu-supply = <&vdd_cpu>;
|
||||
+//};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+//&cpu2 {
|
||||
+// cpu-supply = <&vdd_cpu>;
|
||||
+//};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+//&cpu3 {
|
||||
+// cpu-supply = <&vdd_cpu>;
|
||||
+//};
|
||||
+
|
||||
+&cpu_thermal {
|
||||
+ trips {
|
||||
+ cpu_hot: cpu_hot {
|
||||
+ temperature = <55000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "active";
|
||||
+ };
|
||||
+ };
|
||||
+//&cpu_thermal {
|
||||
+// trips {
|
||||
+// cpu_hot: cpu_hot {
|
||||
+// temperature = <55000>;
|
||||
+// hysteresis = <2000>;
|
||||
+// type = "active";
|
||||
+// };
|
||||
+// };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map1 {
|
||||
+ trip = <&cpu_hot>;
|
||||
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+// cooling-maps {
|
||||
+// map1 {
|
||||
+// trip = <&cpu_hot>;
|
||||
+// cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+// };
|
||||
+// };
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
@ -97,23 +97,23 @@
|
||||
status = "okay";
|
||||
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ regulator-compatible = "fan53555-reg";
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1390000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-always-on;
|
||||
+// vdd_cpu: regulator@1c {
|
||||
+// compatible = "tcs,tcs4525";
|
||||
+// reg = <0x1c>;
|
||||
+// vin-supply = <&vcc5v0_sys>;
|
||||
+// regulator-compatible = "fan53555-reg";
|
||||
+// regulator-name = "vdd_cpu";
|
||||
+// regulator-min-microvolt = <712500>;
|
||||
+// regulator-max-microvolt = <1390000>;
|
||||
+// regulator-ramp-delay = <2300>;
|
||||
+// fcs,suspend-voltage-selector = <1>;
|
||||
+// regulator-boot-on;
|
||||
+// regulator-always-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+// regulator-state-mem {
|
||||
+// regulator-off-in-suspend;
|
||||
+// };
|
||||
+// };
|
||||
+
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
File diff suppressed because it is too large
Load Diff
@ -2,7 +2,7 @@ new file mode 100644
|
||||
index 000000000..fac2db500
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts
|
||||
@@ -0,0 +1,1000 @@
|
||||
@@ -0,0 +1,1044 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
@ -180,6 +180,24 @@ index 000000000..fac2db500
|
||||
+ regulator-name = "vcc5v0_otg";
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_lcd0_n: vcc3v3-lcd0-n {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_lcd0_n";
|
||||
+ regulator-boot-on;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_lcd1_n: vcc3v3-lcd1-n {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_lcd1_n";
|
||||
+ regulator-boot-on;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_hub_power: vcc-hub-power-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
@ -210,8 +228,17 @@ index 000000000..fac2db500
|
||||
+ regulator-always-on;
|
||||
+ };
|
||||
+
|
||||
+ vcc_4g_power: vcc-4g-power-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc_4g_power_en>;
|
||||
+ regulator-name = "vcc_4g_power_en";
|
||||
+ regulator-always-on;
|
||||
+ };
|
||||
+
|
||||
+ firefly_leds: leds {
|
||||
+// status = "okay";
|
||||
+ compatible = "gpio-leds";
|
||||
+ power_led: power {
|
||||
+ label = "firefly:blue:power";
|
||||
@ -242,30 +269,30 @@ index 000000000..fac2db500
|
||||
+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+// wireless_wlan: wireless-wlan {
|
||||
+// compatible = "wlan-platdata";
|
||||
+// rockchip,grf = <&grf>;
|
||||
+// wifi_chip_type = "ap6398s";
|
||||
+// pinctrl-names = "default";
|
||||
+// pinctrl-0 = <&wifi_host_wake_irq>;
|
||||
+// WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+// status = "disabled";
|
||||
+// };
|
||||
+ wireless_wlan: wireless-wlan {
|
||||
+ compatible = "wlan-platdata";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ wifi_chip_type = "ap6398s";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_host_wake_irq>;
|
||||
+ WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+// wireless_bluetooth: wireless-bluetooth {
|
||||
+// compatible = "bluetooth-platdata";
|
||||
+// clocks = <&rk809 1>;
|
||||
+// clock-names = "ext_clock";
|
||||
+// //wifi-bt-power-toggle;
|
||||
+// uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
+// pinctrl-names = "default", "rts_gpio";
|
||||
+// pinctrl-0 = <&uart8m0_rtsn>;
|
||||
+// pinctrl-1 = <&uart8_gpios>;
|
||||
+// BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+// BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
|
||||
+// BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+// status = "disabled";
|
||||
+// };
|
||||
+ wireless_bluetooth: wireless-bluetooth {
|
||||
+ compatible = "bluetooth-platdata";
|
||||
+ clocks = <&rk809 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ //wifi-bt-power-toggle;
|
||||
+ uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-names = "default", "rts_gpio";
|
||||
+ pinctrl-0 = <&uart8m0_rtsn>;
|
||||
+ pinctrl-1 = <&uart8_gpios>;
|
||||
+ BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
|
||||
+ BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ flash_led: flash-led {
|
||||
+ compatible = "led,rgb13h";
|
||||
@ -279,18 +306,6 @@ index 000000000..fac2db500
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+// vcc3v3_pcie: vcc3v3_pcie {
|
||||
+// compatible = "regulator-fixed";
|
||||
+// regulator-name = "vcc3v3_pcie";
|
||||
+// enable-active-high;
|
||||
+// gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+// pinctrl-names = "default";
|
||||
+// pinctrl-0 = <&vcc3v3_pcie_en_h>;
|
||||
+// regulator-min-microvolt = <3300000>;
|
||||
+// regulator-max-microvolt = <3300000>;
|
||||
+// vin-supply = <&vcc_3v3>;
|
||||
+// };
|
||||
+
|
||||
+ rk809-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
@ -407,7 +422,6 @@ index 000000000..fac2db500
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint@0 {
|
||||
+// reg = <0>;
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
@ -698,6 +712,18 @@ index 000000000..fac2db500
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c5 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s0_8ch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -726,16 +752,16 @@ index 000000000..fac2db500
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+//&pcie30phy {
|
||||
+// status = "okay";
|
||||
+//};
|
||||
+&pcie30phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+//&pcie3x2 {
|
||||
+// reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+// vpcie3v3-supply = <&pcie30_3v3>;
|
||||
+&pcie3x2 {
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&pcie30_3v3>;
|
||||
+
|
||||
+// status = "okay";
|
||||
+//};
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gic {
|
||||
+ status = "okay";
|
||||
@ -752,17 +778,17 @@ index 000000000..fac2db500
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+// wireless-wlan {
|
||||
+// wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
+// rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+// };
|
||||
+// };
|
||||
+ wireless-wlan {
|
||||
+ wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+// wireless-bluetooth {
|
||||
+// uart8_gpios: uart8-gpios {
|
||||
+// rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+// };
|
||||
+// };
|
||||
+ wireless-bluetooth {
|
||||
+ uart8_gpios: uart8-gpios {
|
||||
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic_int {
|
||||
@ -803,6 +829,12 @@ index 000000000..fac2db500
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ 4g {
|
||||
+ vcc_4g_power_en: vcc-4g-power-en {
|
||||
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ led_power: led-power {
|
||||
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
@ -860,15 +892,9 @@ index 000000000..fac2db500
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+//&sdio_pwrseq {
|
||||
+// status = "okay";
|
||||
+// reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
||||
+// post-power-on-delay-ms = <100>;
|
||||
+//};
|
||||
+
|
||||
+&sdmmc2 {
|
||||
+// max-frequency = <150000000>;
|
||||
+ max-frequency = <100000000>;
|
||||
+ max-frequency = <150000000>;
|
||||
+// max-frequency = <100000000>;
|
||||
+ supports-sdio;
|
||||
+ bus-width = <4>;
|
||||
+ disable-wp;
|
||||
@ -883,14 +909,20 @@ index 000000000..fac2db500
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+//&wireless_wlan {
|
||||
+// wifi_chip_type = "ap6275s";
|
||||
+// status = "okay";
|
||||
+//};
|
||||
+&sdio_pwrseq {
|
||||
+ status = "okay";
|
||||
+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
||||
+ post-power-on-delay-ms = <100>;
|
||||
+};
|
||||
+
|
||||
+//&wireless_bluetooth {
|
||||
+// status = "okay";
|
||||
+//};
|
||||
+&wireless_wlan {
|
||||
+ wifi_chip_type = "ap6275s";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&wireless_bluetooth {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
@ -903,15 +935,21 @@ index 000000000..fac2db500
|
||||
+};
|
||||
+
|
||||
+&uart3 {
|
||||
+// status = "disabled";
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart4 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart4m1_xfer>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart8 {
|
||||
+ status = "okay";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
@ -975,6 +1013,12 @@ index 000000000..fac2db500
|
||||
+// status = "okay";
|
||||
+//};
|
||||
+
|
||||
+&rk809 {
|
||||
+ rtc {
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm4 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -135,7 +135,7 @@ Subject: [PATCH] media: v4l2: Add NV15 and NV20 pixel formats
|
||||
Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for
|
||||
10-bit buffers.
|
||||
|
||||
NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/CbCr format
|
||||
NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/UV format
|
||||
similar to P010 and P210 but has no padding between components. Instead,
|
||||
luminance and chrominance samples are grouped into 4s so that each group is
|
||||
packed into an integer number of bytes:
|
||||
@ -172,28 +172,28 @@ index e6fd355a2e92..24771edaa4f2 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
|
||||
case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break;
|
||||
case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break;
|
||||
case V4L2_PIX_FMT_P010: descr = "10-bit Y/CbCr 4:2:0"; break;
|
||||
+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break;
|
||||
+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/CbCr 4:2:2 (Packed)"; break;
|
||||
case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
|
||||
case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break;
|
||||
case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break;
|
||||
+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
|
||||
+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/UV 4:2:2 (Packed)"; break;
|
||||
case V4L2_PIX_FMT_NV12_4L4: descr = "Y/UV 4:2:0 (4x4 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV12_16L16: descr = "Y/UV 4:2:0 (16x16 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV12_32L32: descr = "Y/UV 4:2:0 (32x32 Linear)"; break;
|
||||
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
|
||||
index 01e630f2ec78..cea44992aea3 100644
|
||||
--- a/include/uapi/linux/videodev2.h
|
||||
+++ b/include/uapi/linux/videodev2.h
|
||||
@@ -628,6 +628,9 @@ struct v4l2_pix_format {
|
||||
#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
|
||||
#define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */
|
||||
#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/VU 4:4:4 */
|
||||
#define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/UV 4:2:0 10-bit per component */
|
||||
|
||||
+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
|
||||
+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */
|
||||
+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/UV 4:2:0 10-bit packed */
|
||||
+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/UV 4:2:2 10-bit packed */
|
||||
+
|
||||
/* two non contiguous planes - one Y, one Cr + Cb interleaved */
|
||||
#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */
|
||||
#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */
|
||||
#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/UV 4:2:0 */
|
||||
#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/VU 4:2:0 */
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
@ -2112,6 +2112,69 @@ index a2d101ebf7a7..7f6ffbc3e7b2 100644
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -2732,40 +2744,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
|
||||
*/
|
||||
|
||||
/* Default 8bit RGB fallback */
|
||||
- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24))
|
||||
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
|
||||
if (max_bpc >= 16 && info->bpc == 16) {
|
||||
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
|
||||
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
|
||||
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV16_1X48))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
|
||||
|
||||
- output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
|
||||
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB161616_1X48))
|
||||
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
|
||||
}
|
||||
|
||||
if (max_bpc >= 12 && info->bpc >= 12) {
|
||||
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
|
||||
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
|
||||
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY12_1X24))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
|
||||
|
||||
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
|
||||
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
|
||||
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV12_1X36))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
|
||||
|
||||
- output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
|
||||
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB121212_1X36))
|
||||
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
|
||||
}
|
||||
|
||||
if (max_bpc >= 10 && info->bpc >= 10) {
|
||||
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
|
||||
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
|
||||
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY10_1X20))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
|
||||
|
||||
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
|
||||
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
|
||||
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV10_1X30))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
|
||||
|
||||
- output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
|
||||
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB101010_1X30))
|
||||
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
|
||||
}
|
||||
|
||||
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
|
||||
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR422) &&
|
||||
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY8_1X16))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
|
||||
|
||||
- if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
|
||||
+ if ((info->color_formats & DRM_COLOR_FORMAT_YCBCR444) &&
|
||||
+ is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
|
||||
|
||||
*num_output_fmts = i;
|
||||
|
||||
@@ -2946,11 +2969,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
|
||||
struct dw_hdmi *hdmi = bridge->driver_private;
|
||||
const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
|
||||
@ -414,13 +414,13 @@ Required to proper decode H.264@4K
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 +++++++++++---
|
||||
drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 14 +++++++++++---
|
||||
1 file changed, 11 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
|
||||
index 8de6fd2e8eef..002b1a600f93 100644
|
||||
--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
--- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
|
||||
+++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c
|
||||
@@ -15,7 +15,8 @@
|
||||
#include "rockchip_vpu2_regs.h"
|
||||
|
||||
@ -58,38 +58,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
@@ -190,6 +234,31 @@
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
+ };
|
||||
+
|
||||
+ wireless-wlan {
|
||||
+ compatible = "wlan-platdata";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ wifi_chip_type = "ap6359sa";
|
||||
+ sdio_vref = <1800>;
|
||||
+ WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ wireless-bluetooth {
|
||||
+ compatible = "bluetooth-platdata";
|
||||
+ clocks = <&rk808 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-names = "default", "rts_gpio";
|
||||
+ pinctrl-0 = <&uart0_rts>;
|
||||
+ pinctrl-1 = <&uart0_gpios>;
|
||||
+ // wifi-bt-power-toggle;
|
||||
+ // BT,power_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
+ BT,wake_gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
+ BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -453,10 +522,19 @@
|
||||
};
|
||||
|
||||
@ -105,8 +73,8 @@
|
||||
+ reg = <0x1a>;
|
||||
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
|
||||
+ clock-names = "mclk";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
+ //pinctrl-names = "default";
|
||||
+ //pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
+ };
|
||||
};
|
||||
|
||||
@ -187,26 +155,6 @@
|
||||
pmic {
|
||||
cpu_b_sleep: cpu-b-sleep {
|
||||
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
@@ -581,6 +713,19 @@
|
||||
|
||||
sdmmc0_pwr_h: sdmmc0-pwr-h {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wireless-wlan {
|
||||
+ wifi_pwr: wifi-pwr {
|
||||
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wireless-bluetooth {
|
||||
+ uart0_gpios: uart0-gpios {
|
||||
+ rockchip,pins =
|
||||
+ <2 RK_PC3 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -747,11 +892,3 @@
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
@ -219,4 +167,3 @@
|
||||
-&vopl_mmu {
|
||||
- status = "okay";
|
||||
-};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,790 @@
|
||||
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
|
||||
index 42a7ab542..822999710 100644
|
||||
--- a/drivers/gpu/drm/panel/Makefile
|
||||
+++ b/drivers/gpu/drm/panel/Makefile
|
||||
@@ -8,6 +8,7 @@ obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
|
||||
obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
|
||||
obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
|
||||
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
|
||||
+obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple-dsi.o
|
||||
obj-$(CONFIG_DRM_PANEL_EDP) += panel-edp.o
|
||||
obj-$(CONFIG_DRM_PANEL_ELIDA_KD35T133) += panel-elida-kd35t133.o
|
||||
obj-$(CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02) += panel-feixin-k101-im2ba02.o
|
||||
diff --git a/drivers/gpu/drm/panel/panel-simple-dsi.c b/drivers/gpu/drm/panel/panel-simple-dsi.c
|
||||
new file mode 100644
|
||||
index 000000000..906d40ebe
|
||||
--- /dev/null
|
||||
+++ b/drivers/gpu/drm/panel/panel-simple-dsi.c
|
||||
@@ -0,0 +1,772 @@
|
||||
+/*
|
||||
+ * Copyright (C) 2021
|
||||
+ * This simple dsi driver porting from rock-chip panel-simple.c on linux-4.4
|
||||
+ */
|
||||
+
|
||||
+#include <linux/backlight.h>
|
||||
+#include <linux/gpio/consumer.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/regulator/consumer.h>
|
||||
+
|
||||
+#include <drm/drm_crtc.h>
|
||||
+#include <drm/drm_mipi_dsi.h>
|
||||
+#include <drm/drm_panel.h>
|
||||
+
|
||||
+#include <video/display_timing.h>
|
||||
+#include <video/mipi_display.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <video/of_display_timing.h>
|
||||
+#include <linux/of_graph.h>
|
||||
+#include <video/videomode.h>
|
||||
+#include <linux/delay.h>
|
||||
+
|
||||
+struct cmd_ctrl_hdr {
|
||||
+ u8 dtype; /* data type */
|
||||
+ u8 wait; /* ms */
|
||||
+ u8 dlen; /* payload len */
|
||||
+} __packed;
|
||||
+
|
||||
+struct cmd_desc {
|
||||
+ struct cmd_ctrl_hdr dchdr;
|
||||
+ u8 *payload;
|
||||
+};
|
||||
+
|
||||
+struct panel_cmds {
|
||||
+ u8 *buf;
|
||||
+ int blen;
|
||||
+ struct cmd_desc *cmds;
|
||||
+ int cmd_cnt;
|
||||
+};
|
||||
+
|
||||
+struct panel_desc {
|
||||
+ const struct drm_display_mode *modes;
|
||||
+ unsigned int num_modes;
|
||||
+ const struct display_timing *timings;
|
||||
+ unsigned int num_timings;
|
||||
+
|
||||
+ unsigned int bpc;
|
||||
+
|
||||
+ struct {
|
||||
+ unsigned int width;
|
||||
+ unsigned int height;
|
||||
+ } size;
|
||||
+
|
||||
+ /**
|
||||
+ * @reset: the time (in milliseconds) indicates the delay time
|
||||
+ * after the panel to operate reset gpio
|
||||
+ * @init: the time (in milliseconds) that it takes for the panel to
|
||||
+ * power on and dsi host can send command to panel
|
||||
+ * @prepare: the time (in milliseconds) that it takes for the panel to
|
||||
+ * become ready and start receiving video data
|
||||
+ * @enable: the time (in milliseconds) that it takes for the panel to
|
||||
+ * display the first valid frame after starting to receive
|
||||
+ * video data
|
||||
+ * @disable: the time (in milliseconds) that it takes for the panel to
|
||||
+ * turn the display off (no content is visible)
|
||||
+ * @unprepare: the time (in milliseconds) that it takes for the panel
|
||||
+ * to power itself down completely
|
||||
+ */
|
||||
+ struct {
|
||||
+ unsigned int reset;
|
||||
+ unsigned int init;
|
||||
+ unsigned int prepare;
|
||||
+ unsigned int enable;
|
||||
+ unsigned int disable;
|
||||
+ unsigned int unprepare;
|
||||
+ } delay;
|
||||
+
|
||||
+ u32 bus_format;
|
||||
+};
|
||||
+
|
||||
+struct panel_simple {
|
||||
+ struct drm_panel base;
|
||||
+ struct mipi_dsi_device *dsi;
|
||||
+ bool prepared;
|
||||
+ bool enabled;
|
||||
+ bool power_invert;
|
||||
+
|
||||
+ struct device *dev;
|
||||
+ const struct panel_desc *desc;
|
||||
+
|
||||
+ struct regulator *supply;
|
||||
+
|
||||
+ struct gpio_desc *enable_gpio;
|
||||
+ struct gpio_desc *reset_gpio;
|
||||
+ int cmd_type;
|
||||
+
|
||||
+ struct panel_cmds *on_cmds;
|
||||
+ struct panel_cmds *off_cmds;
|
||||
+ struct device_node *np_crtc;
|
||||
+
|
||||
+ int reset_level;
|
||||
+ enum drm_panel_orientation orientation;
|
||||
+};
|
||||
+
|
||||
+enum rockchip_cmd_type {
|
||||
+ CMD_TYPE_DEFAULT,
|
||||
+ CMD_TYPE_SPI,
|
||||
+ CMD_TYPE_MCU
|
||||
+};
|
||||
+
|
||||
+static void panel_simple_sleep(unsigned int msec)
|
||||
+{
|
||||
+ if (msec > 20)
|
||||
+ msleep(msec);
|
||||
+ else
|
||||
+ usleep_range(msec * 1000, (msec + 1) * 1000);
|
||||
+}
|
||||
+
|
||||
+static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
|
||||
+{
|
||||
+ return container_of(panel, struct panel_simple, base);
|
||||
+}
|
||||
+
|
||||
+static void panel_simple_cmds_cleanup(struct panel_simple *p)
|
||||
+{
|
||||
+ if (p->on_cmds) {
|
||||
+ kfree(p->on_cmds->buf);
|
||||
+ kfree(p->on_cmds->cmds);
|
||||
+ }
|
||||
+
|
||||
+ if (p->off_cmds) {
|
||||
+ kfree(p->off_cmds->buf);
|
||||
+ kfree(p->off_cmds->cmds);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_parse_cmds(struct device *dev,
|
||||
+ const u8 *data, int blen,
|
||||
+ struct panel_cmds *pcmds)
|
||||
+{
|
||||
+ unsigned int len;
|
||||
+ char *buf, *bp;
|
||||
+ struct cmd_ctrl_hdr *dchdr;
|
||||
+ int i, cnt;
|
||||
+
|
||||
+ if (!pcmds)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ buf = kmemdup(data, blen, GFP_KERNEL);
|
||||
+ if (!buf)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ /* scan init commands */
|
||||
+ bp = buf;
|
||||
+ len = blen;
|
||||
+ cnt = 0;
|
||||
+ while (len > sizeof(*dchdr)) {
|
||||
+ dchdr = (struct cmd_ctrl_hdr *)bp;
|
||||
+
|
||||
+ if (dchdr->dlen > len) {
|
||||
+ dev_err(dev, "%s: error, len=%d", __func__,
|
||||
+ dchdr->dlen);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ bp += sizeof(*dchdr);
|
||||
+ len -= sizeof(*dchdr);
|
||||
+ bp += dchdr->dlen;
|
||||
+ len -= dchdr->dlen;
|
||||
+ cnt++;
|
||||
+ }
|
||||
+
|
||||
+ if (len != 0) {
|
||||
+ dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
|
||||
+ __func__, buf[0], blen);
|
||||
+ kfree(buf);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ pcmds->cmds = kcalloc(cnt, sizeof(struct cmd_desc), GFP_KERNEL);
|
||||
+ if (!pcmds->cmds) {
|
||||
+ kfree(buf);
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ pcmds->cmd_cnt = cnt;
|
||||
+ pcmds->buf = buf;
|
||||
+ pcmds->blen = blen;
|
||||
+
|
||||
+ bp = buf;
|
||||
+ len = blen;
|
||||
+ for (i = 0; i < cnt; i++) {
|
||||
+ dchdr = (struct cmd_ctrl_hdr *)bp;
|
||||
+ len -= sizeof(*dchdr);
|
||||
+ bp += sizeof(*dchdr);
|
||||
+ pcmds->cmds[i].dchdr = *dchdr;
|
||||
+ pcmds->cmds[i].payload = bp;
|
||||
+ bp += dchdr->dlen;
|
||||
+ len -= dchdr->dlen;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
|
||||
+ struct panel_cmds *cmds)
|
||||
+{
|
||||
+ struct mipi_dsi_device *dsi = panel->dsi;
|
||||
+ int i, err;
|
||||
+
|
||||
+ if (!cmds)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ for (i = 0; i < cmds->cmd_cnt; i++) {
|
||||
+ struct cmd_desc *cmd = &cmds->cmds[i];
|
||||
+
|
||||
+ switch (cmd->dchdr.dtype) {
|
||||
+ case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
|
||||
+ case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
|
||||
+ case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
|
||||
+ case MIPI_DSI_GENERIC_LONG_WRITE:
|
||||
+ err = mipi_dsi_generic_write(dsi, cmd->payload,
|
||||
+ cmd->dchdr.dlen);
|
||||
+ break;
|
||||
+ case MIPI_DSI_DCS_SHORT_WRITE:
|
||||
+ case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
|
||||
+ case MIPI_DSI_DCS_LONG_WRITE:
|
||||
+ err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
|
||||
+ cmd->dchdr.dlen);
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (err < 0)
|
||||
+ dev_err(panel->dev, "failed to write dcs cmd: %d\n",
|
||||
+ err);
|
||||
+
|
||||
+ if (cmd->dchdr.wait)
|
||||
+ panel_simple_sleep(cmd->dchdr.wait);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_get_cmds(struct panel_simple *panel)
|
||||
+{
|
||||
+ const void *data;
|
||||
+ int len;
|
||||
+ int err;
|
||||
+
|
||||
+ data = of_get_property(panel->dev->of_node, "panel-init-sequence",
|
||||
+ &len);
|
||||
+ if (data) {
|
||||
+ panel->on_cmds = devm_kzalloc(panel->dev,
|
||||
+ sizeof(*panel->on_cmds),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!panel->on_cmds)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ err = panel_simple_parse_cmds(panel->dev, data, len,
|
||||
+ panel->on_cmds);
|
||||
+ if (err) {
|
||||
+ dev_err(panel->dev, "failed to parse panel init sequence\n");
|
||||
+ return err;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ data = of_get_property(panel->dev->of_node, "panel-exit-sequence",
|
||||
+ &len);
|
||||
+ if (data) {
|
||||
+ panel->off_cmds = devm_kzalloc(panel->dev,
|
||||
+ sizeof(*panel->off_cmds),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!panel->off_cmds)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ err = panel_simple_parse_cmds(panel->dev, data, len,
|
||||
+ panel->off_cmds);
|
||||
+ if (err) {
|
||||
+ dev_err(panel->dev, "failed to parse panel exit sequence\n");
|
||||
+ return err;
|
||||
+ }
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_get_modes(struct drm_panel *panel,struct drm_connector *connector)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+ struct drm_device *drm = connector->dev;
|
||||
+ struct drm_display_mode *mode;
|
||||
+ struct device_node *timings_np;
|
||||
+ int ret;
|
||||
+
|
||||
+ timings_np = of_get_child_by_name(panel->dev->of_node,
|
||||
+ "display-timings");
|
||||
+ if (!timings_np) {
|
||||
+ dev_dbg(panel->dev, "failed to find display-timings node\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ of_node_put(timings_np);
|
||||
+ mode = drm_mode_create(drm);
|
||||
+ if (!mode)
|
||||
+ return 0;
|
||||
+
|
||||
+ ret = of_get_drm_display_mode(panel->dev->of_node, mode, p->desc->bus_format,
|
||||
+ OF_USE_NATIVE_MODE);
|
||||
+ if (ret) {
|
||||
+ dev_dbg(panel->dev, "failed to find dts display timings\n");
|
||||
+ drm_mode_destroy(drm, mode);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ drm_mode_set_name(mode);
|
||||
+ mode->type |= DRM_MODE_TYPE_PREFERRED;
|
||||
+
|
||||
+ connector->display_info.width_mm = mode->width_mm;
|
||||
+ connector->display_info.height_mm = mode->height_mm;
|
||||
+
|
||||
+ drm_mode_probed_add(connector, mode);
|
||||
+
|
||||
+ /*
|
||||
+ * TODO: Remove once all drm drivers call
|
||||
+ * drm_connector_set_orientation_from_panel()
|
||||
+ */
|
||||
+ drm_connector_set_panel_orientation(connector, p->orientation);
|
||||
+
|
||||
+ return 1;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_regulator_enable(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+ int err = 0;
|
||||
+
|
||||
+ if (p->power_invert) {
|
||||
+ if (regulator_is_enabled(p->supply) > 0)
|
||||
+ regulator_disable(p->supply);
|
||||
+ } else {
|
||||
+ err = regulator_enable(p->supply);
|
||||
+ if (err < 0) {
|
||||
+ dev_err(panel->dev, "failed to enable supply: %d\n",
|
||||
+ err);
|
||||
+ return err;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_regulator_disable(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+ int err = 0;
|
||||
+
|
||||
+ if (p->power_invert) {
|
||||
+ if (!regulator_is_enabled(p->supply)) {
|
||||
+ err = regulator_enable(p->supply);
|
||||
+ if (err < 0) {
|
||||
+ dev_err(panel->dev, "failed to enable supply: %d\n",
|
||||
+ err);
|
||||
+ return err;
|
||||
+ }
|
||||
+ }
|
||||
+ } else {
|
||||
+ regulator_disable(p->supply);
|
||||
+ }
|
||||
+
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_disable(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+ int err = 0;
|
||||
+
|
||||
+ if (!p->enabled)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (p->desc && p->desc->delay.disable)
|
||||
+ panel_simple_sleep(p->desc->delay.disable);
|
||||
+
|
||||
+ p->enabled = false;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_unprepare(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+ int err = 0;
|
||||
+
|
||||
+ if (!p->prepared)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (p->off_cmds) {
|
||||
+ if (p->dsi)
|
||||
+ err = panel_simple_dsi_send_cmds(p, p->off_cmds);
|
||||
+ if (err)
|
||||
+ dev_err(p->dev, "failed to send off cmds\n");
|
||||
+ }
|
||||
+
|
||||
+ if (p->reset_gpio)
|
||||
+ gpiod_direction_output(p->reset_gpio, !p->reset_level);
|
||||
+
|
||||
+ if (p->enable_gpio)
|
||||
+ gpiod_direction_output(p->enable_gpio, 0);
|
||||
+
|
||||
+ panel_simple_regulator_disable(panel);
|
||||
+
|
||||
+ if (p->desc && p->desc->delay.unprepare)
|
||||
+ panel_simple_sleep(p->desc->delay.unprepare);
|
||||
+
|
||||
+ p->prepared = false;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_prepare(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+ int err;
|
||||
+
|
||||
+ if (p->prepared)
|
||||
+ return 0;
|
||||
+
|
||||
+ err = panel_simple_regulator_enable(panel);
|
||||
+ if (err < 0) {
|
||||
+ dev_err(panel->dev, "failed to enable supply: %d\n", err);
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ if (p->enable_gpio)
|
||||
+ gpiod_direction_output(p->enable_gpio, 1);
|
||||
+
|
||||
+ if (p->desc && p->desc->delay.prepare)
|
||||
+ panel_simple_sleep(p->desc->delay.prepare);
|
||||
+
|
||||
+ if (p->reset_gpio)
|
||||
+ gpiod_direction_output(p->reset_gpio, !p->reset_level);
|
||||
+
|
||||
+ if (p->desc && p->desc->delay.reset)
|
||||
+ panel_simple_sleep(p->desc->delay.reset);
|
||||
+
|
||||
+ if (p->reset_gpio)
|
||||
+ gpiod_direction_output(p->reset_gpio, p->reset_level);
|
||||
+
|
||||
+ if (p->desc && p->desc->delay.init)
|
||||
+ panel_simple_sleep(p->desc->delay.init);
|
||||
+
|
||||
+ if (p->on_cmds) {
|
||||
+ if (p->dsi)
|
||||
+ err = panel_simple_dsi_send_cmds(p, p->on_cmds);
|
||||
+ if (err)
|
||||
+ dev_err(p->dev, "failed to send on cmds\n");
|
||||
+ }
|
||||
+
|
||||
+ p->prepared = true;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_enable(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+ int err = 0;
|
||||
+
|
||||
+ if (p->enabled)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (p->desc && p->desc->delay.enable)
|
||||
+ panel_simple_sleep(p->desc->delay.enable);
|
||||
+
|
||||
+ p->enabled = true;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_get_timings(struct drm_panel *panel,
|
||||
+ unsigned int num_timings,
|
||||
+ struct display_timing *timings)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+ unsigned int i;
|
||||
+
|
||||
+ if (!p->desc)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (p->desc->num_timings < num_timings)
|
||||
+ num_timings = p->desc->num_timings;
|
||||
+
|
||||
+ if (timings)
|
||||
+ for (i = 0; i < num_timings; i++)
|
||||
+ timings[i] = p->desc->timings[i];
|
||||
+
|
||||
+ return p->desc->num_timings;
|
||||
+}
|
||||
+
|
||||
+static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
|
||||
+{
|
||||
+ struct panel_simple *p = to_panel_simple(panel);
|
||||
+
|
||||
+ return p->orientation;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+static const struct drm_panel_funcs panel_simple_funcs = {
|
||||
+ .disable = panel_simple_disable,
|
||||
+ .unprepare = panel_simple_unprepare,
|
||||
+ .prepare = panel_simple_prepare,
|
||||
+ .enable = panel_simple_enable,
|
||||
+ .get_modes = panel_simple_get_modes,
|
||||
+ .get_orientation = panel_simple_get_orientation,
|
||||
+ .get_timings = panel_simple_get_timings,
|
||||
+};
|
||||
+
|
||||
+static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
|
||||
+{
|
||||
+ struct panel_simple *panel;
|
||||
+ struct panel_desc *of_desc;
|
||||
+ const char *cmd_type;
|
||||
+ u32 val;
|
||||
+ int err;
|
||||
+
|
||||
+ panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
|
||||
+ if (!panel)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ if (!desc)
|
||||
+ of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
|
||||
+ else
|
||||
+ of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
|
||||
+
|
||||
+ if (!of_property_read_u32(dev->of_node, "bus-format", &val))
|
||||
+ of_desc->bus_format = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "bpc", &val))
|
||||
+ of_desc->bpc = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "prepare-delay-ms", &val))
|
||||
+ of_desc->delay.prepare = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "enable-delay-ms", &val))
|
||||
+ of_desc->delay.enable = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "disable-delay-ms", &val))
|
||||
+ of_desc->delay.disable = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "unprepare-delay-ms", &val))
|
||||
+ of_desc->delay.unprepare = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "reset-delay-ms", &val))
|
||||
+ of_desc->delay.reset = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "init-delay-ms", &val))
|
||||
+ of_desc->delay.init = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "width-mm", &val))
|
||||
+ of_desc->size.width = val;
|
||||
+ if (!of_property_read_u32(dev->of_node, "height-mm", &val))
|
||||
+ of_desc->size.height = val;
|
||||
+
|
||||
+ panel->enabled = false;
|
||||
+ panel->prepared = false;
|
||||
+ panel->desc = of_desc;
|
||||
+ panel->dev = dev;
|
||||
+
|
||||
+ err = panel_simple_get_cmds(panel);
|
||||
+ if (err) {
|
||||
+ dev_err(dev, "failed to get init cmd: %d\n", err);
|
||||
+ return err;
|
||||
+ }
|
||||
+ panel->supply = devm_regulator_get(dev, "power");
|
||||
+ if (IS_ERR(panel->supply))
|
||||
+ return PTR_ERR(panel->supply);
|
||||
+
|
||||
+ panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
|
||||
+ if (IS_ERR(panel->enable_gpio)) {
|
||||
+ err = PTR_ERR(panel->enable_gpio);
|
||||
+ dev_err(dev, "failed to request enable GPIO: %d\n", err);
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
|
||||
+ if (IS_ERR(panel->reset_gpio)) {
|
||||
+ err = PTR_ERR(panel->reset_gpio);
|
||||
+ dev_err(dev, "failed to request reset GPIO: %d\n", err);
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ if (!of_property_read_u32(dev->of_node, "reset-level", &val)) {
|
||||
+ panel->reset_level = val;
|
||||
+ } else {
|
||||
+ panel->reset_level = 0;
|
||||
+ }
|
||||
+
|
||||
+ err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
|
||||
+ if (err) {
|
||||
+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ panel->cmd_type = CMD_TYPE_DEFAULT;
|
||||
+
|
||||
+ panel->power_invert =
|
||||
+ of_property_read_bool(dev->of_node, "power-invert");
|
||||
+
|
||||
+ drm_panel_init(&panel->base, dev, &panel_simple_funcs,DRM_MODE_CONNECTOR_DSI);
|
||||
+ panel->base.dev = dev;
|
||||
+ panel->base.funcs = &panel_simple_funcs;
|
||||
+
|
||||
+ err = drm_panel_of_backlight(&panel->base);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ drm_panel_add(&panel->base);
|
||||
+
|
||||
+ dev_set_drvdata(dev, panel);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int panel_simple_remove(struct device *dev)
|
||||
+{
|
||||
+ struct panel_simple *panel = dev_get_drvdata(dev);
|
||||
+
|
||||
+ drm_panel_remove(&panel->base);
|
||||
+
|
||||
+ panel_simple_disable(&panel->base);
|
||||
+ panel_simple_unprepare(&panel->base);
|
||||
+
|
||||
+ panel_simple_cmds_cleanup(panel);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void panel_simple_shutdown(struct device *dev)
|
||||
+{
|
||||
+ struct panel_simple *panel = dev_get_drvdata(dev);
|
||||
+
|
||||
+ panel_simple_disable(&panel->base);
|
||||
+
|
||||
+ if (panel->prepared) {
|
||||
+ if (panel->reset_gpio)
|
||||
+ gpiod_direction_output(panel->reset_gpio, !panel->reset_level);
|
||||
+
|
||||
+ if (panel->enable_gpio)
|
||||
+ gpiod_direction_output(panel->enable_gpio, 0);
|
||||
+
|
||||
+ panel_simple_regulator_disable(&panel->base);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+struct panel_desc_dsi {
|
||||
+ struct panel_desc desc;
|
||||
+
|
||||
+ unsigned long flags;
|
||||
+ enum mipi_dsi_pixel_format format;
|
||||
+ unsigned int lanes;
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
|
||||
+ .clock = 157200,
|
||||
+ .hdisplay = 1920,
|
||||
+ .hsync_start = 1920 + 154,
|
||||
+ .hsync_end = 1920 + 154 + 16,
|
||||
+ .htotal = 1920 + 154 + 16 + 32,
|
||||
+ .vdisplay = 1200,
|
||||
+ .vsync_start = 1200 + 17,
|
||||
+ .vsync_end = 1200 + 17 + 2,
|
||||
+ .vtotal = 1200 + 17 + 2 + 16,
|
||||
+ .vrefresh = 60,
|
||||
+};
|
||||
+static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
|
||||
+ .desc = {
|
||||
+ .modes = &panasonic_vvx10f004b00_mode,
|
||||
+ .num_modes = 1,
|
||||
+ .bpc = 8,
|
||||
+ .size = {
|
||||
+ .width = 217,
|
||||
+ .height = 136,
|
||||
+ },
|
||||
+ },
|
||||
+ .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
|
||||
+ MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||||
+ .format = MIPI_DSI_FMT_RGB888,
|
||||
+ .lanes = 4,
|
||||
+};
|
||||
+*/
|
||||
+
|
||||
+static const struct of_device_id dsi_of_match[] = {
|
||||
+ {
|
||||
+ .compatible = "panel-dsi-simple",
|
||||
+ .data = NULL
|
||||
+ }, {
|
||||
+ /* sentinel */
|
||||
+ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, dsi_of_match);
|
||||
+
|
||||
+static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
|
||||
+{
|
||||
+ struct device *dev = &dsi->dev;
|
||||
+ struct panel_simple *panel;
|
||||
+ const struct panel_desc_dsi *desc;
|
||||
+ const struct of_device_id *id;
|
||||
+ const struct panel_desc *pdesc;
|
||||
+ int err;
|
||||
+ u32 val;
|
||||
+
|
||||
+ id = of_match_node(dsi_of_match, dev->of_node);
|
||||
+ if (!id)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ desc = id->data;
|
||||
+
|
||||
+ if (desc) {
|
||||
+ dsi->mode_flags = desc->flags;
|
||||
+ dsi->format = desc->format;
|
||||
+ dsi->lanes = desc->lanes;
|
||||
+ pdesc = &desc->desc;
|
||||
+ } else {
|
||||
+ pdesc = NULL;
|
||||
+ }
|
||||
+
|
||||
+ err = panel_simple_probe(dev, pdesc);
|
||||
+ if (err < 0)
|
||||
+ return err;
|
||||
+
|
||||
+ panel = dev_get_drvdata(dev);
|
||||
+ panel->dsi = dsi;
|
||||
+
|
||||
+ if (!of_property_read_u32(dev->of_node, "dsi,flags", &val))
|
||||
+ dsi->mode_flags = val;
|
||||
+
|
||||
+ if (!of_property_read_u32(dev->of_node, "dsi,format", &val))
|
||||
+ dsi->format = val;
|
||||
+
|
||||
+ if (!of_property_read_u32(dev->of_node, "dsi,lanes", &val))
|
||||
+ dsi->lanes = val;
|
||||
+
|
||||
+ return mipi_dsi_attach(dsi);
|
||||
+}
|
||||
+
|
||||
+static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
|
||||
+{
|
||||
+ int err;
|
||||
+
|
||||
+ err = mipi_dsi_detach(dsi);
|
||||
+ if (err < 0)
|
||||
+ dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
|
||||
+
|
||||
+ panel_simple_remove(&dsi->dev);
|
||||
+}
|
||||
+
|
||||
+static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
|
||||
+{
|
||||
+ panel_simple_shutdown(&dsi->dev);
|
||||
+}
|
||||
+
|
||||
+static struct mipi_dsi_driver panel_simple_dsi_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "panel-dsi-simple",
|
||||
+ .of_match_table = dsi_of_match,
|
||||
+ },
|
||||
+ .probe = panel_simple_dsi_probe,
|
||||
+ .remove = panel_simple_dsi_remove,
|
||||
+ .shutdown = panel_simple_dsi_shutdown,
|
||||
+};
|
||||
+
|
||||
+module_mipi_dsi_driver(panel_simple_dsi_driver);
|
||||
+
|
||||
+MODULE_AUTHOR("iamdrq <iamdrq@qq.com>");
|
||||
+MODULE_DESCRIPTION("DRM Driver for DSI Simple Panels");
|
||||
+MODULE_LICENSE("GPL");
|
||||
@ -0,0 +1,12 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1685,7 +1685,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
|
||||
- pinctrl-names = "bclk_on", "bclk_off";
|
||||
+ pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_8ch_bus>;
|
||||
pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
|
||||
power-domains = <&power RK3399_PD_SDIOAUDIO>;
|
||||
|
||||
@ -1,656 +0,0 @@
|
||||
From 3b60e97e8cf8a1ae78ec68a2fed37cd763675e56 Mon Sep 17 00:00:00 2001
|
||||
From: baiywt <baiywt_gj@163.com>
|
||||
Date: Fri, 18 Feb 2022 16:38:43 +0800
|
||||
Subject: [PATCH] Add yt8531c support.
|
||||
Adapted from orangepi-xunlong/openwrt - 600-Add-yt8531c-support.patch by schwar3kat
|
||||
---
|
||||
drivers/net/phy/Kconfig | 5 +
|
||||
drivers/net/phy/motorcomm.c | 1540 +++++++++++++++++++++++++++++++++
|
||||
drivers/net/phy/yt8614-phy.h | 491 +++++++++++
|
||||
include/linux/motorcomm_phy.h | 119 +++
|
||||
5 files changed, 2156 insertions(+)
|
||||
create mode 100644 drivers/net/phy/motorcomm.c
|
||||
create mode 100644 drivers/net/phy/yt8614-phy.h
|
||||
create mode 100644 include/linux/motorcomm_phy.h
|
||||
|
||||
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
|
||||
index ce030fcb1..ff4861847 100644
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -297,6 +297,11 @@ config MICROSEMI_PHY
|
||||
help
|
||||
Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
|
||||
|
||||
+config MOTORCOMM_PHY
|
||||
+ tristate "Motorcomm PHYs"
|
||||
+ help
|
||||
+ Supports the YT8010, YT8510, YT8511, YT8512 YT8521 YT8531 PHYs.
|
||||
+
|
||||
config NATIONAL_PHY
|
||||
tristate "National Semiconductor PHYs"
|
||||
help
|
||||
diff --git a/drivers/net/phy/yt8614-phy.h b/drivers/net/phy/yt8614-phy.h
|
||||
new file mode 100644
|
||||
index 000000000..56a398338
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/phy/yt8614-phy.h
|
||||
@@ -0,0 +1,491 @@
|
||||
+#ifndef _PHY_H_
|
||||
+#define _PHY_H_
|
||||
+
|
||||
+
|
||||
+/* configuration for driver */
|
||||
+
|
||||
+#define YT8614_MAX_LPORT_ID 3
|
||||
+
|
||||
+#define YT8614_PHY_MODE_FIBER 1 //fiber mode only
|
||||
+#define YT8614_PHY_MODE_UTP 2 //utp mode only
|
||||
+#define YT8614_PHY_MODE_POLL 3 //fiber and utp, poll mode
|
||||
+
|
||||
+/* please make choice according to system design
|
||||
+ * for Fiber only system, please define YT8614_PHY_MODE_CURR 1
|
||||
+ * for UTP only system, please define YT8614_PHY_MODE_CURR 2
|
||||
+ * for combo system, please define YT8614_PHY_MODE_CURR 3
|
||||
+ */
|
||||
+#define YT8614_PHY_MODE_CURR 3
|
||||
+
|
||||
+
|
||||
+
|
||||
+/* pls dont modify below lines */
|
||||
+
|
||||
+#define PHY_ID_YT8614 0x4F51E899 //serdes
|
||||
+#define MOTORCOMM_MPHY_ID_MASK_8614 0xffffffff
|
||||
+
|
||||
+#ifndef BOOL
|
||||
+#define BOOL unsigned int
|
||||
+#endif
|
||||
+
|
||||
+#ifndef FALSE
|
||||
+#define FALSE 0
|
||||
+#endif
|
||||
+
|
||||
+#ifndef TRUE
|
||||
+#define TRUE 1
|
||||
+#endif
|
||||
+
|
||||
+#ifndef SPEED_1000M
|
||||
+#define SPEED_1000M 2
|
||||
+#endif
|
||||
+#ifndef SPEED_100M
|
||||
+#define SPEED_100M 1
|
||||
+#endif
|
||||
+#ifndef SPEED_10M
|
||||
+#define SPEED_10M 0
|
||||
+#endif
|
||||
+
|
||||
+#ifndef SPEED_UNKNOWN
|
||||
+#define SPEED_UNKNOWN 0xffff
|
||||
+#endif
|
||||
+
|
||||
+#ifndef DUPLEX_FULL
|
||||
+#define DUPLEX_FULL 1
|
||||
+#endif
|
||||
+#ifndef DUPLEX_HALF
|
||||
+#define DUPLEX_HALF 0
|
||||
+#endif
|
||||
+
|
||||
+#ifndef BIT
|
||||
+#define BIT(n) (0x1<<(n))
|
||||
+#endif
|
||||
+#ifndef s32
|
||||
+typedef int s32;
|
||||
+typedef unsigned int u32;
|
||||
+typedef unsigned short u16;
|
||||
+typedef unsigned char u8;
|
||||
+#endif
|
||||
+
|
||||
+#ifndef REG_PHY_SPEC_STATUS
|
||||
+#define REG_PHY_SPEC_STATUS 0x11
|
||||
+#define REG_DEBUG_ADDR_OFFSET 0x1e
|
||||
+#define REG_DEBUG_DATA 0x1f
|
||||
+#endif
|
||||
+
|
||||
+/**********YT8614************************************************/
|
||||
+
|
||||
+#define YT8614_SMI_SEL_PHY 0x0
|
||||
+#define YT8614_SMI_SEL_SDS_QSGMII 0x02
|
||||
+#define YT8614_SMI_SEL_SDS_SGMII 0x03
|
||||
+
|
||||
+/* yt8614 register type */
|
||||
+#define YT8614_TYPE_COMMON 0x01
|
||||
+#define YT8614_TYPE_UTP_MII 0x02
|
||||
+#define YT8614_TYPE_UTP_EXT 0x03
|
||||
+#define YT8614_TYPE_LDS_MII 0x04
|
||||
+#define YT8614_TYPE_UTP_MMD 0x05
|
||||
+#define YT8614_TYPE_SDS_QSGMII_MII 0x06
|
||||
+#define YT8614_TYPE_SDS_SGMII_MII 0x07
|
||||
+#define YT8614_TYPE_SDS_QSGMII_EXT 0x08
|
||||
+#define YT8614_TYPE_SDS_SGMII_EXT 0x09
|
||||
+
|
||||
+/* YT8614 extended common register */
|
||||
+#define YT8614_REG_COM_SMI_MUX 0xA000
|
||||
+#define YT8614_REG_COM_SLED_CFG0 0xA001
|
||||
+#define YT8614_REG_COM_PHY_ID 0xA002
|
||||
+#define YT8614_REG_COM_CHIP_VER 0xA003
|
||||
+#define YT8614_REG_COM_SLED_CFG 0xA004
|
||||
+#define YT8614_REG_COM_MODE_CHG_RESET 0xA005
|
||||
+#define YT8614_REG_COM_SYNCE0_CFG 0xA006
|
||||
+#define YT8614_REG_COM_CHIP_MODE 0xA007
|
||||
+
|
||||
+#define YT8614_REG_COM_HIDE_SPEED 0xA009
|
||||
+
|
||||
+#define YT8614_REG_COM_SYNCE1_CFG 0xA00E
|
||||
+
|
||||
+#define YT8614_REG_COM_HIDE_FIBER_MODE 0xA019
|
||||
+
|
||||
+
|
||||
+#define YT8614_REG_COM_HIDE_SEL1 0xA054
|
||||
+#define YT8614_REG_COM_HIDE_LED_CFG2 0xB8
|
||||
+#define YT8614_REG_COM_HIDE_LED_CFG3 0xB9
|
||||
+#define YT8614_REG_COM_HIDE_LED_CFG5 0xBB
|
||||
+
|
||||
+#define YT8614_REG_COM_HIDE_LED_CFG4 0xBA //not used currently
|
||||
+
|
||||
+#if 0
|
||||
+#define YT8614_REG_COM_HIDE_LED12_CFG 0xA060 //not used currently
|
||||
+#define YT8614_REG_COM_HIDE_LED13_CFG 0xA061
|
||||
+#define YT8614_REG_COM_HIDE_LED14_CFG 0xA062
|
||||
+#define YT8614_REG_COM_HIDE_LED15_CFG 0xA063
|
||||
+#define YT8614_REG_COM_HIDE_LED16_CFG 0xA064
|
||||
+#define YT8614_REG_COM_HIDE_LED17_CFG 0xA065
|
||||
+#define YT8614_REG_COM_HIDE_LED18_CFG 0xA066
|
||||
+#define YT8614_REG_COM_HIDE_LED19_CFG 0xA067
|
||||
+#define YT8614_REG_COM_HIDE_LED20_CFG 0xA068
|
||||
+#define YT8614_REG_COM_HIDE_LED21_CFG 0xA069
|
||||
+#define YT8614_REG_COM_HIDE_LED22_CFG 0xA06A
|
||||
+#define YT8614_REG_COM_HIDE_LED23_CFG 0xA06B
|
||||
+#define YT8614_REG_COM_HIDE_LED24_CFG 0xA06C
|
||||
+#define YT8614_REG_COM_HIDE_LED25_CFG 0xA06D
|
||||
+#define YT8614_REG_COM_HIDE_LED26_CFG 0xA06E
|
||||
+#define YT8614_REG_COM_HIDE_LED27_CFG 0xA06F
|
||||
+#endif
|
||||
+
|
||||
+#define YT8614_REG_COM_HIDE_LED28_CFG 0xA070
|
||||
+#define YT8614_REG_COM_HIDE_LED29_CFG 0xA071
|
||||
+#define YT8614_REG_COM_HIDE_LED30_CFG 0xA072
|
||||
+#define YT8614_REG_COM_HIDE_LED31_CFG 0xA073
|
||||
+#define YT8614_REG_COM_HIDE_LED32_CFG 0xA074
|
||||
+#define YT8614_REG_COM_HIDE_LED33_CFG 0xA075
|
||||
+#define YT8614_REG_COM_HIDE_LED34_CFG 0xA076
|
||||
+#define YT8614_REG_COM_HIDE_LED35_CFG 0xA077
|
||||
+
|
||||
+#define YT8614_REG_COM_PKG_CFG0 0xA0A0
|
||||
+#define YT8614_REG_COM_PKG_CFG1 0xA0A1
|
||||
+#define YT8614_REG_COM_PKG_CFG2 0xA0A2
|
||||
+#define YT8614_REG_COM_PKG_RX_VALID0 0xA0A3
|
||||
+#define YT8614_REG_COM_PKG_RX_VALID1 0xA0A4
|
||||
+#define YT8614_REG_COM_PKG_RX_OS0 0xA0A5
|
||||
+#define YT8614_REG_COM_PKG_RX_OS1 0xA0A6
|
||||
+#define YT8614_REG_COM_PKG_RX_US0 0xA0A7
|
||||
+#define YT8614_REG_COM_PKG_RX_US1 0xA0A8
|
||||
+#define YT8614_REG_COM_PKG_RX_ERR 0xA0A9
|
||||
+#define YT8614_REG_COM_PKG_RX_OS_BAD 0xA0AA
|
||||
+#define YT8614_REG_COM_PKG_RX_FRAG 0xA0AB
|
||||
+#define YT8614_REG_COM_PKG_RX_NOSFD 0xA0AC
|
||||
+#define YT8614_REG_COM_PKG_TX_VALID0 0xA0AD
|
||||
+#define YT8614_REG_COM_PKG_TX_VALID1 0xA0AE
|
||||
+#define YT8614_REG_COM_PKG_TX_OS0 0xA0AF
|
||||
+
|
||||
+#define YT8614_REG_COM_PKG_TX_OS1 0xA0B0
|
||||
+#define YT8614_REG_COM_PKG_TX_US0 0xA0B1
|
||||
+#define YT8614_REG_COM_PKG_TX_US1 0xA0B2
|
||||
+#define YT8614_REG_COM_PKG_TX_ERR 0xA0B3
|
||||
+#define YT8614_REG_COM_PKG_TX_OS_BAD 0xA0B4
|
||||
+#define YT8614_REG_COM_PKG_TX_FRAG 0xA0B5
|
||||
+#define YT8614_REG_COM_PKG_TX_NOSFD 0xA0B6
|
||||
+#define YT8614_REG_COM_PKG_CFG3 0xA0B7
|
||||
+#define YT8614_REG_COM_PKG_AZ_CFG 0xA0B8
|
||||
+#define YT8614_REG_COM_PKG_DA_SA_CFG3 0xA0B9
|
||||
+
|
||||
+#define YT8614_REG_COM_MANU_HW_RESET 0xA0C0
|
||||
+
|
||||
+/* YT8614 UTP MII register: same as generic phy register definitions */
|
||||
+#define REG_MII_BMCR 0x00 /* Basic mode control register */
|
||||
+#define REG_MII_BMSR 0x01 /* Basic mode status register */
|
||||
+#define REG_MII_PHYSID1 0x02 /* PHYS ID 1 */
|
||||
+#define REG_MII_PHYSID2 0x03 /* PHYS ID 2 */
|
||||
+#define REG_MII_ADVERTISE 0x04 /* Advertisement control reg */
|
||||
+#define REG_MII_LPA 0x05 /* Link partner ability reg */
|
||||
+#define REG_MII_EXPANSION 0x06 /* Expansion register */
|
||||
+#define REG_MII_NEXT_PAGE 0x07 /* Next page register */
|
||||
+#define REG_MII_LPR_NEXT_PAGE 0x08 /* LPR next page register */
|
||||
+#define REG_MII_CTRL1000 0x09 /* 1000BASE-T control */
|
||||
+#define REG_MII_STAT1000 0x0A /* 1000BASE-T status */
|
||||
+
|
||||
+#define REG_MII_MMD_CTRL 0x0D /* MMD access control register */
|
||||
+#define REG_MII_MMD_DATA 0x0E /* MMD access data register */
|
||||
+
|
||||
+#define REG_MII_ESTATUS 0x0F /* Extended Status */
|
||||
+#define REG_MII_SPEC_CTRL 0x10 /* PHY specific func control */
|
||||
+#define REG_MII_SPEC_STATUS 0x11 /* PHY specific status */
|
||||
+#define REG_MII_INT_MASK 0x12 /* Interrupt mask register */
|
||||
+#define REG_MII_INT_STATUS 0x13 /* Interrupt status register */
|
||||
+#define REG_MII_DOWNG_CTRL 0x14 /* Speed auto downgrade control*/
|
||||
+#define REG_MII_RERRCOUNTER 0x15 /* Receive error counter */
|
||||
+
|
||||
+#define REG_MII_EXT_ADDR 0x1E /* Extended reg's address */
|
||||
+#define REG_MII_EXT_DATA 0x1F /* Extended reg's date */
|
||||
+
|
||||
+#ifndef MII_BMSR
|
||||
+#define MII_BMSR REG_MII_BMSR
|
||||
+#endif
|
||||
+
|
||||
+#ifndef YT8614_SPEED_MODE_BIT
|
||||
+#define YT8614_SPEED_MODE 0xc000
|
||||
+#define YT8614_DUPLEX 0x2000
|
||||
+#define YT8614_SPEED_MODE_BIT 14
|
||||
+#define YT8614_DUPLEX_BIT 13
|
||||
+#define YT8614_LINK_STATUS_BIT 10
|
||||
+
|
||||
+#endif
|
||||
+
|
||||
+#define YT8614_REG_COM_HIDE_SPEED_CMB_PRI 0x2000
|
||||
+
|
||||
+/* YT8614 UTP MMD register */
|
||||
+#define YT8614_REG_UTP_MMD_CTRL1 0x00 /* PCS control 1 register */
|
||||
+#define YT8614_REG_UTP_MMD_STATUS1 0x01 /* PCS status 1 register */
|
||||
+#define YT8614_REG_UTP_MMD_EEE_CTRL 0x14 /* EEE control and capability */
|
||||
+#define YT8614_REG_UTP_MMD_EEE_WK_ERR_CNT 0x16 /* EEE wake error counter */
|
||||
+#define YT8614_REG_UTP_MMD_EEE_LOCAL_ABI 0x3C /* local device EEE ability */
|
||||
+#define YT8614_REG_UTP_MMD_EEE_LP_ABI 0x3D /* link partner EEE ability */
|
||||
+#define YT8614_REG_UTP_MMD_EEE_AUTONEG_RES 0x8000 /* autoneg result of EEE */
|
||||
+
|
||||
+/* YT8614 UTP EXT register */
|
||||
+#define YT8614_REG_UTP_EXT_LPBK 0x0A
|
||||
+#define YT8614_REG_UTP_EXT_SLEEP_CTRL1 0x27
|
||||
+#define YT8614_REG_UTP_EXT_DEBUG_MON1 0x5A
|
||||
+#define YT8614_REG_UTP_EXT_DEBUG_MON2 0x5B
|
||||
+#define YT8614_REG_UTP_EXT_DEBUG_MON3 0x5C
|
||||
+#define YT8614_REG_UTP_EXT_DEBUG_MON4 0x5D
|
||||
+
|
||||
+/* YT8614 SDS(1.25G/5G) MII register: same as YT8521S */
|
||||
+#define REG_SDS_BMCR 0x00 /* Basic mode control register */
|
||||
+#define REG_SDS_BMSR 0x01 /* Basic mode status register */
|
||||
+#define REG_SDS_PHYSID1 0x02 /* PHYS ID 1 */
|
||||
+#define REG_SDS_PHYSID2 0x03 /* PHYS ID 2 */
|
||||
+#define REG_SDS_ADVERTISE 0x04 /* Advertisement control reg */
|
||||
+#define REG_SDS_LPA 0x05 /* Link partner ability reg */
|
||||
+#define REG_SDS_EXPANSION 0x06 /* Expansion register */
|
||||
+#define REG_SDS_NEXT_PAGE 0x07 /* Next page register */
|
||||
+#define REG_SDS_LPR_NEXT_PAGE 0x08 /* LPR next page register */
|
||||
+
|
||||
+#define REG_SDS_ESTATUS 0x0F /* Extended Status */
|
||||
+#define REG_SDS_SPEC_STATUS 0x11 /* SDS specific status */
|
||||
+
|
||||
+#define REG_SDS_100FX_CFG 0x14 /* 100fx cfg */
|
||||
+#define REG_SDS_RERRCOUNTER 0x15 /* Receive error counter */
|
||||
+#define REG_SDS_LINT_FAIL_CNT 0x16 /* Lint fail counter mon */
|
||||
+
|
||||
+/* YT8614 SDS(5G) EXT register */
|
||||
+#define YT8614_REG_QSGMII_EXT_ANA_DIG_CFG 0x02 /* sds analog digital interface cfg */
|
||||
+#define YT8614_REG_QSGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */
|
||||
+#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_1 0x06 /* sds prbs cfg2 */
|
||||
+#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_2 0x07 /* sds prbs cfg2 */
|
||||
+#define YT8614_REG_QSGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */
|
||||
+#define YT8614_REG_QSGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */
|
||||
+#define YT8614_REG_QSGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */
|
||||
+#define YT8614_REG_QSGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */
|
||||
+#define YT8614_REG_QSGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */
|
||||
+#define YT8614_REG_QSGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */
|
||||
+
|
||||
+/* YT8614 SDS(1.25G) EXT register */
|
||||
+#define YT8614_REG_SGMII_EXT_PRBS_CFG1 0x05 /* sds prbs cfg1 */
|
||||
+#define YT8614_REG_SGMII_EXT_PRBS_CFG2 0x06 /* sds prbs cfg2 */
|
||||
+#define YT8614_REG_SGMII_EXT_PRBS_MON1 0x08 /* sds prbs mon1 */
|
||||
+#define YT8614_REG_SGMII_EXT_PRBS_MON2 0x09 /* sds prbs mon2 */
|
||||
+#define YT8614_REG_SGMII_EXT_PRBS_MON3 0x0A /* sds prbs mon3 */
|
||||
+#define YT8614_REG_SGMII_EXT_PRBS_MON4 0x0B /* sds prbs mon4 */
|
||||
+#define YT8614_REG_SGMII_EXT_PRBS_MON5 0x0C /* sds prbs mon5 */
|
||||
+#define YT8614_REG_SGMII_EXT_ANA_CFG2 0xA1 /* Analog cfg2 */
|
||||
+#define YT8614_REG_SGMII_EXT_HIDE_AUTO_SEN 0xA5 /* Fiber auto sensing */
|
||||
+
|
||||
+////////////////////////////////////////////////////////////////////
|
||||
+#define YT8614_MMD_DEV_ADDR1 0x1
|
||||
+#define YT8614_MMD_DEV_ADDR3 0x3
|
||||
+#define YT8614_MMD_DEV_ADDR7 0x7
|
||||
+#define YT8614_MMD_DEV_ADDR_NONE 0xFF
|
||||
+
|
||||
+/**********YT8521S************************************************/
|
||||
+/* Basic mode control register(0x00) */
|
||||
+#define BMCR_RESV 0x003f /* Unused... */
|
||||
+#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
|
||||
+#define BMCR_CTST 0x0080 /* Collision test */
|
||||
+#define BMCR_FULLDPLX 0x0100 /* Full duplex */
|
||||
+#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
|
||||
+#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
|
||||
+#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
|
||||
+#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
|
||||
+#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
|
||||
+#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
|
||||
+#define BMCR_RESET 0x8000 /* Reset the DP83840 */
|
||||
+
|
||||
+/* Basic mode status register(0x01) */
|
||||
+#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
|
||||
+#define BMSR_JCD 0x0002 /* Jabber detected */
|
||||
+#define BMSR_LSTATUS 0x0004 /* Link status */
|
||||
+#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
|
||||
+#define BMSR_RFAULT 0x0010 /* Remote fault detected */
|
||||
+#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
|
||||
+#define BMSR_RESV 0x00c0 /* Unused... */
|
||||
+#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
|
||||
+#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
|
||||
+#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
|
||||
+#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
|
||||
+#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
|
||||
+#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
|
||||
+#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
|
||||
+#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
|
||||
+
|
||||
+/* Advertisement control register(0x04) */
|
||||
+#define ADVERTISE_SLCT 0x001f /* Selector bits */
|
||||
+#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
|
||||
+#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
|
||||
+#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
|
||||
+#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
|
||||
+#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
|
||||
+#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
|
||||
+#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
|
||||
+#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
|
||||
+#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
|
||||
+#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
|
||||
+#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
|
||||
+#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
|
||||
+#define ADVERTISE_RESV 0x1000 /* Unused... */
|
||||
+#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
|
||||
+#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
|
||||
+#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
|
||||
+
|
||||
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
|
||||
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
|
||||
+ ADVERTISE_100HALF | ADVERTISE_100FULL)
|
||||
+
|
||||
+/* Link partner ability register(0x05) */
|
||||
+#define LPA_SLCT 0x001f /* Same as advertise selector */
|
||||
+#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
|
||||
+#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
|
||||
+#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
|
||||
+#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
|
||||
+#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
|
||||
+#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
|
||||
+#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
|
||||
+#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym */
|
||||
+#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
|
||||
+#define LPA_PAUSE_CAP 0x0400 /* Can pause */
|
||||
+#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
|
||||
+#define LPA_RESV 0x1000 /* Unused... */
|
||||
+#define LPA_RFAULT 0x2000 /* Link partner faulted */
|
||||
+#define LPA_LPACK 0x4000 /* Link partner acked us */
|
||||
+#define LPA_NPAGE 0x8000 /* Next page bit */
|
||||
+
|
||||
+/* 1000BASE-T Control register(0x09) */
|
||||
+#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
|
||||
+#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
|
||||
+#define CTL1000_AS_MASTER 0x0800
|
||||
+#define CTL1000_ENABLE_MASTER 0x1000
|
||||
+
|
||||
+/* 1000BASE-T Status register(0x0A) */
|
||||
+#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
|
||||
+#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
|
||||
+#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
|
||||
+#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
|
||||
+
|
||||
+/**********YT8614************************************************/
|
||||
+/* Basic mode control register(0x00) */
|
||||
+#define FIBER_BMCR_RESV 0x001f /* b[4:0] Unused... */
|
||||
+#define FIBER_BMCR_EN_UNIDIR 0x0020 /* b[5] Valid when bit 0.12 is zero and bit 0.8 is one */
|
||||
+#define FIBER_BMCR_SPEED1000 0x0040 /* b[6] MSB of Speed (1000) */
|
||||
+#define FIBER_BMCR_CTST 0x0080 /* b[7] Collision test */
|
||||
+#define FIBER_BMCR_DUPLEX_MODE 0x0100 /* b[8] Duplex mode */
|
||||
+#define FIBER_BMCR_ANRESTART 0x0200 /* b[9] Auto negotiation restart */
|
||||
+#define FIBER_BMCR_ISOLATE 0x0400 /* b[10] Isolate phy from RGMII/SGMII/FIBER */
|
||||
+#define FIBER_BMCR_PDOWN 0x0800 /* b[11] 1: Power down */
|
||||
+#define FIBER_BMCR_ANENABLE 0x1000 /* b[12] Enable auto negotiation */
|
||||
+#define FIBER_BMCR_SPEED100 0x2000 /* b[13] LSB of Speed (100) */
|
||||
+#define FIBER_BMCR_LOOPBACK 0x4000 /* b[14] Internal loopback control */
|
||||
+#define FIBER_BMCR_RESET 0x8000 /* b[15] PHY Software Reset(self-clear) */
|
||||
+
|
||||
+/* Sds specific status register(0x11) */
|
||||
+#define FIBER_SSR_ERCAP 0x0001 /* b[0] realtime syncstatus */
|
||||
+#define FIBER_SSR_XMIT 0x000E /* b[3:1] realtime transmit statemachine.
|
||||
+ 001: Xmit Idle;
|
||||
+ 010: Xmit Config;
|
||||
+ 100: Xmit Data. */
|
||||
+#define FIBER_SSR_SER_MODE_CFG 0x0030 /* b[5:4] realtime serdes working mode.
|
||||
+ 00: SG_MAC;
|
||||
+ 01: SG_PHY;
|
||||
+ 10: FIB_1000;
|
||||
+ 11: FIB_100. */
|
||||
+#define FIBER_SSR_EN_FLOWCTRL_TX 0x0040 /* b[6] realtime en_flowctrl_tx */
|
||||
+#define FIBER_SSR_EN_FLOWCTRL_RX 0x0080 /* b[7] realtime en_flowctrl_rx */
|
||||
+#define FIBER_SSR_DUPLEX_ERROR 0x0100 /* b[8] realtime deplex error */
|
||||
+#define FIBER_SSR_RX_LPI_ACTIVE 0x0200 /* b[9] rx lpi is active */
|
||||
+#define FIBER_SSR_LSTATUS 0x0400 /* b[10] Link status real-time */
|
||||
+#define FIBER_SSR_PAUSE 0x1800 /* b[12:11] Pause to mac */
|
||||
+#define FIBER_SSR_DUPLEX 0x2000 /* b[13] This status bit is valid only when bit10 is 1.
|
||||
+ 1: full duplex
|
||||
+ 0: half duplex */
|
||||
+#define FIBER_SSR_SPEED_MODE 0xC000 /* b[15:14] These status bits are valid only when bit10 is 1.
|
||||
+ 10---1000M
|
||||
+ 01---100M */
|
||||
+
|
||||
+/* SLED cfg0 (ext 0xA001) */
|
||||
+#define FIBER_SLED_CFG0_EN_CTRL 0x00FF /* b[7:0] Control to enable the eight ports' SLED */
|
||||
+#define FIBER_SLED_CFG0_BIT_MASK 0x0700 /* b[10:8] 1: enable the pin output */
|
||||
+#define FIBER_SLED_CFG0_ACT_LOW 0x0800 /* b[11] control SLED's polarity. 1: active low; 0: active high */
|
||||
+#define FIBER_SLED_CFG0_MANU_ST 0x7000 /* b[14:12] SLEDs' manul status, corresponding to each port's 3 SLEDs */
|
||||
+#define FIBER_SLED_CFG0_MANU_EN 0x8000 /* b[15] to control serial LEDs status manually */
|
||||
+
|
||||
+/**********YT8614************************************************/
|
||||
+/* Fiber auto sensing(sgmii ext 0xA5) */
|
||||
+#define FIBER_AUTO_SEN_ENABLE 0x8000 /* b[15] Enable fiber auto sensing */
|
||||
+
|
||||
+/* Fiber force speed(common ext 0xA009) */
|
||||
+#define FIBER_FORCE_1000M 0x0001 /* b[0] 1:1000BX 0:100FX */
|
||||
+
|
||||
+#ifndef NULL
|
||||
+#define NULL 0
|
||||
+#endif
|
||||
+
|
||||
+/* errno */
|
||||
+enum ytphy_8614_errno_e
|
||||
+{
|
||||
+ SYS_E_NONE,
|
||||
+ SYS_E_PARAM,
|
||||
+ SYS_E_MAX
|
||||
+};
|
||||
+
|
||||
+/* errno */
|
||||
+enum ytphy_8614_combo_speed_e
|
||||
+{
|
||||
+ YT8614_COMBO_FIBER_1000M,
|
||||
+ YT8614_COMBO_FIBER_100M,
|
||||
+ YT8614_COMBO_UTP_ONLY,
|
||||
+ YT8614_COMBO_SPEED_MAX
|
||||
+};
|
||||
+
|
||||
+/* definition for porting */
|
||||
+/* phy registers access */
|
||||
+typedef struct
|
||||
+{
|
||||
+ u16 reg; /* the offset of the phy internal address */
|
||||
+ u16 val; /* the value of the register */
|
||||
+ u8 regType; /* register type */
|
||||
+} phy_data_s;
|
||||
+
|
||||
+/* for porting use.
|
||||
+ * pls over-write member function read/write for mdio access
|
||||
+ */
|
||||
+typedef struct phy_info_str
|
||||
+{
|
||||
+#if 0
|
||||
+ struct phy_device *phydev;
|
||||
+ int mdio_base;
|
||||
+#endif
|
||||
+ unsigned int lport;
|
||||
+ unsigned int bus_id;
|
||||
+ unsigned int phy_addr;
|
||||
+
|
||||
+ s32 (*read)(struct phy_info_str *info, phy_data_s *param);
|
||||
+ s32 (*write)(struct phy_info_str *info, phy_data_s *param);
|
||||
+}phy_info_s;
|
||||
+
|
||||
+/* get phy access method */
|
||||
+s32 yt8614_read_reg(struct phy_info_str *info, phy_data_s *param);
|
||||
+s32 yt8614_write_reg(struct phy_info_str *info, phy_data_s *param);
|
||||
+s32 yt8614_phy_soft_reset(u32 lport);
|
||||
+s32 yt8614_phy_init(u32 lport);
|
||||
+s32 yt8614_fiber_enable(u32 lport, BOOL enable);
|
||||
+s32 yt8614_utp_enable(u32 lport, BOOL enable);
|
||||
+s32 yt8614_fiber_unidirection_set(u32 lport, int speed, BOOL enable);
|
||||
+s32 yt8614_fiber_autosensing_set(u32 lport, BOOL enable);
|
||||
+s32 yt8614_fiber_speed_set(u32 lport, int fiber_speed);
|
||||
+s32 yt8614_qsgmii_autoneg_set(u32 lport, BOOL enable);
|
||||
+s32 yt8614_sgmii_autoneg_set(u32 lport, BOOL enable);
|
||||
+s32 yt8614_qsgmii_sgmii_link_status_get(u32 lport, BOOL *enable, BOOL if_qsgmii);
|
||||
+int yt8614_combo_media_priority_set (u32 lport, int fiber);
|
||||
+int yt8614_combo_media_priority_get (u32 lport, int *fiber);
|
||||
+s32 yt8614_utp_autoneg_set(u32 lport, BOOL enable);
|
||||
+s32 yt8614_utp_autoneg_get(u32 lport, BOOL *enable);
|
||||
+s32 yt8614_utp_autoneg_ability_set(u32 lport, unsigned int cap_mask);
|
||||
+s32 yt8614_utp_autoneg_ability_get(u32 lport, unsigned int *cap_mask);
|
||||
+s32 yt8614_utp_force_duplex_set(u32 lport, BOOL full);
|
||||
+s32 yt8614_utp_force_duplex_get(u32 lport, BOOL *full);
|
||||
+s32 yt8614_utp_force_speed_set(u32 lport, unsigned int speed);
|
||||
+s32 yt8614_utp_force_speed_get(u32 lport, unsigned int *speed);
|
||||
+int yt8614_autoneg_done_get (u32 lport, int speed, int *aneg);
|
||||
+int yt8614_media_status_get(u32 lport, int* speed, int* duplex, int* ret_link, int *media);
|
||||
+
|
||||
+#endif
|
||||
diff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h
|
||||
new file mode 100644
|
||||
index 000000000..9e01fc205
|
||||
--- /dev/null
|
||||
+++ b/include/linux/motorcomm_phy.h
|
||||
@@ -0,0 +1,119 @@
|
||||
+/*
|
||||
+ * include/linux/motorcomm_phy.h
|
||||
+ *
|
||||
+ * Motorcomm PHY IDs
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms of the GNU General Public License as published by the
|
||||
+ * Free Software Foundation; either version 2 of the License, or (at your
|
||||
+ * option) any later version.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#ifndef _MOTORCOMM_PHY_H
|
||||
+#define _MOTORCOMM_PHY_H
|
||||
+
|
||||
+#define MOTORCOMM_PHY_ID_MASK 0x00000fff
|
||||
+#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff
|
||||
+#define MOTORCOMM_MPHY_ID_MASK 0x0000ffff
|
||||
+
|
||||
+#define PHY_ID_YT8010 0x00000309
|
||||
+#define PHY_ID_YT8510 0x00000109
|
||||
+#define PHY_ID_YT8511 0x0000010a
|
||||
+#define PHY_ID_YT8512 0x00000118
|
||||
+#define PHY_ID_YT8512B 0x00000128
|
||||
+#define PHY_ID_YT8521 0x0000011a
|
||||
+#define PHY_ID_YT8531S 0x4f51e91a
|
||||
+#define PHY_ID_YT8531 0x4f51e91b
|
||||
+//#define PHY_ID_YT8614 0x0000e899
|
||||
+#define PHY_ID_YT8618 0x0000e889
|
||||
+
|
||||
+#define REG_PHY_SPEC_STATUS 0x11
|
||||
+#define REG_DEBUG_ADDR_OFFSET 0x1e
|
||||
+#define REG_DEBUG_DATA 0x1f
|
||||
+
|
||||
+#define YT8512_EXTREG_AFE_PLL 0x50
|
||||
+#define YT8512_EXTREG_EXTEND_COMBO 0x4000
|
||||
+#define YT8512_EXTREG_LED0 0x40c0
|
||||
+#define YT8512_EXTREG_LED1 0x40c3
|
||||
+
|
||||
+#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
|
||||
+
|
||||
+#define YT_SOFTWARE_RESET 0x8000
|
||||
+
|
||||
+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
|
||||
+#define YT8512_CONTROL1_RMII_EN 0x0001
|
||||
+#define YT8512_LED0_ACT_BLK_IND 0x1000
|
||||
+#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
|
||||
+#define YT8512_LED0_BT_BLK_EN 0x0002
|
||||
+#define YT8512_LED0_HT_BLK_EN 0x0004
|
||||
+#define YT8512_LED0_COL_BLK_EN 0x0008
|
||||
+#define YT8512_LED0_BT_ON_EN 0x0010
|
||||
+#define YT8512_LED1_BT_ON_EN 0x0010
|
||||
+#define YT8512_LED1_TXACT_BLK_EN 0x0100
|
||||
+#define YT8512_LED1_RXACT_BLK_EN 0x0200
|
||||
+#define YT8512_SPEED_MODE 0xc000
|
||||
+#define YT8512_DUPLEX 0x2000
|
||||
+
|
||||
+#define YT8512_SPEED_MODE_BIT 14
|
||||
+#define YT8512_DUPLEX_BIT 13
|
||||
+#define YT8512_EN_SLEEP_SW_BIT 15
|
||||
+
|
||||
+#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
|
||||
+#define YT8521_EN_SLEEP_SW_BIT 15
|
||||
+
|
||||
+#define YT8521_SPEED_MODE 0xc000
|
||||
+#define YT8521_DUPLEX 0x2000
|
||||
+#define YT8521_SPEED_MODE_BIT 14
|
||||
+#define YT8521_DUPLEX_BIT 13
|
||||
+#define YT8521_LINK_STATUS_BIT 10
|
||||
+
|
||||
+/* based on yt8521 wol config register */
|
||||
+#define YTPHY_UTP_INTR_REG 0x12
|
||||
+/* WOL Event Interrupt Enable */
|
||||
+#define YTPHY_WOL_INTR BIT(6)
|
||||
+
|
||||
+/* Magic Packet MAC address registers */
|
||||
+#define YTPHY_MAGIC_PACKET_MAC_ADDR2 0xa007
|
||||
+#define YTPHY_MAGIC_PACKET_MAC_ADDR1 0xa008
|
||||
+#define YTPHY_MAGIC_PACKET_MAC_ADDR0 0xa009
|
||||
+
|
||||
+#define YTPHY_WOL_CFG_REG 0xa00a
|
||||
+#define YTPHY_WOL_CFG_TYPE BIT(0) /* WOL TYPE */
|
||||
+#define YTPHY_WOL_CFG_EN BIT(3) /* WOL Enable */
|
||||
+#define YTPHY_WOL_CFG_INTR_SEL BIT(6) /* WOL Event Interrupt Enable */
|
||||
+#define YTPHY_WOL_CFG_WIDTH1 BIT(1) /* WOL Pulse Width */
|
||||
+#define YTPHY_WOL_CFG_WIDTH2 BIT(2)
|
||||
+
|
||||
+#define YTPHY_REG_SPACE_UTP 0
|
||||
+#define YTPHY_REG_SPACE_FIBER 2
|
||||
+
|
||||
+enum ytphy_wol_type_e
|
||||
+{
|
||||
+ YTPHY_WOL_TYPE_LEVEL,
|
||||
+ YTPHY_WOL_TYPE_PULSE,
|
||||
+ YTPHY_WOL_TYPE_MAX
|
||||
+};
|
||||
+typedef enum ytphy_wol_type_e ytphy_wol_type_t;
|
||||
+
|
||||
+enum ytphy_wol_width_e
|
||||
+{
|
||||
+ YTPHY_WOL_WIDTH_84MS,
|
||||
+ YTPHY_WOL_WIDTH_168MS,
|
||||
+ YTPHY_WOL_WIDTH_336MS,
|
||||
+ YTPHY_WOL_WIDTH_672MS,
|
||||
+ YTPHY_WOL_WIDTH_MAX
|
||||
+};
|
||||
+typedef enum ytphy_wol_width_e ytphy_wol_width_t;
|
||||
+
|
||||
+struct ytphy_wol_cfg_s
|
||||
+{
|
||||
+ int enable;
|
||||
+ int type;
|
||||
+ int width;
|
||||
+};
|
||||
+typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t;
|
||||
+
|
||||
+#endif /* _MOTORCOMM_PHY_H */
|
||||
+
|
||||
+
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -1,150 +0,0 @@
|
||||
From 0207f77ece3d07b964d5723c501adc3f3a5a3c6d Mon Sep 17 00:00:00 2001
|
||||
From: Dan Johansen <strit@manjaro.org>
|
||||
Date: Mon, 1 Jun 2020 17:14:50 +0200
|
||||
Subject: [PATCH] fix wonky wifi/bt on PBP
|
||||
|
||||
---
|
||||
drivers/bluetooth/hci_bcm.c | 17 +++++++++++++++++
|
||||
drivers/bluetooth/hci_serdev.c | 2 ++
|
||||
drivers/mmc/core/pwrseq_simple.c | 19 ++++++++++++++++---
|
||||
drivers/tty/serdev/core.c | 11 +++++++++++
|
||||
include/linux/serdev.h | 1 +
|
||||
5 files changed, 47 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c
|
||||
index b236cb11c0dc..bfd37fb9eeb0 100644
|
||||
--- a/drivers/bluetooth/hci_bcm.c
|
||||
+++ b/drivers/bluetooth/hci_bcm.c
|
||||
@@ -1472,6 +1472,22 @@ static void bcm_serdev_remove(struct serdev_device *serdev)
|
||||
hci_uart_unregister_device(&bcmdev->serdev_hu);
|
||||
}
|
||||
|
||||
+static void bcm_serdev_shutdown(struct serdev_device *serdev)
|
||||
+{
|
||||
+ struct bcm_device *bcmdev = serdev_device_get_drvdata(serdev);
|
||||
+
|
||||
+/*
|
||||
+ if (test_bit(HCI_UART_REGISTERED, &bcmdev->hu->flags)) {
|
||||
+ hci_uart_unregister_device(&bcmdev->serdev_hu);
|
||||
+ }
|
||||
+*/
|
||||
+ dev_info(bcmdev->dev, "Cutting power to bluetooth module\n");
|
||||
+ if (bcm_gpio_set_power(bcmdev, false)) {
|
||||
+ dev_err(bcmdev->dev, "Failed to power down\n");
|
||||
+ }
|
||||
+ usleep_range(500000, 1000000);
|
||||
+}
|
||||
+
|
||||
#ifdef CONFIG_OF
|
||||
static struct bcm_device_data bcm4354_device_data = {
|
||||
.no_early_set_baudrate = true,
|
||||
@@ -1497,6 +1513,7 @@ MODULE_DEVICE_TABLE(of, bcm_bluetooth_of_match);
|
||||
static struct serdev_device_driver bcm_serdev_driver = {
|
||||
.probe = bcm_serdev_probe,
|
||||
.remove = bcm_serdev_remove,
|
||||
+ .shutdown = bcm_serdev_shutdown,
|
||||
.driver = {
|
||||
.name = "hci_uart_bcm",
|
||||
.of_match_table = of_match_ptr(bcm_bluetooth_of_match),
|
||||
diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c
|
||||
index 4652896d4990..043c585b34a7 100644
|
||||
--- a/drivers/bluetooth/hci_serdev.c
|
||||
+++ b/drivers/bluetooth/hci_serdev.c
|
||||
@@ -395,5 +395,7 @@ void hci_uart_unregister_device(struct hci_uart *hu)
|
||||
clear_bit(HCI_UART_PROTO_READY, &hu->flags);
|
||||
serdev_device_close(hu->serdev);
|
||||
}
|
||||
+
|
||||
+clear_bit(HCI_UART_REGISTERED, &hu->flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hci_uart_unregister_device);
|
||||
diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
|
||||
index ea4d3670560e..b52c3f5b4f13 100644
|
||||
--- a/drivers/mmc/core/pwrseq_simple.c
|
||||
+++ b/drivers/mmc/core/pwrseq_simple.c
|
||||
@@ -80,10 +80,8 @@ static void mmc_pwrseq_simple_post_power_on(struct mmc_host *host)
|
||||
msleep(pwrseq->post_power_on_delay_ms);
|
||||
}
|
||||
|
||||
-static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
|
||||
+static void __mmc_pwrseq_simple_power_off(struct mmc_pwrseq_simple *pwrseq)
|
||||
{
|
||||
- struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
|
||||
-
|
||||
mmc_pwrseq_simple_set_gpios_value(pwrseq, 1);
|
||||
|
||||
if (pwrseq->power_off_delay_us)
|
||||
@@ -96,6 +94,12 @@ static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
|
||||
}
|
||||
}
|
||||
|
||||
+static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
|
||||
+{
|
||||
+ struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
|
||||
+ __mmc_pwrseq_simple_power_off(pwrseq);
|
||||
+}
|
||||
+
|
||||
static const struct mmc_pwrseq_ops mmc_pwrseq_simple_ops = {
|
||||
.pre_power_on = mmc_pwrseq_simple_pre_power_on,
|
||||
.post_power_on = mmc_pwrseq_simple_post_power_on,
|
||||
@@ -151,9 +155,18 @@ static int mmc_pwrseq_simple_remove(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void mmc_pwrseq_simple_shutdown(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct mmc_pwrseq_simple *pwrseq = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ dev_info(&pdev->dev, "Turning off mmc\n");
|
||||
+ __mmc_pwrseq_simple_power_off(pwrseq);
|
||||
+}
|
||||
+
|
||||
static struct platform_driver mmc_pwrseq_simple_driver = {
|
||||
.probe = mmc_pwrseq_simple_probe,
|
||||
.remove = mmc_pwrseq_simple_remove,
|
||||
+ .shutdown = mmc_pwrseq_simple_shutdown,
|
||||
.driver = {
|
||||
.name = "pwrseq_simple",
|
||||
.of_match_table = mmc_pwrseq_simple_of_match,
|
||||
diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c
|
||||
index c5f0d936b003..54bcb38f0c05 100644
|
||||
--- a/drivers/tty/serdev/core.c
|
||||
+++ b/drivers/tty/serdev/core.c
|
||||
@@ -432,11 +432,22 @@ static int serdev_drv_remove(struct device *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void serdev_drv_shutdown(struct device *dev)
|
||||
+{
|
||||
+ const struct serdev_device_driver *sdrv;
|
||||
+ if (dev->driver) {
|
||||
+ sdrv = to_serdev_device_driver(dev->driver);
|
||||
+ if (sdrv->shutdown)
|
||||
+ sdrv->shutdown(to_serdev_device(dev));
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static struct bus_type serdev_bus_type = {
|
||||
.name = "serial",
|
||||
.match = serdev_device_match,
|
||||
.probe = serdev_drv_probe,
|
||||
.remove = serdev_drv_remove,
|
||||
+ .shutdown = serdev_drv_shutdown,
|
||||
};
|
||||
|
||||
/**
|
||||
diff --git a/include/linux/serdev.h b/include/linux/serdev.h
|
||||
index 9f14f9c12ec4..c3d5dccd6115 100644
|
||||
--- a/include/linux/serdev.h
|
||||
+++ b/include/linux/serdev.h
|
||||
@@ -63,6 +63,7 @@ struct serdev_device_driver {
|
||||
struct device_driver driver;
|
||||
int (*probe)(struct serdev_device *);
|
||||
void (*remove)(struct serdev_device *);
|
||||
+ void (*shutdown)(struct serdev_device *);
|
||||
};
|
||||
|
||||
static inline struct serdev_device_driver *to_serdev_device_driver(struct device_driver *d)
|
||||
--
|
||||
2.26.2
|
||||
|
||||
@ -9,30 +9,3 @@
|
||||
phy_type = "utmi_wide";
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
resets = <&cru SRST_USB3OTG0>;
|
||||
@@ -1031,6 +1031,25 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ i2s2_2ch: i2s@fe420000 {
|
||||
+ compatible = "rockchip,rk3568-i2s-tdm";
|
||||
+ reg = <0x0 0xfe420000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
||||
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
+ dmas = <&dmac1 4>, <&dmac1 5>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ rockchip,cru = <&cru>;
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ pinctrl-0 = <&i2s2m0_sclktx
|
||||
+ &i2s2m0_lrcktx
|
||||
+ &i2s2m0_sdi
|
||||
+ &i2s2m0_sdo>;
|
||||
+ pinctrl-names = "default";
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
i2s3_2ch: i2s@fe430000 {
|
||||
compatible = "rockchip,rk3568-i2s-tdm";
|
||||
reg = <0x0 0xfe430000 0x0 0x1000>;
|
||||
|
||||
|
||||
@ -58,6 +58,38 @@
|
||||
};
|
||||
};
|
||||
|
||||
@@ -190,6 +234,31 @@
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
+ };
|
||||
+
|
||||
+ wireless-wlan {
|
||||
+ compatible = "wlan-platdata";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ wifi_chip_type = "ap6359sa";
|
||||
+ sdio_vref = <1800>;
|
||||
+ WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
+ wireless-bluetooth {
|
||||
+ compatible = "bluetooth-platdata";
|
||||
+ clocks = <&rk808 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-names = "default", "rts_gpio";
|
||||
+ pinctrl-0 = <&uart0_rts>;
|
||||
+ pinctrl-1 = <&uart0_gpios>;
|
||||
+ // wifi-bt-power-toggle;
|
||||
+ // BT,power_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
+ BT,wake_gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
+ BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -453,10 +522,19 @@
|
||||
};
|
||||
|
||||
@ -73,8 +105,8 @@
|
||||
+ reg = <0x1a>;
|
||||
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
|
||||
+ clock-names = "mclk";
|
||||
+ //pinctrl-names = "default";
|
||||
+ //pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
+ };
|
||||
};
|
||||
|
||||
@ -155,6 +187,26 @@
|
||||
pmic {
|
||||
cpu_b_sleep: cpu-b-sleep {
|
||||
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
@@ -581,6 +713,19 @@
|
||||
|
||||
sdmmc0_pwr_h: sdmmc0-pwr-h {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wireless-wlan {
|
||||
+ wifi_pwr: wifi-pwr {
|
||||
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ wireless-bluetooth {
|
||||
+ uart0_gpios: uart0-gpios {
|
||||
+ rockchip,pins =
|
||||
+ <2 RK_PC3 1 &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -747,11 +892,3 @@
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
@ -167,3 +219,4 @@
|
||||
-&vopl_mmu {
|
||||
- status = "okay";
|
||||
-};
|
||||
|
||||
|
||||
@ -1,150 +0,0 @@
|
||||
From 0207f77ece3d07b964d5723c501adc3f3a5a3c6d Mon Sep 17 00:00:00 2001
|
||||
From: Dan Johansen <strit@manjaro.org>
|
||||
Date: Mon, 1 Jun 2020 17:14:50 +0200
|
||||
Subject: [PATCH] fix wonky wifi/bt on PBP
|
||||
|
||||
---
|
||||
drivers/bluetooth/hci_bcm.c | 17 +++++++++++++++++
|
||||
drivers/bluetooth/hci_serdev.c | 2 ++
|
||||
drivers/mmc/core/pwrseq_simple.c | 19 ++++++++++++++++---
|
||||
drivers/tty/serdev/core.c | 11 +++++++++++
|
||||
include/linux/serdev.h | 1 +
|
||||
5 files changed, 47 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c
|
||||
index b236cb11c0dc..bfd37fb9eeb0 100644
|
||||
--- a/drivers/bluetooth/hci_bcm.c
|
||||
+++ b/drivers/bluetooth/hci_bcm.c
|
||||
@@ -1472,6 +1472,22 @@ static void bcm_serdev_remove(struct serdev_device *serdev)
|
||||
hci_uart_unregister_device(&bcmdev->serdev_hu);
|
||||
}
|
||||
|
||||
+static void bcm_serdev_shutdown(struct serdev_device *serdev)
|
||||
+{
|
||||
+ struct bcm_device *bcmdev = serdev_device_get_drvdata(serdev);
|
||||
+
|
||||
+/*
|
||||
+ if (test_bit(HCI_UART_REGISTERED, &bcmdev->hu->flags)) {
|
||||
+ hci_uart_unregister_device(&bcmdev->serdev_hu);
|
||||
+ }
|
||||
+*/
|
||||
+ dev_info(bcmdev->dev, "Cutting power to bluetooth module\n");
|
||||
+ if (bcm_gpio_set_power(bcmdev, false)) {
|
||||
+ dev_err(bcmdev->dev, "Failed to power down\n");
|
||||
+ }
|
||||
+ usleep_range(500000, 1000000);
|
||||
+}
|
||||
+
|
||||
#ifdef CONFIG_OF
|
||||
static struct bcm_device_data bcm4354_device_data = {
|
||||
.no_early_set_baudrate = true,
|
||||
@@ -1497,6 +1513,7 @@ MODULE_DEVICE_TABLE(of, bcm_bluetooth_of_match);
|
||||
static struct serdev_device_driver bcm_serdev_driver = {
|
||||
.probe = bcm_serdev_probe,
|
||||
.remove = bcm_serdev_remove,
|
||||
+ .shutdown = bcm_serdev_shutdown,
|
||||
.driver = {
|
||||
.name = "hci_uart_bcm",
|
||||
.of_match_table = of_match_ptr(bcm_bluetooth_of_match),
|
||||
diff --git a/drivers/bluetooth/hci_serdev.c b/drivers/bluetooth/hci_serdev.c
|
||||
index 4652896d4990..043c585b34a7 100644
|
||||
--- a/drivers/bluetooth/hci_serdev.c
|
||||
+++ b/drivers/bluetooth/hci_serdev.c
|
||||
@@ -395,5 +395,7 @@ void hci_uart_unregister_device(struct hci_uart *hu)
|
||||
clear_bit(HCI_UART_PROTO_READY, &hu->flags);
|
||||
serdev_device_close(hu->serdev);
|
||||
}
|
||||
+
|
||||
+clear_bit(HCI_UART_REGISTERED, &hu->flags);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hci_uart_unregister_device);
|
||||
diff --git a/drivers/mmc/core/pwrseq_simple.c b/drivers/mmc/core/pwrseq_simple.c
|
||||
index ea4d3670560e..b52c3f5b4f13 100644
|
||||
--- a/drivers/mmc/core/pwrseq_simple.c
|
||||
+++ b/drivers/mmc/core/pwrseq_simple.c
|
||||
@@ -80,10 +80,8 @@ static void mmc_pwrseq_simple_post_power_on(struct mmc_host *host)
|
||||
msleep(pwrseq->post_power_on_delay_ms);
|
||||
}
|
||||
|
||||
-static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
|
||||
+static void __mmc_pwrseq_simple_power_off(struct mmc_pwrseq_simple *pwrseq)
|
||||
{
|
||||
- struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
|
||||
-
|
||||
mmc_pwrseq_simple_set_gpios_value(pwrseq, 1);
|
||||
|
||||
if (pwrseq->power_off_delay_us)
|
||||
@@ -96,6 +94,12 @@ static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
|
||||
}
|
||||
}
|
||||
|
||||
+static void mmc_pwrseq_simple_power_off(struct mmc_host *host)
|
||||
+{
|
||||
+ struct mmc_pwrseq_simple *pwrseq = to_pwrseq_simple(host->pwrseq);
|
||||
+ __mmc_pwrseq_simple_power_off(pwrseq);
|
||||
+}
|
||||
+
|
||||
static const struct mmc_pwrseq_ops mmc_pwrseq_simple_ops = {
|
||||
.pre_power_on = mmc_pwrseq_simple_pre_power_on,
|
||||
.post_power_on = mmc_pwrseq_simple_post_power_on,
|
||||
@@ -151,9 +155,18 @@ static int mmc_pwrseq_simple_remove(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void mmc_pwrseq_simple_shutdown(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct mmc_pwrseq_simple *pwrseq = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ dev_info(&pdev->dev, "Turning off mmc\n");
|
||||
+ __mmc_pwrseq_simple_power_off(pwrseq);
|
||||
+}
|
||||
+
|
||||
static struct platform_driver mmc_pwrseq_simple_driver = {
|
||||
.probe = mmc_pwrseq_simple_probe,
|
||||
.remove = mmc_pwrseq_simple_remove,
|
||||
+ .shutdown = mmc_pwrseq_simple_shutdown,
|
||||
.driver = {
|
||||
.name = "pwrseq_simple",
|
||||
.of_match_table = mmc_pwrseq_simple_of_match,
|
||||
diff --git a/drivers/tty/serdev/core.c b/drivers/tty/serdev/core.c
|
||||
index c5f0d936b003..54bcb38f0c05 100644
|
||||
--- a/drivers/tty/serdev/core.c
|
||||
+++ b/drivers/tty/serdev/core.c
|
||||
@@ -432,11 +432,22 @@ static int serdev_drv_remove(struct device *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void serdev_drv_shutdown(struct device *dev)
|
||||
+{
|
||||
+ const struct serdev_device_driver *sdrv;
|
||||
+ if (dev->driver) {
|
||||
+ sdrv = to_serdev_device_driver(dev->driver);
|
||||
+ if (sdrv->shutdown)
|
||||
+ sdrv->shutdown(to_serdev_device(dev));
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static struct bus_type serdev_bus_type = {
|
||||
.name = "serial",
|
||||
.match = serdev_device_match,
|
||||
.probe = serdev_drv_probe,
|
||||
.remove = serdev_drv_remove,
|
||||
+ .shutdown = serdev_drv_shutdown,
|
||||
};
|
||||
|
||||
/**
|
||||
diff --git a/include/linux/serdev.h b/include/linux/serdev.h
|
||||
index 9f14f9c12ec4..c3d5dccd6115 100644
|
||||
--- a/include/linux/serdev.h
|
||||
+++ b/include/linux/serdev.h
|
||||
@@ -63,6 +63,7 @@ struct serdev_device_driver {
|
||||
struct device_driver driver;
|
||||
int (*probe)(struct serdev_device *);
|
||||
void (*remove)(struct serdev_device *);
|
||||
+ void (*shutdown)(struct serdev_device *);
|
||||
};
|
||||
|
||||
static inline struct serdev_device_driver *to_serdev_device_driver(struct device_driver *d)
|
||||
--
|
||||
2.26.2
|
||||
|
||||
@ -0,0 +1,12 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1705,7 +1705,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
|
||||
- pinctrl-names = "bclk_on", "bclk_off";
|
||||
+ pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_8ch_bus>;
|
||||
pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
|
||||
power-domains = <&power RK3399_PD_SDIOAUDIO>;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user