0b49f88acf
Currently the thunk we upload into the SRAM is using DSB and ISB instructions, which were introduced in ARMv7. Also it relies on movw/movt pairs, which became available in ARMv6T2. The Allwinner F1Cx00 SoCs are using an ARMv5TE compliant core, so they do not know these instructions. Change the code to be ARMv5TE compliant, so it can run on all relevant Allwinner ARM cores: - One movw is just used to compare two bits, replace that with a tst/tsteq sequence to skip the load. - The other movw/movt pairs get replaced with ldr's, that load from literal storage at the end of the code (from Icenowy). - The DSB and ISB get replaced with their CP15 MCR counterparts. Those are deprecated in ARMv7, but still work, when the CP15BEN bit is set in SCTLR. We check for this in fel.c (from Icenowy). ISB is not implemented on the ARM926, so make this conditional. A simple branch takes care of the desired pipeline flush for the old SoC. Also remove the rather pointless Ruby prolog that generates the header file. We have a less awkward version of this in the Makefile, and need that for the other thunks there anyway, so it's just duplicated code. Embedding a header generator in Ruby in an assembly file is a cute gimmick, but serves no purpose anymore. This is based on work by Icenowy, who put a similar solution in a separate file. Originally-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Andre Przywara <osp@andrep.de>
87 lines
5.3 KiB
C
87 lines
5.3 KiB
C
/* <entry_point>: */
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0xea000015, /* 0: b 5c <setup_stack> */
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/* <stack_begin>: */
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0xffffffff, /* 4: .word 0xffffffff */
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0xffffffff, /* 8: .word 0xffffffff */
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0xffffffff, /* c: .word 0xffffffff */
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0xffffffff, /* 10: .word 0xffffffff */
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0xffffffff, /* 14: .word 0xffffffff */
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0xffffffff, /* 18: .word 0xffffffff */
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0xffffffff, /* 1c: .word 0xffffffff */
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0xffffffff, /* 20: .word 0xffffffff */
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/* <stack_end>: */
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0xe1a00000, /* 24: nop */
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/* <swap_all_buffers>: */
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0xe28f40e8, /* 28: add r4, pc, #232 */
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/* <swap_next_buffer>: */
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0xe4940004, /* 2c: ldr r0, [r4], #4 */
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0xe4941004, /* 30: ldr r1, [r4], #4 */
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0xe4946004, /* 34: ldr r6, [r4], #4 */
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0xe3560000, /* 38: cmp r6, #0 */
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0x012fff1e, /* 3c: bxeq lr */
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/* <swap_next_word>: */
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0xe5902000, /* 40: ldr r2, [r0] */
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0xe5913000, /* 44: ldr r3, [r1] */
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0xe2566004, /* 48: subs r6, r6, #4 */
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0xe4812004, /* 4c: str r2, [r1], #4 */
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0xe4803004, /* 50: str r3, [r0], #4 */
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0x1afffff9, /* 54: bne 40 <swap_next_word> */
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0xeafffff3, /* 58: b 2c <swap_next_buffer> */
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/* <setup_stack>: */
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0xe59f80b0, /* 5c: ldr r8, [pc, #176] */
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0xe24f0044, /* 60: sub r0, pc, #68 */
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0xe520d004, /* 64: str sp, [r0, #-4]! */
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0xe1a0d000, /* 68: mov sp, r0 */
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0xe10f2000, /* 6c: mrs r2, CPSR */
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0xe92d4004, /* 70: push {r2, lr} */
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0xe38220c0, /* 74: orr r2, r2, #192 */
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0xe121f002, /* 78: msr CPSR_c, r2 */
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0xee112f10, /* 7c: mrc 15, 0, r2, cr1, cr0, {0} */
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0xe3120004, /* 80: tst r2, #4 */
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0x03120a01, /* 84: tsteq r2, #4096 */
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0x1a000013, /* 88: bne dc <cache_is_unsupported> */
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0xebffffe5, /* 8c: bl 28 <swap_all_buffers> */
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/* <verify_checksum>: */
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0xe59f706c, /* 90: ldr r7, [pc, #108] */
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0xe1a00008, /* 94: mov r0, r8 */
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0xe5905010, /* 98: ldr r5, [r0, #16] */
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/* <check_next_word>: */
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0xe4902004, /* 9c: ldr r2, [r0], #4 */
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0xe2555004, /* a0: subs r5, r5, #4 */
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0xe0877002, /* a4: add r7, r7, r2 */
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0x1afffffb, /* a8: bne 9c <check_next_word> */
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0xe598200c, /* ac: ldr r2, [r8, #12] */
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0xe0577082, /* b0: subs r7, r7, r2, lsl #1 */
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0x1a00000b, /* b4: bne e8 <checksum_is_bad> */
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0xe59f2048, /* b8: ldr r2, [pc, #72] */
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0xe5882008, /* bc: str r2, [r8, #8] */
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0xee072f9a, /* c0: mcr 15, 0, r2, cr7, cr10, {4} */
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0xee102f10, /* c4: mrc 15, 0, r2, cr0, cr0, {0} */
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0xe202280f, /* c8: and r2, r2, #983040 */
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0xe3520806, /* cc: cmp r2, #393216 */
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0xce072f95, /* d0: mcrgt 15, 0, r2, cr7, cr5, {4} */
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0xe12fff38, /* d4: blx r8 */
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0xea000004, /* d8: b f0 <return_to_fel> */
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/* <cache_is_unsupported>: */
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0xe59f2028, /* dc: ldr r2, [pc, #40] */
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0xe5882008, /* e0: str r2, [r8, #8] */
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0xea000002, /* e4: b f4 <return_to_fel_noswap> */
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/* <checksum_is_bad>: */
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0xe59f2020, /* e8: ldr r2, [pc, #32] */
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0xe5882008, /* ec: str r2, [r8, #8] */
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/* <return_to_fel>: */
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0xebffffcc, /* f0: bl 28 <swap_all_buffers> */
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/* <return_to_fel_noswap>: */
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0xe8bd4004, /* f4: pop {r2, lr} */
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0xe121f002, /* f8: msr CPSR_c, r2 */
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0xe59dd000, /* fc: ldr sp, [sp] */
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0xe12fff1e, /* 100: bx lr */
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/* <checksum_seed>: */
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0x5f0a6c39, /* 104: .word 0x5f0a6c39 */
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/* <egon_fel_str>: */
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0x4c45462e, /* 108: .word 0x4c45462e */
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/* <cache_enabled_str>: */
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0x3f3f3f2e, /* 10c: .word 0x3f3f3f2e */
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/* <checksum_failed_str>: */
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0x4441422e, /* 110: .word 0x4441422e */
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