Merge pull request #179 from apritzel/v5_r528

Allwinner V5 and R528/T113 support
This commit is contained in:
Icenowy Zheng 2022-07-30 00:55:41 +08:00 committed by GitHub
commit e9c5719fea
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2 changed files with 44 additions and 5 deletions

View File

@ -409,6 +409,29 @@ soc_info_t soc_info_table[] = {
.sid_offset = 0x200,
.icache_fix = true,
.watchdog = &wd_v853_compat,
},{
.soc_id = 0x1859, /* Allwinner D1/D1s/R528/T113-S3 */
.name = "R528",
.spl_addr = 0x20000,
.scratch_addr = 0x21000,
.thunk_addr = 0x3a200, .thunk_size = 0x200,
.swap_buffers = v831_sram_swap_buffers,
.sram_size = 160 * 1024,
.sid_base = 0x03006000,
.sid_offset = 0x200,
.icache_fix = true,
.watchdog = &wd_v853_compat,
},{
.soc_id = 0x1721, /* Allwinner V5 */
.name = "V5",
.spl_addr = 0x20000,
.scratch_addr = 0x21000,
.thunk_addr = 0x42200, .thunk_size = 0x200,
.swap_buffers = h6_sram_swap_buffers,
.sram_size = 136 * 1024,
.sid_base = 0x03006000,
.sid_offset = 0x200,
.watchdog = &wd_h6_compat,
},{
.swap_buffers = NULL /* End of the table */
}

View File

@ -141,7 +141,9 @@ enum sunxi_gpio_number {
#define SUN5I_GPB_UART0 (2)
#define SUN6I_GPH_UART0 (2)
#define SUN8I_H3_GPA_UART0 (2)
#define SUN8I_R528_GPE_UART0 (6)
#define SUN8I_V3S_GPB_UART0 (3)
#define SUN8I_V5_GPB_UART0 (2)
#define SUN8I_V831_GPH_UART0 (5)
#define SUN8I_V853_GPH_UART0 (5)
#define SUN50I_H5_GPA_UART0 (2)
@ -310,6 +312,8 @@ void soc_detection_init(void)
#define soc_is_v3s() (soc_id == 0x1681)
#define soc_is_v831() (soc_id == 0x1817)
#define soc_is_v853() (soc_id == 0x1886)
#define soc_is_r528() (soc_id == 0x1859)
#define soc_is_v5() (soc_id == 0x1721)
/* A10s and A13 share the same ID, so we need a little more effort on those */
@ -394,9 +398,9 @@ void clock_init_uart_r329(void)
void clock_init_uart(void)
{
if (soc_is_h6() || soc_is_v831() || soc_is_h616())
if (soc_is_h6() || soc_is_v831() || soc_is_h616() || soc_is_v5())
clock_init_uart_h6();
else if (soc_is_r329() || soc_is_v853())
else if (soc_is_r329() || soc_is_v853() || soc_is_r528())
clock_init_uart_r329();
else
clock_init_uart_legacy();
@ -410,7 +414,7 @@ void clock_init_uart(void)
void gpio_init(void)
{
if (soc_is_v853()) {
if (soc_is_v853() || soc_is_r528()) {
/* GPIO V2 */
pio_bank_size = 0x30;
pio_dat_off = 0x10;
@ -478,6 +482,14 @@ void gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(9), SUN8I_V853_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(10), SUN8I_V853_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(10), SUNXI_GPIO_PULL_UP);
} else if (soc_is_r528()) {
sunxi_gpio_set_cfgpin(SUNXI_GPE(2), SUN8I_R528_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPE(3), SUN8I_R528_GPE_UART0);
sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
} else if (soc_is_v5()) {
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V5_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_V5_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
} else {
/* Unknown SoC */
while (1) {}
@ -574,13 +586,13 @@ int get_boot_device(void)
void bases_init(void)
{
if (soc_is_h6() || soc_is_v831() || soc_is_h616()) {
if (soc_is_h6() || soc_is_v831() || soc_is_h616() || soc_is_v5()) {
pio_base = H6_PIO_BASE;
uart0_base = H6_UART0_BASE;
} else if (soc_is_r329()) {
pio_base = R329_PIO_BASE;
uart0_base = R329_UART0_BASE;
} else if (soc_is_v853()) {
} else if (soc_is_v853() || soc_is_r528()) {
pio_base = V853_PIO_BASE;
uart0_base = R329_UART0_BASE;
} else {
@ -629,6 +641,10 @@ int main(void)
uart0_puts("Allwinner V831!\n");
else if (soc_is_v853())
uart0_puts("Allwinner V853!\n");
else if (soc_is_r528())
uart0_puts("Allwinner R528/T113!\n");
else if (soc_is_v5())
uart0_puts("Allwinner V5!\n");
else
uart0_puts("unknown Allwinner SoC!\n");