diff --git a/soc_info.c b/soc_info.c index c72ad3b..6414fa7 100644 --- a/soc_info.c +++ b/soc_info.c @@ -60,16 +60,18 @@ sram_swap_buffers a31_sram_swap_buffers[] = { /* * A64 has 32KiB of SRAM A at 0x10000 and a large SRAM C at 0x18000. SRAM A * and SRAM C reside in the address space back-to-back without any gaps, thus - * representing a singe large contiguous area. Everything is the same as on - * A10/A13/A20, but just shifted by 0x10000. + * representing a singe large contiguous area. The BROM FEL code memory areas + * are the same as on A10/A13/A20, but just shifted by 0x10000. + * We put the backup buffers towards the end of SRAM C, in a location that + * is also available on the H5. */ sram_swap_buffers a64_sram_swap_buffers[] = { /* 0x11C00-0x11FFF (IRQ stack) */ - { .buf1 = 0x11C00, .buf2 = 0x1A400, .size = 0x0400 }, + { .buf1 = 0x11C00, .buf2 = 0x31400, .size = 0x0400 }, /* 0x15C00-0x16FFF (Stack) */ - { .buf1 = 0x15C00, .buf2 = 0x1A800, .size = 0x1400 }, + { .buf1 = 0x15C00, .buf2 = 0x31800, .size = 0x1400 }, /* 0x17C00-0x17FFF (Something important) */ - { .buf1 = 0x17C00, .buf2 = 0x1BC00, .size = 0x0400 }, + { .buf1 = 0x17C00, .buf2 = 0x32c00, .size = 0x0400 }, { .size = 0 } /* End of the table */ }; @@ -212,9 +214,9 @@ soc_info_t soc_info_table[] = { .name = "A64", .spl_addr = 0x10000, .scratch_addr = 0x11000, - .thunk_addr = 0x1A200, .thunk_size = 0x200, + .thunk_addr = 0x31200, .thunk_size = 0x200, .swap_buffers = a64_sram_swap_buffers, - .sram_size = 192 * 1024, + .sram_size = 140 * 1024, .sid_base = 0x01C14000, .sid_offset = 0x200, .rvbar_reg = 0x017000A0, @@ -272,9 +274,9 @@ soc_info_t soc_info_table[] = { .name = "H5", .spl_addr = 0x10000, .scratch_addr = 0x11000, - .thunk_addr = 0x1A200, .thunk_size = 0x200, + .thunk_addr = 0x31200, .thunk_size = 0x200, .swap_buffers = a64_sram_swap_buffers, - .sram_size = 144 * 1024, + .sram_size = 140 * 1024, .sid_base = 0x01C14000, .sid_offset = 0x200, .rvbar_reg = 0x017000A0,