From 681403670889bb649b708a9cc77fca01b86359ce Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 19 Jun 2018 01:22:10 +0100 Subject: [PATCH] spi: Add support for H6 As Icenowy rightfully assumed, the V831 SPI support covers the H6 as well. The only difference was a slight deviation in the pinmux setup: the H6 has the SPI0-CS on pin PC5, the V831 on pin PC1. Just add the right SoC ID and tweak the pinmux setup to enable it. Tested on a Pine H64. Signed-off-by: Andre Przywara --- fel-spiflash.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/fel-spiflash.c b/fel-spiflash.c index 26e0bea..b7a3546 100644 --- a/fel-spiflash.c +++ b/fel-spiflash.c @@ -123,6 +123,7 @@ static uint32_t gpio_base(feldev_handle *dev) soc_info_t *soc_info = dev->soc_info; switch (soc_info->soc_id) { case 0x1817: /* V831 */ + case 0x1728: /* H6 */ return 0x0300B000; default: return 0x01C20800; @@ -139,6 +140,7 @@ static uint32_t spi_base(feldev_handle *dev) case 0x1701: /* R40 */ return 0x01C05000; case 0x1817: /* V831 */ + case 0x1728: /* H6 */ return 0x05010000; default: return 0x01C68000; @@ -178,6 +180,7 @@ static bool soc_is_h6_style(feldev_handle *dev) soc_info_t *soc_info = dev->soc_info; switch (soc_info->soc_id) { case 0x1817: /* V831 */ + case 0x1728: /* H6 */ return true; default: return false; @@ -223,10 +226,14 @@ static bool spi0_init(feldev_handle *dev) gpio_set_cfgpin(dev, PC, 3, SUN50I_GPC_SPI0); break; case 0x1817: /* Allwinner V831 */ + gpio_set_cfgpin(dev, PC, 1, SUN50I_GPC_SPI0); /* SPI0-CS */ + /* fall-through */ + case 0x1728: /* Allwinner H6 */ gpio_set_cfgpin(dev, PC, 0, SUN50I_GPC_SPI0); - gpio_set_cfgpin(dev, PC, 1, SUN50I_GPC_SPI0); gpio_set_cfgpin(dev, PC, 2, SUN50I_GPC_SPI0); gpio_set_cfgpin(dev, PC, 3, SUN50I_GPC_SPI0); + /* PC5 is SPI0-CS on the H6, and SPI0-HOLD on the V831 */ + gpio_set_cfgpin(dev, PC, 5, SUN50I_GPC_SPI0); break; default: /* Unknown/Unsupported SoC */ printf("SPI support not implemented yet for %x (%s)!\n",