From bbfcf117bb6b042420c4fe3f24e5ada5ca458336 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 29 Nov 2016 15:18:37 +0800 Subject: [PATCH 1/2] fel: Add SOC ID, SRAM info and SID address for R40 The R40 is marketed as the successor to the A20. The SRAM layout is the same as the A20, but there doesn't seem to be a secure SRAM block. The SID block is at a completely different address. The layout is the same as the newer SoCs, with the e-fuses at an offset of 0x200. Signed-off-by: Chen-Yu Tsai --- fel.c | 1 + soc_info.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/fel.c b/fel.c index a988371..4b1e587 100644 --- a/fel.c +++ b/fel.c @@ -265,6 +265,7 @@ void aw_fel_print_version(libusb_device_handle *usb) case 0x1667: soc_name="A33"; break; case 0x1673: soc_name="A83T"; break; case 0x1680: soc_name="H3"; break; + case 0x1701: soc_name="R40"; break; case 0x1718: soc_name="H5"; break; } diff --git a/soc_info.c b/soc_info.c index bfafdab..f35c363 100644 --- a/soc_info.c +++ b/soc_info.c @@ -167,6 +167,12 @@ soc_info_t soc_info_table[] = { .swap_buffers = a64_sram_swap_buffers, .sid_addr = 0x01C14200, .rvbar_reg = 0x017000A0, + },{ + .soc_id = 0x1701, /* Allwinner R40 */ + .scratch_addr = 0x1000, + .thunk_addr = 0xA200, .thunk_size = 0x200, + .swap_buffers = a10_a13_a20_sram_swap_buffers, + .sid_addr = 0x01C1B200, },{ .swap_buffers = NULL /* End of the table */ } From e4806339275b69f9ef16b83d9ce9d063b55da022 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 29 Nov 2016 15:20:07 +0800 Subject: [PATCH 2/2] uart0-helloworld: Add support for R40 The R40 is the same as the A20 for all intents and purposes of uart0-helloworld. Add R40's SOC ID. Signed-off-by: Chen-Yu Tsai --- uart0-helloworld-sdboot.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/uart0-helloworld-sdboot.c b/uart0-helloworld-sdboot.c index c9cde01..d60720c 100644 --- a/uart0-helloworld-sdboot.c +++ b/uart0-helloworld-sdboot.c @@ -256,6 +256,7 @@ void soc_detection_init(void) #define soc_is_a64() (soc_id == 0x1689) #define soc_is_h3() (soc_id == 0x1680) #define soc_is_h5() (soc_id == 0x1718) +#define soc_is_r40() (soc_id == 0x1701) /* A10s and A13 share the same ID, so we need a little more effort on those */ @@ -303,7 +304,7 @@ void clock_init_uart(void) void gpio_init(void) { - if (soc_is_a10() || soc_is_a20()) { + if (soc_is_a10() || soc_is_a20() || soc_is_r40()) { sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0); sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); @@ -446,6 +447,8 @@ int main(void) uart0_puts("Allwinner H3!\n"); else if (soc_is_h5()) uart0_puts("Allwinner H5!\n"); + else if (soc_is_r40()) + uart0_puts("Allwinner R40!\n"); else uart0_puts("unknown Allwinner SoC!\n");