From f483e7a74a4f0c2d30c3158f00a1f024274391d3 Mon Sep 17 00:00:00 2001
From: Qubot <1445788683@qq.com>
Date: Tue, 16 Jun 2026 22:13:32 +0800
Subject: [PATCH] media: sunxi-vin: tune BPI-M8 CSI1 PHY

---
 .../vin/vin-mipi/combo_csi/combo_csi_reg.c    |  5 ++++
 .../vin/vin-mipi/combo_csi/combo_csi_reg.h    |  1 +
 bsp/drivers/vin/vin-mipi/sunxi_mipi.c         | 23 +++++++++++++++++++
 3 files changed, 29 insertions(+)

diff --git a/bsp/drivers/vin/vin-mipi/combo_csi/combo_csi_reg.c b/bsp/drivers/vin/vin-mipi/combo_csi/combo_csi_reg.c
index b9698b6cb..9091e11ae 100644
--- a/bsp/drivers/vin/vin-mipi/combo_csi/combo_csi_reg.c
+++ b/bsp/drivers/vin/vin-mipi/combo_csi/combo_csi_reg.c
@@ -202,6 +202,11 @@ unsigned int cmb_phy_laneck_en_status_get(unsigned int sel)
 	return (reg_val & CMB_PHY_LANECK_EN_MASK) >> CMB_PHY_LANECK_EN;
 }
 
+void cmb_phy_reg_write(unsigned int sel, unsigned int off, unsigned int val)
+{
+	vin_reg_writel(cmb_csi_phy_base_addr[sel] + off, val);
+}
+
 void cmb_phy_lane_num_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg)
 {
 	vin_reg_clr_set(cmb_csi_phy_base_addr[sel] + CMB_PHY_CTL_REG_OFF,
diff --git a/bsp/drivers/vin/vin-mipi/combo_csi/combo_csi_reg.h b/bsp/drivers/vin/vin-mipi/combo_csi/combo_csi_reg.h
index 1a5fcd9ba..d2d2ba1a1 100644
--- a/bsp/drivers/vin/vin-mipi/combo_csi/combo_csi_reg.h
+++ b/bsp/drivers/vin/vin-mipi/combo_csi/combo_csi_reg.h
@@ -210,6 +210,7 @@ unsigned int cmb_phy_en_status_get(unsigned int sel);
 unsigned int cmb_phy_lanedt_en_status_get(unsigned int sel);
 unsigned int cmb_phy_laneck_en_status_get(unsigned int sel);
 void cmb_phy_lane_num_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg);
+void cmb_phy_reg_write(unsigned int sel, unsigned int off, unsigned int val);
 void cmb_phy0_work_mode(unsigned int sel, unsigned int mode);
 void cmb_phy0_ofscal_cfg(unsigned int sel);
 void cmb_phy_deskew_en(unsigned int sel, struct phy_lane_cfg phy_lane_cfg);
diff --git a/bsp/drivers/vin/vin-mipi/sunxi_mipi.c b/bsp/drivers/vin/vin-mipi/sunxi_mipi.c
index cc97a4706..162334c98 100644
--- a/bsp/drivers/vin/vin-mipi/sunxi_mipi.c
+++ b/bsp/drivers/vin/vin-mipi/sunxi_mipi.c
@@ -18,6 +18,7 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/delay.h>
+#include <linux/of.h>
 #include <media/v4l2-device.h>
 #include <media/v4l2-mediabus.h>
 #include <media/v4l2-subdev.h>
@@ -33,6 +34,25 @@
 
 #define IS_FLAG(x, y) (((x)&(y)) == y)
 
+#if defined MIPI_COMBO_CSI
+#define BPI_M8_CSI1_PHY_EQ		0x00ff001f
+#define BPI_M8_CSI1_PHY_DESKEW1		0x00300000
+
+static void bpi_m8_csi1_phy_tune(struct mipi_dev *mipi)
+{
+	if (!mipi || mipi->id != 1 ||
+	    !of_machine_is_compatible("allwinner,a733"))
+		return;
+
+	/*
+	 * The BPI-M8 CSI1 connector needs stronger PHY EQ and clock deskew
+	 * than the controller default for reliable 4-lane RAW10 capture.
+	 */
+	cmb_phy_reg_write(mipi->id + mipi->phy_offset, 0x004, BPI_M8_CSI1_PHY_EQ);
+	cmb_phy_reg_write(mipi->id + mipi->phy_offset, 0x018, BPI_M8_CSI1_PHY_DESKEW1);
+}
+#endif
+
 /* mipi_lane_spec[m][n]:
 * m: maximum number of mipi
 * n: fixed to 2
@@ -584,6 +604,9 @@ void cmb_phy_init(struct mipi_dev *mipi)
 	cmb_phy0_en(mipi->id + mipi->phy_offset, 1);
 	cmb_phy0_freq_en(mipi->id, 1);
 	cmb_phy_deskew1_cfg(mipi->id + mipi->phy_offset, mipi->deskew, mipi->cmb_mode == MIPI_VC_WDR_MODE ? true : false);
+#if defined MIPI_COMBO_CSI
+	bpi_m8_csi1_phy_tune(mipi);
+#endif
 }
 
 static void combo_csi_link_mode_set(struct v4l2_subdev *sd)