diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 639e01a4d..ba7b9a5de 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -30,3 +30,4 @@ subdir-y += synaptics subdir-y += ti subdir-y += toshiba subdir-y += xilinx +subdir-y += sunxi diff --git a/arch/arm64/boot/dts/sunxi/Makefile b/arch/arm64/boot/dts/sunxi/Makefile new file mode 100644 index 000000000..dd9dd12c2 --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_SUNXI) += sun60i-a733-bananapi-m8.dtb +subdir-y += overlay diff --git a/arch/arm64/boot/dts/sunxi/overlay/Makefile b/arch/arm64/boot/dts/sunxi/overlay/Makefile new file mode 100644 index 000000000..3f58be62a --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/overlay/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +subdir-y += bpi-m8 diff --git a/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/Makefile b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/Makefile new file mode 100644 index 000000000..7a99be9e1 --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtbo-$(CONFIG_ARCH_SUNXI) += board1.dtbo +dtbo-$(CONFIG_ARCH_SUNXI) += board2.dtbo +dtbo-$(CONFIG_ARCH_SUNXI) += board3.dtbo diff --git a/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board1.dts b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board1.dts new file mode 100644 index 000000000..be1119fce --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board1.dts @@ -0,0 +1,31 @@ +/dts-v1/; +/plugin/; +/ { + /* As DTS design, these properties only for loader, won't overlay */ + compatible = "board_manufacturer,board_model"; + + /* These properties are examples */ + board_id = <0x00000001>; + board_rev = <0x00000000>; + another_hw_information = "some_data"; + soc_id = <0x68000000>; + +}; + +&soc { + dtbo_version = <0x00000001>; + dtbo{ + compatible = "allwinner,sunxi-dtbo"; + dtbo_type = <1>; + }; +}; + +&twi2 { + focaltech@38{ + focaltech,display-coords = <0 0 1200 2000>; + focaltech,swap-x2y = <0>; + focaltech,revert_x = <1>; + focaltech,revert_y = <1>; + }; +}; + diff --git a/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board2.dts b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board2.dts new file mode 100644 index 000000000..222a44403 --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board2.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; +/ { + /* As DTS design, these properties only for loader, won't overlay */ + compatible = "board_manufacturer,board_model"; + + /* These properties are examples */ + board_id = <0x00000002>; + board_rev = <0x00000000>; + another_hw_information = "some_data"; + soc_id = <0x68000000>; + +}; + +&soc { + dtbo_version = <0x00000001>; + dtbo{ + compatible = "allwinner,sunxi-dtbo"; + dtbo_type = <2>; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board3.dts b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board3.dts new file mode 100644 index 000000000..0be6070f3 --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/board3.dts @@ -0,0 +1,21 @@ +/dts-v1/; +/plugin/; +/ { + /* As DTS design, these properties only for loader, won't overlay */ + compatible = "board_manufacturer,board_model"; + + /* These properties are examples */ + board_id = <0x00000003>; + board_rev = <0x00000000>; + another_hw_information = "some_data"; + soc_id = <0x68000000>; + +}; + +&soc { + dtbo_version = <0x00000001>; + dtbo{ + compatible = "allwinner,sunxi-dtbo"; + dtbo_type = <3>; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/dtboimg.cfg b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/dtboimg.cfg new file mode 100644 index 000000000..1811916f8 --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/overlay/bpi-m8/dtboimg.cfg @@ -0,0 +1,20 @@ +# global options + page_size=2048 + id=/:board_id #use .dtbo file default + rev=/:board_rev #reverser value is zero + custom0=0xabc + +#entry +board1.dtbo + id=0x00000001 + custom0=0x55551234 + custom1=0x55551234 + custom2=0x55551234 + custom3=0x55551234 + +board2.dtbo + id=0x00000002 # override the value of id in global options + +board3.dtbo + id=0x00000003 # override the value of id in global options + custom0=0x123 # override the value of custom0 in global options diff --git a/arch/arm64/boot/dts/sunxi/sun60i-a733-bananapi-m8.dts b/arch/arm64/boot/dts/sunxi/sun60i-a733-bananapi-m8.dts new file mode 100644 index 000000000..dcff5daba --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/sun60i-a733-bananapi-m8.dts @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) + +/dts-v1/; + +#include "sun60iw2p1.dtsi" +#include + +/{ + board = "A733", "A733-PRO3"; + compatible = "allwinner,a733", "arm,sun60iw2p1"; + aliases { + standby_param = &standby_param; + arisc-config = &arisc_config; + pmu0 = &pmu0; + sunxi-mmc2 = &sdc2; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bpi-m8:pwr"; + gpios = <&pio PD 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + sys-led { + label = "bpi-m8:sys"; + gpios = <&pio PD 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* CH334F downstream HOST-D1/HOST-D2 external 5V enable. */ + reg_usb_hub_d12_vbus: usb-hub-d12-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb-hub-d12-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-enable-ramp-delay = <1000>; + gpio = <&r_pio PL 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + /* HOST-D3 plus USB3 SS port external 5V enable. */ + reg_usb3_hub_d3_vbus: usb3-hub-d3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3-hub-d3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-enable-ramp-delay = <1000>; + gpio = <&r_pio PL 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + standby_param: standby_param { + vdd-cpub = <0x00000004 0x00000000>; + vdd-cpu = <0x00000010 0x00000000>; + vdd-sys = <0x00000002 0x00000000>; + vdd-gpu = <0x00000008 0x00000000>; + vdd-npu = <0x00000002 0x00000000>; + vcc-pll = <0x01000000 0x00000000>; + vcc18-hdmi = <0x00800000 0x00000000>; + avdd-h-combo = <0x04000000 0x00000000>; + vcc-io = <0x00000400 0x00000000>; + vcc25-ufs = <0x00000000 0x00000001>; + vcc18-12-ufs = <0x00000080 0x00000000>; + vcc-efuse = <0x08000000 0x00000000>; + + vdd-usb = <0x00000001>; + osc24m-on = <0>; + }; + + arisc_config: arisc_config { + s_uart_config{ + pins = "PL2", "PL3"; + function = <3>, <3>; + status = "disabled"; + }; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + status = "okay"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <73>; + pwms = <&pwm0 4 25000 0>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <1 64 128 192 255>; + pwms = <&s_pwm0 1 25000 0>; + }; + + sunxi-keyboard { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + key_vol0 { + label = "VOL+"; + gpios = <&pio PB 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key_vol1 { + label = "VOL-"; + gpios = <&pio PB 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel_0: panel_0@0 { + compatible = "allwinner,panel-dsi"; + status = "okay"; + power-delay-ms = <10>; + power-num = <2>; + power0-supply = <®_dc1sw1>; + power1-supply = <®_bldo2>; + // avdd-supply = <®_ext_ocp2131_avdd>; + // avdd-output-voltage = <6000000>; + // avee-supply = <®_ext_ocp2131_avee>; + // avee-output-voltage = <6000000>; + + gpio-num = <3>; + enable0-gpios = <&pio PH 9 GPIO_ACTIVE_HIGH>; // reset + enable1-gpios = <&pio PH 10 GPIO_ACTIVE_HIGH>; // reset + // enable2-gpios = <&pio PD 22 GPIO_ACTIVE_HIGH>; // backlight-gpio + reset-num = <2>; + reset-delay-ms = <10>; + reset-gpios = <&pio PD 21 GPIO_ACTIVE_HIGH>; //reset + backlight = <&backlight0>; + width-mm = <143>; + height-mm = <238>; + // dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_SLAVE_MODE)>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_ASYNC_INCELL)>; + dsi,lanes = <4>; + dsi,format = <0>; + panel-init-sequence = [ + 15 00 02 00 00 + 15 00 02 FA 5A + 15 00 02 00 00 + 39 00 04 FF 82 05 01 + 15 00 02 00 80 + 39 00 03 FF 82 05 + 15 00 02 00 93 + 15 00 02 C5 6B + 15 00 02 00 97 + 15 00 02 C5 6B + 15 00 02 00 9E + 15 00 02 C5 0A + 15 00 02 00 9A + 15 00 02 C5 CD + 15 00 02 00 9C + 15 00 02 C5 CD + 15 00 02 00 B6 + 39 00 03 C5 57 57 + 15 00 02 00 B8 + 39 00 03 C5 43 43 + 15 00 02 00 A0 + 15 00 02 A5 04 + 15 00 02 00 00 + 39 00 03 D8 B4 B4 + 15 00 02 00 82 + 15 00 02 C5 95 + 15 00 02 00 83 + 15 00 02 C5 07 + 15 00 02 00 D9 + 15 00 02 CB 40 + 15 00 02 00 00 + 39 00 11 E1 00 04 11 1E 27 31 41 4F 52 5F 63 79 88 73 71 65 + 15 00 02 00 10 + 39 00 09 E1 5B 4F 3E 34 2B 1E 16 15 + 15 00 02 00 00 + 39 00 11 E2 00 04 11 1E 27 31 41 4F 52 5F 63 79 88 73 71 65 + 15 00 02 00 10 + 39 00 09 E2 5B 4F 3E 34 2B 1B 0C 0A + 15 00 02 00 A1 + 39 00 03 B3 04 B0 + 15 00 02 00 A3 + 39 00 03 B3 07 D0 + 15 00 02 00 A5 + 39 00 03 B3 80 13 + 15 00 02 00 80 + 39 00 08 CB 3C 3C 3C 3C 3C 3C 3C + 15 00 02 00 87 + 15 00 02 CB 3C + 15 00 02 00 88 + 39 00 09 CB 3C 3C 3C 3C 3C 3C 3C 3C + 15 00 02 00 90 + 39 00 07 CB 03 3C 3C 3C 3C 3C + 15 00 02 00 97 + 15 00 02 CB 33 + 15 00 02 00 98 + 39 00 09 CB 34 34 34 34 34 34 34 34 + 15 00 02 00 A0 + 39 00 09 CB 34 34 34 37 34 34 34 34 + 15 00 02 00 A8 + 39 00 07 CB C8 34 34 34 34 34 + 15 00 02 00 B0 + 39 00 08 CB 00 00 00 00 00 00 00 + 15 00 02 00 B7 + 15 00 02 CB 00 + 15 00 02 00 B8 + 39 00 09 CB 00 00 00 00 00 00 00 00 + 15 00 02 00 C0 + 39 00 08 CB 00 00 00 00 00 00 00 + 15 00 02 00 C7 + 15 00 02 CB 00 + 15 00 02 00 80 + 39 00 09 CC 2F 2F 2F 27 31 32 01 2C + 15 00 02 00 88 + 39 00 09 CC 2D 1B 1D 1F 21 0B 0D 0F + 15 00 02 00 90 + 39 00 07 CC 11 13 15 03 2F 2F + 15 00 02 00 80 + 39 00 09 CD 2F 2F 2F 27 31 32 02 2C + 15 00 02 00 88 + 39 00 09 CD 2D 1C 1E 20 22 0C 0E 10 + 15 00 02 00 90 + 39 00 07 CD 12 14 16 04 2F 2F + 15 00 02 00 80 + 39 00 05 C2 8C 0A 7A AA + 15 00 02 00 84 + 39 00 05 C2 8B 0A 7A AA + 15 00 02 00 C0 + 39 00 08 C2 86 87 00 06 7A AA 0B + 15 00 02 00 C7 + 39 00 08 C2 85 86 00 06 7A AA 0B + 15 00 02 00 D0 + 39 00 08 C2 84 85 00 06 7A AA 0B + 15 00 02 00 D7 + 39 00 08 C2 83 84 00 06 7A AA 0B + 15 00 02 00 E0 + 39 00 08 C2 82 83 00 06 7A AA 0B + 15 00 02 00 E7 + 39 00 08 C2 81 82 00 06 7A AA 0B + 15 00 02 00 F0 + 39 00 08 C2 80 81 00 06 7A AA 0B + 15 00 02 00 F7 + 39 00 08 C2 01 80 00 06 7A AA 0B + 15 00 02 00 80 + 39 00 08 C3 02 8B 00 06 7A AA 0B + 15 00 02 00 87 + 39 00 08 C3 03 8A 00 06 7A AA 0B + 15 00 02 00 90 + 39 00 08 C3 04 89 00 06 7A AA 0B + 15 00 02 00 97 + 39 00 08 C3 05 88 00 06 7A AA 0B + 15 00 02 00 A0 + 39 00 05 C2 06 46 7A AA + 15 00 02 00 A4 + 39 00 05 C2 05 46 7A AA + 15 00 02 00 A8 + 39 00 05 C2 04 46 7A AA + 15 00 02 00 AC + 39 00 05 C2 03 46 7A AA + 15 00 02 00 B0 + 39 00 05 C2 02 46 7A AA + 15 00 02 00 B4 + 39 00 05 C2 01 46 7A AA + 15 00 02 00 B8 + 39 00 05 C2 00 06 7A AA + 15 00 02 00 BC + 39 00 05 C2 01 06 7A AA + 15 00 02 00 A0 + 39 00 09 C3 00 70 D3 0A 7A AA 00 00 + 15 00 02 00 A8 + 39 00 09 C3 00 70 D4 0B 7A AA 00 00 + 15 00 02 00 F0 + 39 00 06 CC 3D 8E 8E 18 18 + 15 00 02 00 A2 + 15 00 02 F3 55 + 15 00 02 00 E0 + 39 00 05 C3 27 00 00 00 + 15 00 02 00 E4 + 39 00 05 C3 27 00 00 00 + 15 00 02 00 EC + 39 00 03 C3 C2 C2 + 15 00 02 00 E8 + 39 00 05 C3 44 00 0C 70 + 15 00 02 00 EE + 15 00 02 C3 02 + 15 00 02 00 80 + 39 00 07 C0 00 8C 00 DC 00 10 + 15 00 02 00 90 + 39 00 07 C0 00 8C 00 DC 00 10 + 15 00 02 00 A0 + 39 00 07 C0 00 F0 00 DC 00 10 + 15 00 02 00 B0 + 39 00 06 C0 00 A7 00 DC 10 + 15 00 02 00 A3 + 39 00 07 C1 00 24 00 24 00 04 + 15 00 02 00 80 + 39 00 0D CE 01 81 0B 21 00 35 00 AC 00 2A 00 3A + 15 00 02 00 90 + 39 00 0F CE 00 88 0C 66 00 88 80 0B 21 00 03 00 1C 0C + 15 00 02 00 A0 + 39 00 04 CE 10 00 00 + 15 00 02 00 B0 + 39 00 04 CE 62 00 00 + 15 00 02 00 CC + 39 00 03 CE 07 F8 + 15 00 02 00 D0 + 39 00 09 CE 01 00 0F 01 01 00 DE 01 + 15 00 02 00 E1 + 39 00 08 CE 0A 01 6B 02 37 00 82 + 15 00 02 00 F0 + 39 00 0B CE 00 11 08 01 2D 01 D6 00 EC 1A + 15 00 02 00 B0 + 39 00 05 CF 07 07 DA DE + 15 00 02 00 B5 + 39 00 05 CF 03 03 A6 AA + 15 00 02 00 C0 + 39 00 05 CF 07 07 DA DE + 15 00 02 00 C5 + 39 00 05 CF 00 07 1C D0 + 15 00 02 00 90 + 15 00 02 C1 22 + 15 00 02 00 9C + 15 00 02 C1 08 + 15 00 02 00 00 + 15 00 02 35 01 + 15 00 02 00 9F + 15 00 02 C5 00 + 15 00 02 00 98 + 15 00 02 C5 54 + 15 00 02 00 91 + 15 00 02 C5 4C + 15 00 02 00 8C + 39 00 03 CF 40 40 + 15 00 02 00 93 + 15 00 02 C4 90 + 15 00 02 00 D7 + 15 00 02 C0 F0 + 15 00 02 00 A2 + 15 00 02 F5 1F + 15 00 02 00 90 + 15 00 02 E9 10 + 15 00 02 00 B1 + 15 00 02 F5 02 + 15 00 02 00 80 + 15 00 02 A4 2C + 15 00 02 00 84 + 15 00 02 C5 FD + 15 00 02 00 88 + 15 00 02 B0 07 + 15 00 02 00 00 + 15 00 02 FA 01 + 15 00 02 00 A8 + 15 00 02 C5 99 + 15 00 02 00 B6 + 39 00 03 C5 55 55 + 15 00 02 00 B8 + 39 00 03 C5 41 41 + 15 00 02 00 9A + 15 00 02 F5 00 + 15 00 02 00 B2 + 15 00 02 CE 92 + 15 00 02 00 00 + 15 00 02 FA 5A + 15 00 02 00 88 + 15 00 02 B0 01 + 15 00 02 00 00 + 39 00 04 FF 00 00 00 + 15 00 02 00 80 + 39 00 03 FF 00 00 + 15 96 02 11 00 + 15 32 02 29 00 + 15 00 02 35 00 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <171993120>; + hback-porch = <26>; + hactive = <1200>; + hfront-porch = <46>; + hsync-len = <10>; + vback-porch = <20>; + vactive = <2000>; + vfront-porch = <212>; + vsync-len = <4>; + }; + }; + port { + panel0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_output_0>; + }; + }; + }; +}; + +&ccu { + clk-init-gate = <1>; +}; + +&pio { + uart1_pins_active: uart1_pins@0 { + pins = "PG6", "PG7", "PG8", "PG9"; + function = "uart1"; + drive-strength = <10>; + bias-pull-up; + }; + + uart1_pins_sleep: uart1_pins@1 { + pins = "PG6", "PG7", "PG8", "PG9"; + function = "gpio_in"; + }; + + uart2_pins_active: uart2_pins@0 { + pins = "PB0", "PB1", "PB2", "PB3"; + function = "uart2"; + drive-strength = <10>; + }; + + uart2_pins_sleep: uart2_pins@1 { + pins = "PB0", "PB1", "PB2", "PB3"; + function = "io_disabled"; + drive-strength = <10>; + }; + + uart4_pins_active: uart4_pins@0 { + pins = "PJ24", "PJ25", "PJ26", "PJ27"; + function = "uart4"; + drive-strength = <10>; + }; + + uart4_pins_sleep: uart4_pins@1 { + pins = "PJ24", "PJ25", "PJ26", "PJ27"; + function = "io_disabled"; + drive-strength = <10>; + }; + + uart5_pins_active: uart5_pins@0 { + pins = "PH13", "PH14", "PH15", "PH16"; + function = "uart5"; + drive-strength = <10>; + }; + + uart5_pins_sleep: uart5_pins@1 { + pins = "PH13", "PH14", "PH15", "PH16"; + function = "io_disabled"; + drive-strength = <10>; + }; + + uart6_pins_active: uart6_pins@0 { + pins = "PK0", "PK1", "PK2", "PK3"; + function = "uart6"; + drive-strength = <10>; + }; + + uart6_pins_sleep: uart6_pins@1 { + pins = "PK0", "PK1", "PK2", "PK3"; + function = "io_disabled"; + drive-strength = <10>; + }; + + uart7_pins_active: uart7_pins@0 { + pins = "PL10", "PL11"; + function = "uart7"; + drive-strength = <10>; + }; + + uart7_pins_sleep: uart7_pins@1 { + pins = "PL10", "PL11"; + function = "io_disabled"; + drive-strength = <10>; + }; + + uart8_pins_active: uart8_pins@0 { + pins = "PL2", "PL3"; + function = "uart8"; + drive-strength = <10>; + }; + + uart8_pins_sleep: uart8_pins@1 { + pins = "PL2", "PL3"; + function = "io_disabled"; + drive-strength = <10>; + }; + + twi1_pins_default: twi1@0 { + pins = "PH2", "PH3"; + function = "twi1"; + drive-strength = <10>; + bias-pull-up; + }; + + twi1_pins_sleep: twi1@1 { + pins = "PH2", "PH3"; + function = "gpio_in"; + }; + + twi2_pins_default: twi2@0 { + pins = "PD16", "PD17"; + function = "twi2"; + drive-strength = <10>; + bias-pull-up; + }; + + twi2_pins_sleep: twi2@1 { + pins = "PD16", "PD17"; + function = "gpio_in"; + }; + + twi3_pins_default: twi3@0 { + pins = "PE3", "PE4"; + function = "twi3"; + drive-strength = <10>; + bias-pull-up; + }; + + twi3_pins_sleep: twi3@1 { + pins = "PE3", "PE4"; + function = "gpio_in"; + }; + + twi4_pins_default: twi4@0 { + pins = "PE10", "PE11"; + function = "twi4"; + drive-strength = <10>; + bias-pull-up; + }; + + twi4_pins_sleep: twi4@1 { + pins = "PE10", "PE11"; + function = "gpio_in"; + }; + + pwm0_4_pins_active: pwm0@0 { + pins = "PD22"; + function = "pwm0_4"; + }; + + pwm0_4_pins_sleep: pwm0@1 { + pins = "PD22"; + function = "gpio_in"; + bias-pull-down; + }; + + gmac0_pins_default: gmac0@0 { + pins = "PH0", "PH1", "PH2", "PH3", + "PH4", "PH5", "PH6", "PH7", + "PH8", "PH9", "PH10", "PH11", + "PH12","PH13", "PH14", "PH15"; + function = "rgmii0"; + drive-strength = <40>; + bias-pull-up; + }; + + gmac0_pins_sleep: gmac0@1 { + pins = "PH0", "PH1", "PH2", "PH3", + "PH4", "PH5", "PH6", "PH7", + "PH8", "PH9", "PH10", "PH11", + "PH12","PH13", "PH14", "PH15"; + function = "io_disabled"; + }; + + /* i2s0 pins */ + i2s0_pins_a: i2s0@0 { + pins = "PB4"; + function = "i2s0_mclk"; + drive-strength = <10>; + bias-disable; + }; + + i2s0_pins_b: i2s0@1 { + pins = "PB5"; + function = "i2s0_bclk"; + drive-strength = <10>; + bias-disable; + }; + + i2s0_pins_c: i2s0@2 { + pins = "PB6"; + function = "i2s0_lrck"; + drive-strength = <10>; + bias-disable; + }; + + i2s0_pins_d: i2s0@3 { + pins = "PB7"; + function = "i2s0_dout0"; + drive-strength = <10>; + bias-disable; + }; + + i2s0_pins_e: i2s0@4 { + pins = "PB8"; + function = "i2s0_din0"; + drive-strength = <10>; + bias-pull-down; + }; + + i2s0_pins_f: i2s0@5 { + pins = "PB4", "PB5", "PB6", "PB7", "PB8"; + function = "io_disabled"; + drive-strength = <10>; + bias-disable; + }; + + /* i2s1 pins */ + i2s1_pins_a: i2s1@1 { + pins = "PG11"; + function = "i2s1_bclk"; + drive-strength = <20>; + bias-disable; + }; + + i2s1_pins_b: i2s1@2 { + pins = "PG12"; + function = "i2s1_lrck"; + drive-strength = <20>; + bias-disable; + }; + + i2s1_pins_c: i2s1@3 { + pins = "PG13"; + function = "i2s1_dout0"; + drive-strength = <20>; + bias-disable; + }; + + i2s1_pins_d: i2s1@4 { + pins = "PG14"; + function = "i2s1_din0"; + drive-strength = <20>; + bias-disable; + }; + + i2s1_pins_e: i2s1@5 { + pins = "PG11", "PG12", "PG13", "PG14"; + function = "io_disabled"; + drive-strength = <20>; + bias-disable; + }; + + ledc_pins_a: ledc@0 { + pins = "PE4"; + function = "ledc"; + drive-strength = <10>; + }; + + ledc_pins_b: ledc@1 { + pins = "PE4"; + function = "gpio_in"; + }; +}; + +&r_pio { + twi13_pins_default: twi13@0 { + pins = "PL0", "PL1"; + function = "s_twi0"; + drive-strength = <10>; + bias-pull-up; + }; + + twi13_pins_sleep: twi13@1 { + pins = "PL0", "PL1"; + function = "gpio_in"; + }; + + s_twi1_pins_default: s_twi1@0 { + pins = "PL8", "PL9"; + function = "s_twi1"; + drive-strength = <10>; + bias-pull-up; + }; + + s_twi1_pins_sleep: s_twi1@1 { + pins = "PL8", "PL9"; + function = "gpio_in"; + }; + + s_twi2_pins_default: s_twi2@0 { + pins = "PL10", "PL11"; + function = "s_twi2"; + drive-strength = <10>; + bias-pull-up; + }; + + s_twi2_pins_sleep: s_twi2@1 { + pins = "PL10", "PL11"; + function = "gpio_in"; + }; + + s_pwm0_1_pins_active: s_pwm0@0 { + pins = "PM5"; + function = "s_pwm0_1"; + drive-strength = <10>; + }; + + s_pwm0_1_pins_sleep: s_pwm0@1 { + pins = "PM5"; + function = "gpio_in"; + bias-pull-down; + }; +}; + +&soc { + auto_print@54321 { + reg = <0x0 0x54321 0x0 0x0>; + device_type = "auto_print"; + status = "okay"; + }; +}; + +&msgbox { + status = "okay"; +}; + +&hwspinlock { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_pins_active>; + pinctrl-1 = <&uart1_pins_sleep>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_pins_active>; + pinctrl-1 = <&uart2_pins_sleep>; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart4_pins_active>; + pinctrl-1 = <&uart4_pins_sleep>; + status = "disabled"; +}; + +&uart5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart5_pins_active>; + pinctrl-1 = <&uart5_pins_sleep>; + status = "disabled"; +}; + +&uart6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart6_pins_active>; + pinctrl-1 = <&uart6_pins_sleep>; + status = "disabled"; +}; + +&uart7 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart7_pins_active>; + pinctrl-1 = <&uart7_pins_sleep>; + status = "disabled"; +}; + +&uart8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart8_pins_active>; + pinctrl-1 = <&uart8_pins_sleep>; + status = "disabled"; +}; + +&sdc2 { + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + /* HS400/200MHz is unstable on BPI-M8 eMMC. */ + /*mmc-hs400-1_8v;*/ + no-sdio; + no-sd; + ctl-spec-caps = <0x328>; + cap-mmc-highspeed; + sunxi-power-save-mode; + sunxi-dis-signal-vol-sw; + mmc-bootpart-noacc; + /*cap-hsq;*/ + /* CQE is disabled for BPI-M8 eMMC stability. */ + /*cqe-on;*/ + /*ctl-cmdq-md = <0x2>;*/ + max-frequency = <150000000>; + /*vmmc-supply = <®_cldo3>;*/ + /*emmc io vol 3.3v*/ + /*vqmmc-supply = <®_aldo1>;*/ + /*emmc io vol 1.8v*/ + /*vqmmc-supply = <®_cldo1>;*/ + status = "okay"; +}; + +&sdc3 { + status = "disabled"; +}; + +&sdc0 { + bus-width = <4>; + cd-gpios = <&pio PF 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + /*data3-detect;*/ + /*card-pwr-gpios = <&pio PH 14 1 1 2 0xffffffff>;*/ + cd-used-24M; + cd-set-debounce = <0x1>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + no-sdio; + no-mmc; + sunxi-power-save-mode; + /*sunxi-dis-signal-vol-sw;*/ + max-frequency = <150000000>; + ctl-spec-caps = <0x428>; + /*vmmc-supply = <®_cldo3>;*/ + /*vqmmc33sw-supply = <®_cldo3>;*/ + /*vdmmc33sw-supply = <®_cldo3>;*/ + /*vqmmc18sw-supply = <®_cldo1>;*/ + /*vdmmc18sw-supply = <®_cldo1>;*/ + status = "okay"; +}; + +&sdc1 { + bus-width = <4>; + no-mmc; + no-sd; + cap-sd-highspeed; + /*sd-uhs-sdr12*/ + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; + /*sunxi-power-save-mode;*/ + sunxi-dis-signal-vol-sw; + cap-sdio-irq; + keep-power-in-suspend; + ignore-pm-notify; + /* + * For AIC Wi-Fi SDIO3.0, + * when max-frequency = <208000000>, set sunxi-dly-208M = <0 0 0 0 0 0> + * when max-frequency = <150000000>, set sunxi-dly-208M = <1 1 0 0 1 1> + */ + max-frequency = <208000000>; + sunxi-dly-208M = <0 0 0 0 0 0>; + ctl-spec-caps = <0x428>; + status = "okay"; +}; + +/* + * usb_port_type: usb mode. 0-device, 1-host, 2-otg. + * usb_detect_type: usb hotplug detect mode. 0-none, 1-vbus/id detect, 2-pmu detect, 3-tcpm detect. + * usb_detect_mode: 0-thread scan, 1-id gpio interrupt, 2-pmu notify. + * usb_id_gpio: gpio for id detect. + * usb_det_vbus_gpio: gpio for id detect. gpio or "axp_ctrl". + * usb_wakeup_suspend：0-SUPER_STANDBY, 1-USB_STANDBY. + */ +&usbc0 { + device_type = "usbc0"; + usb_port_type = <0x0>; + usb_detect_type = <0x2>; + usb_detect_mode = <0x2>; + usb_id_gpio; + usb_det_vbus_gpio = "axp_ctrl"; + detvbus_io-supply = <®_cldo1>; + usb_regulator_io = "nocare"; + usb_wakeup_suspend = <0>; + usb_luns = <3>; + usb_serial_unique = <0>; + usb_serial_number = "20080411"; + rndis_wceis = <1>; + status = "okay"; +}; + +&udc { + phy_range = <0x188>; + status = "okay"; +}; + +&ehci0 { + phy_range = <0x188>; + status = "okay"; +}; + +&ohci0 { + phy_range = <0x188>; + status = "okay"; +}; + +&usbc1 { + device_type = "usbc1"; + usb_regulator_io = "nocare"; + usb_wakeup_suspend = <0>; + status = "okay"; +}; + +&ehci1 { + phy_range = <0x188>; + drvvbus-supply = <®_usb3_hub_d3_vbus>; + status = "okay"; +}; + +&ohci1 { + phy_range = <0x188>; + drvvbus-supply = <®_usb3_hub_d3_vbus>; + status = "okay"; +}; + +&usbc2 { + device_type = "usbc2"; + drvvbus-supply = <®_usb3_hub_d3_vbus>; + status = "okay"; +}; + +&xhci2 { + dr_mode = "host"; + drvvbus-supply = <®_usb3_hub_d3_vbus>; + phys = <&u2phy>, <&combo0_usb>; + phy-names = "usb2-phy", "usb3-phy"; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&serdes { + serdes1v8-supply = <®_cldo5>; + status = "okay"; +}; + +&twi1 { + clock-frequency = <400000>; + pinctrl-0 = <&twi1_pins_default>; + pinctrl-1 = <&twi1_pins_sleep>; + pinctrl-names = "default", "sleep"; + /* For stability and backwards compatibility, we recommend setting ‘twi_drv_used’ to 1 */ + twi_drv_used = <1>; + twi-supply = <®_dc1sw2>; + status = "disabled"; +}; + +&twi2 { + clock-frequency = <400000>; + pinctrl-0 = <&twi2_pins_default>; + pinctrl-1 = <&twi2_pins_sleep>; + pinctrl-names = "default", "sleep"; + /* For stability and backwards compatibility, we recommend setting ‘twi_drv_used’ to 1 */ + twi_drv_used = <1>; + twi-supply = <®_bldo2>; + status = "okay"; +}; + +&s_twi2 { + clock-frequency = <400000>; + pinctrl-0 = <&s_twi2_pins_default>; + pinctrl-1 = <&s_twi2_pins_sleep>; + pinctrl-names = "default", "sleep"; + /* For stability and backwards compatibility, we recommend setting ‘twi_drv_used’ to 1 */ + twi_drv_used = <1>; + no_suspend = <1>; + status = "okay"; + + ac101: ac101@1a { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-ac101"; + reg = <0x1a>; + pllclk-src = "MCLK"; + sysclk-src = "MCLK"; + pcm-bit-first = "MSB"; + frame-sync-width = <1>; + + reset-gpios = <&pio PD 10 GPIO_ACTIVE_LOW>; + irq-gpio = <&pio PD 11 GPIO_ACTIVE_LOW>; + hp-det-gpio = <&r_pio PL 4 GPIO_ACTIVE_HIGH>; + jack-det-gpio = <&r_pio PL 4 GPIO_ACTIVE_HIGH>; + jack-det-gpio-level = <1>; + jack-swpin-max = <3>; + jack-swpin-0 = <&pio PH 6 GPIO_ACTIVE_HIGH>; + jack-swpin-1 = <&pio PH 8 GPIO_ACTIVE_HIGH>; + jack-swpin-2 = <&pio PH 7 GPIO_ACTIVE_HIGH>; + jack-mode-off = <0xf 0 0>; + jack-mode-usb = <0xf 1 1>; + jack-mode-hp = <0xf 1 0>; + jack-mode-micn = <1 0xf 0xf>; + jack-mode-mici = <0 0xf 0xf>; + jack-det-level = <1>; + jack-det-threshold = <1>; + jack-key-det-threshold = <10>; + jack-det-debouce-time = <15>; + jack-key-det-debouce-time = <2>; + + /* jack-key-det-voltage = */ + jack-key-det-voltage-hook = <23 24>; + jack-key-det-voltage-up = <21 22>; + jack-key-det-voltage-down = <18 20>; + // jack-key-det-voltage-voice = <1 1>; + + /* rglt */ + rglt-max = <2>; + rglt0-mode = "PMU"; + rglt0-voltage = <3300000>; + rglt0-supply = <®_aldo5>; + + rglt1-mode = "PMU"; + rglt1-voltage = <1800000>; + rglt1-supply = <®_bldo4>; + + status = "okay"; + }; +}; + +&twi3 { + clock-frequency = <400000>; + pinctrl-0 = <&twi3_pins_default>; + pinctrl-1 = <&twi3_pins_sleep>; + pinctrl-names = "default", "sleep"; + /* For stability and backwards compatibility, we recommend setting ‘twi_drv_used’ to 1 */ + twi_drv_used = <1>; + //twi-supply = <®_bldo1>; + status = "okay"; +}; + +&twi4 { + clock-frequency = <400000>; + pinctrl-0 = <&twi4_pins_default>; + pinctrl-1 = <&twi4_pins_sleep>; + pinctrl-names = "default", "sleep"; + /* For stability and backwards compatibility, we recommend setting ‘twi_drv_used’ to 1 */ + twi_drv_used = <1>; + //twi-supply = <®_bldo1>; + status = "okay"; +}; + +&s_twi0 { + clock-frequency = <400000>; + pinctrl-0 = <&twi13_pins_default>; + pinctrl-1 = <&twi13_pins_sleep>; + pinctrl-names = "default", "sleep"; + /* For stability and backwards compatibility, we recommend setting ‘twi_drv_used’ to 1 */ + twi_drv_used = <1>; + //twi-supply = <®_aldo1>; + no_suspend = <1>; + status = "okay"; + + pmu0: pmu@36 { + compatible = "x-powers,axp8191"; + reg = <0x36>; + status = "okay"; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&nmi_intc>; + pmu_irq_wakeup = <1>; + pmu_hot_shutdown = <1>; + + powerkey1: powerkey@1 { + compatible = "x-powers,axp2101-pek"; + status = "okay"; + pmu_powkey_off_en = <1>; + pmu_powkey_off_func = <1>; + pmu_powkey_off_time = <6000>; + pmu_powkey_long_time = <1500>; + pmu_powkey_on_time = <1000>; + wakeup_rising; + wakeup_falling; + }; + + power_temp_ctrl0: power_temp_ctrl@0 { + compatible = "x-powers,axp8191-temp-ctrl"; + status = "disabled"; + }; + + regulator0: regulators@0 { + reg_dcdc1: dcdc1 { + regulator-name = "axp8191-dcdc1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3800000>; + regulator-enable-ramp-delay = <1000>; + regulator-ramp-delay = <250>; + regulator-boot-on; + regulator-always-on; + }; + reg_dcdc2: dcdc2 { + regulator-name = "axp8191-dcdc2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-ramp-delay = <250>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dcdc3: dcdc3 { + regulator-name = "axp8191-dcdc3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-ramp-delay = <250>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dcdc4: dcdc4 { + regulator-name = "axp8191-dcdc4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-ramp-delay = <250>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dcdc5: dcdc5 { + regulator-name = "axp8191-dcdc5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-ramp-delay = <250>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dcdc6: dcdc6 { + regulator-name = "axp8191-dcdc6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2760000>; + regulator-ramp-delay = <250>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dcdc7: dcdc7 { + regulator-name = "axp8191-dcdc7"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1840000>; + regulator-ramp-delay = <250>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dcdc8: dcdc8 { + regulator-name = "axp8191-dcdc8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-ramp-delay = <250>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dcdc9: dcdc9 { + regulator-name = "axp8191-dcdc9"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-ramp-delay = <250>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_rtcldo: rtcldo { + /* RTC_LDO is a fixed, always-on regulator */ + regulator-name = "axp8191-rtcldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_aldo1: aldo1 { + regulator-name = "axp8191-aldo1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_aldo2: aldo2 { + regulator-name = "axp8191-aldo2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_aldo3: aldo3 { + regulator-name = "axp8191-aldo3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_aldo4: aldo4 { + regulator-name = "axp8191-aldo4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_aldo5: aldo5 { + regulator-name = "axp8191-aldo5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_aldo6: aldo6 { + regulator-name = "axp8191-aldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_bldo1: bldo1 { + regulator-name = "axp8191-bldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_bldo2: bldo2 { + regulator-name = "axp8191-bldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_bldo3: bldo3 { + regulator-name = "axp8191-bldo3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_bldo4: bldo4 { + regulator-name = "axp8191-bldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_bldo5: bldo5 { + regulator-name = "axp8191-bldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_cldo1: cldo1 { + regulator-name = "axp8191-cldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_cldo2: cldo2 { + regulator-name = "axp8191-cldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_cldo3: cldo3 { + regulator-name = "axp8191-cldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_cldo4: cldo4 { + regulator-name = "axp8191-cldo4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_cldo5: cldo5 { + regulator-name = "axp8191-cldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dldo1: dldo1 { + regulator-name = "axp8191-dldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dldo2: dldo2 { + regulator-name = "axp8191-dldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dldo3: dldo3 { + regulator-name = "axp8191-dldo3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_dldo4: dldo4 { + regulator-name = "axp8191-dldo4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_dldo5: dldo5 { + regulator-name = "axp8191-dldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_dldo6: dldo6 { + regulator-name = "axp8191-dldo6"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_eldo1: eldo1 { + regulator-name = "axp8191-eldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_eldo2: eldo2 { + regulator-name = "axp8191-eldo2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + regulator-boot-on; + regulator-always-on; + }; + reg_eldo3: eldo3 { + regulator-name = "axp8191-eldo3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_eldo4: eldo4 { + regulator-name = "axp8191-eldo4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_eldo5: eldo5 { + regulator-name = "axp8191-eldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + reg_eldo6: eldo6 { + regulator-name = "axp8191-eldo6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-enable-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + }; + reg_dc1sw1: dc1sw1 { + regulator-name = "axp8191-dc1sw1"; + swin-supply = <®_dcdc1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + reg_dc1sw2: dc1sw2 { + regulator-name = "axp8191-dc1sw2"; + swin-supply = <®_dcdc1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + + virtual-dcdc1 { + compatible = "xpower-vregulator,dcdc1"; + dcdc1-supply = <®_dcdc1>; + }; + virtual-dcdc2 { + compatible = "xpower-vregulator,dcdc2"; + dcdc2-supply = <®_dcdc2>; + }; + virtual-dcdc3 { + compatible = "xpower-vregulator,dcdc3"; + dcdc3-supply = <®_dcdc3>; + }; + virtual-dcdc4 { + compatible = "xpower-vregulator,dcdc4"; + dcdc4-supply = <®_dcdc4>; + }; + virtual-dcdc5 { + compatible = "xpower-vregulator,dcdc5"; + dcdc5-supply = <®_dcdc5>; + }; + virtual-dcdc6 { + compatible = "xpower-vregulator,dcdc6"; + dcdc6-supply = <®_dcdc6>; + }; + virtual-dcdc7 { + compatible = "xpower-vregulator,dcdc7"; + dcdc7-supply = <®_dcdc7>; + }; + virtual-dcdc8 { + compatible = "xpower-vregulator,dcdc8"; + dcdc8-supply = <®_dcdc8>; + }; + virtual-dcdc9 { + compatible = "xpower-vregulator,dcdc9"; + dcdc9-supply = <®_dcdc9>; + }; + virtual-rtcldo { + compatible = "xpower-vregulator,rtcldo"; + rtcldo-supply = <®_rtcldo>; + }; + virtual-aldo1 { + compatible = "xpower-vregulator,aldo1"; + aldo1-supply = <®_aldo1>; + }; + virtual-aldo2 { + compatible = "xpower-vregulator,aldo2"; + aldo2-supply = <®_aldo2>; + }; + virtual-aldo3 { + compatible = "xpower-vregulator,aldo3"; + aldo3-supply = <®_aldo3>; + }; + virtual-aldo4 { + compatible = "xpower-vregulator,aldo4"; + aldo4-supply = <®_aldo4>; + }; + virtual-aldo5 { + compatible = "xpower-vregulator,aldo5"; + aldo5-supply = <®_aldo5>; + }; + virtual-aldo6 { + compatible = "xpower-vregulator,aldo6"; + aldo6-supply = <®_aldo6>; + }; + virtual-bldo1 { + compatible = "xpower-vregulator,bldo1"; + bldo1-supply = <®_bldo1>; + }; + virtual-bldo2 { + compatible = "xpower-vregulator,bldo2"; + bldo2-supply = <®_bldo2>; + }; + virtual-bldo3 { + compatible = "xpower-vregulator,bldo3"; + bldo3-supply = <®_bldo3>; + }; + virtual-bldo4 { + compatible = "xpower-vregulator,bldo4"; + bldo4-supply = <®_bldo4>; + }; + virtual-bldo5 { + compatible = "xpower-vregulator,bldo5"; + bldo5-supply = <®_bldo5>; + }; + virtual-cldo1 { + compatible = "xpower-vregulator,cldo1"; + cldo1-supply = <®_cldo1>; + }; + virtual-cldo2 { + compatible = "xpower-vregulator,cldo2"; + cldo2-supply = <®_cldo2>; + }; + virtual-cldo3 { + compatible = "xpower-vregulator,cldo3"; + cldo3-supply = <®_cldo3>; + }; + virtual-cldo4 { + compatible = "xpower-vregulator,cldo4"; + cldo4-supply = <®_cldo4>; + }; + virtual-cldo5 { + compatible = "xpower-vregulator,cldo5"; + cldo5-supply = <®_cldo5>; + }; + virtual-dldo1 { + compatible = "xpower-vregulator,dldo1"; + dldo1-supply = <®_dldo1>; + }; + virtual-dldo2 { + compatible = "xpower-vregulator,dldo2"; + dldo2-supply = <®_dldo2>; + }; + virtual-dldo3 { + compatible = "xpower-vregulator,dldo3"; + dldo3-supply = <®_dldo3>; + }; + virtual-dldo4 { + compatible = "xpower-vregulator,dldo4"; + dldo4-supply = <®_dldo4>; + }; + virtual-dldo5 { + compatible = "xpower-vregulator,dldo5"; + dldo5-supply = <®_dldo5>; + }; + virtual-dldo6 { + compatible = "xpower-vregulator,dldo6"; + dldo6-supply = <®_dldo6>; + }; + virtual-eldo1 { + compatible = "xpower-vregulator,eldo1"; + eldo1-supply = <®_eldo1>; + }; + virtual-eldo2 { + compatible = "xpower-vregulator,eldo2"; + eldo2-supply = <®_eldo2>; + }; + virtual-eldo3 { + compatible = "xpower-vregulator,eldo3"; + eldo3-supply = <®_eldo3>; + }; + virtual-eldo4 { + compatible = "xpower-vregulator,eldo4"; + eldo4-supply = <®_eldo4>; + }; + virtual-eldo5 { + compatible = "xpower-vregulator,eldo5"; + eldo5-supply = <®_eldo5>; + }; + virtual-eldo6 { + compatible = "xpower-vregulator,eldo6"; + eldo6-supply = <®_eldo6>; + }; + virtual-dc1sw1 { + compatible = "xpower-vregulator,dc1sw1"; + dc1sw-supply = <®_dc1sw1>; + }; + virtual-dc1sw2 { + compatible = "xpower-vregulator,dc1sw2"; + dc1sw-supply = <®_dc1sw2>; + }; + }; +}; + +&s_twi1 { + clock-frequency = <400000>; + pinctrl-0 = <&s_twi1_pins_default>; + pinctrl-1 = <&s_twi1_pins_sleep>; + pinctrl-names = "default", "sleep"; + /* For stability and backwards compatibility, we recommend setting 'twi_drv_used' to 1 */ + twi_drv_used = <1>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <8>; + wp-gpios = <&pio PC 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&pwm0_4 { + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&pwm0_4_pins_active>; + pinctrl-1 = <&pwm0_4_pins_sleep>; + status = "okay"; +}; + +&s_pwm0_1 { + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&s_pwm0_1_pins_active>; + pinctrl-1 = <&s_pwm0_1_pins_sleep>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&cpul_thermal_zone { + cooling-maps { + map1 { + trip = <&cpul_threshold>; + cooling-device = <&fan0 0 THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; +}; + +&cpub_thermal_zone { + cooling-maps { + map1 { + trip = <&cpub_threshold>; + cooling-device = <&fan0 0 THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; +}; + +&rfkill { + compatible = "allwinner,sunxi-rfkill"; + status = "okay"; + chip_en = <&pio PG 10 GPIO_ACTIVE_HIGH>; + + /* wlan session */ + wlan { + compatible = "allwinner,sunxi-wlan"; + clocks; + clock-names; + wlan_power = "axp8191-dcdc1", "axp8191-bldo5", "axp8191-cldo1"; /* vcc-wifi/vcc-pg/vcc-pm */ + wlan_power_vol= <3300000>, <1800000>, <1800000>; + wlan_busnum = <0x1>; + wlan_regon = <&r_pio PM 1 GPIO_ACTIVE_HIGH>; + wlan_hostwake = <&r_pio PM 0 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + /* bt session */ + bt { + compatible = "allwinner,sunxi-bt"; + clocks; + clock-names; + bt_power = "axp8191-dcdc1", "axp8191-bldo5", "axp8191-cldo1"; /* vcc-wifi/vcc-pg/vcc-pm */ + bt_power_vol= <3300000>, <1800000>, <1800000>; + bt_rst_n = <&r_pio PM 2 GPIO_ACTIVE_LOW>; + }; +}; + +&addr_mgt { + compatible = "allwinner,sunxi-addr_mgt"; + type_addr_wifi = <0x0>; + type_addr_bt = <0x0>; + type_addr_eth = <0x0>; + status = "okay"; +}; + +&btlpm { + compatible = "allwinner,sunxi-btlpm"; + uart_index = <0x1>; + bt_wake = <&r_pio PM 3 GPIO_ACTIVE_HIGH>; + bt_hostwake = <&r_pio PM 4 GPIO_ACTIVE_HIGH>; + wakeup-source; + status = "okay"; +}; + +&de { + assigned-clock-rates = <600000000>; + chn_cfg_mode = <2>; + status = "okay"; +}; + +&vo0 { + status = "okay"; +}; + +&vo1 { + status = "okay"; +}; + +&tv0 { + status = "okay"; +}; + +&tv1 { + status = "okay"; +}; + +&dlcd0 { + status = "disabled"; +}; + +&dsi0 { + status = "disabled"; + pinctrl-0 = <&dsi0_4lane_pins_a>; + pinctrl-1 = <&dsi0_4lane_pins_b>; + pinctrl-names = "active","sleep"; + + ports { + dsi0_out: port@1{ + dsi_out_panel: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + panel: panel@0 { + // panel-out-reg = <0x00000001>; /* TODO: need to be fixed in the uboot */ + compatible = "allwinner,virtual-panel"; + status = "okay"; + reg = <0>; + ports { + panel_in: port@0 { + reg = <0>; + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_out_panel>; + }; + }; + panel_out: port@1 { + reg = <1>; + panel_output_0: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel0_in>; + }; + }; + }; + }; +}; + +&dsi0combophy { + status = "okay"; +}; + +&lradc { + key_cnt = <2>; + key0 = <646 115>; + key1 = <900 114>; + status = "disabled"; +}; + +&hdmi0 { + dcdc2-supply = <®_dcdc2>; + cldo2-supply = <®_cldo2>; + hdmi_power0 = "dcdc2"; + hdmi_power1 = "cldo2"; + hdmi_power_cnt = <2>; + + hdmi_hdcp1x_enable = <0>; + hdmi_hdcp2x_enable = <0>; + hdmi_cec_enable = <0>; + hdmi_clock_source = <0>; + hdmi_resistor_select = <1>; + hdmi_ddc_index = <20>; + priority = <6>; + + force-output = <0>; + force-output-timing = "440000-3440-3450-4500-4800-1440-1455-1464-1494"; + + snps_phy = < + 25000 185625 0x0007 0x8160 0x8188 + 185625 185625 0x0007 0x8160 0x8198 + 185625 340000 0x0004 0x8040 0x8E85 + 340000 600000 0x0000 0x80c0 0x82F6>; + + status = "okay"; +}; + +&gmac0_phy0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + max-speed = <1000>; + reset-gpios = <&pio PH 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <150000>; + realtek,led1-link-led2-activity; +}; + +&gmac0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&gmac0_pins_default>; + pinctrl-1 = <&gmac0_pins_sleep>; + phy-mode = "rgmii"; + aw,soc-phy25m; + tx-delay = <12>; + rx-delay = <21>; + dwmac3v3-supply = <®_dc1sw2>; + phy3v3-supply = <®_dc1sw2>; + status = "okay"; +}; + +&hdmi_codec { + extcon = <&hdmi0>; + status = "okay"; +}; + +/* audio dirver module -> I2S/PCM */ +&i2s0_plat { + tdm-num = <0>; + tx-pin = <0>; + rx-pin = <0>; + + pinctrl-used; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2s0_pins_a &i2s0_pins_b &i2s0_pins_c &i2s0_pins_d &i2s0_pins_e>; + pinctrl-1 = <&i2s0_pins_f>; + + tx-hub-en; + rx-sync-en; + status = "okay"; +}; + +&i2s0_mach { + soundcard-mach,format = "i2s"; + soundcard-mach,frame-master = <&i2s0_cpu>; + soundcard-mach,bitclock-master = <&i2s0_cpu>; + /* soundcard-mach,frame-inversion; */ + /* soundcard-mach,bitclock-inversion; */ + soundcard-mach,slot-num = <4>; + soundcard-mach,slot-width = <16>; + soundcard-mach,jack-support = <4>; + soundcard-mach,widgets = "Microphone", "HS MIC Jack", + "Headphone", "HP Jack"; + soundcard-mach,pin-switches = "MIC1", "MIC2", + "LINEINL","LINEINR", + "HPOUTL","HPOUTR", + "LINEOUTL","LINEOUTR", + "SPK"; + soundcard-mach,routing = "MIC1P_PIN", "MIC1", + "MIC1N_PIN", "MIC1", + "MIC2P_PIN", "MIC2", + "MIC2N_PIN", "MIC2", + "LINEINL_PIN", "LINEINL", + "LINEINR_PIN", "LINEINR", + "LINEOUTL", "LINEOUTLP_PIN", + "LINEOUTL", "LINEOUTLN_PIN", + "LINEOUTR", "LINEOUTRP_PIN", + "LINEOUTR", "LINEOUTRN_PIN", + "SPK", "LINEOUTLP_PIN", + "SPK", "LINEOUTLN_PIN", + "SPK", "LINEOUTRP_PIN", + "SPK", "LINEOUTRN_PIN", + "HPOUTL", "HPOUTL_PIN", + "HPOUTR", "HPOUTR_PIN"; + status = "okay"; + i2s0_cpu: soundcard-mach,cpu { + sound-dai = <&i2s0_plat>; + /* note: pll freq = 24.576M or 22.5792M * pll-fs */ + soundcard-mach,pll-fs = <1>; + soundcard-mach,mclk-fs = <2>; + soundcard-mach,mclk-fp = <11289600 12288000>; + }; + i2s0_codec: soundcard-mach,codec { + sound-dai = <&ac101>; + }; +}; + +&i2s1_plat { + tdm-num = <1>; + tx-pin = <0>; + rx-pin = <0>; + + pinctrl-used; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2s1_pins_a &i2s1_pins_b &i2s1_pins_c &i2s1_pins_d>; + pinctrl-1 = <&i2s1_pins_e>; + + tx-hub-en; + rx-sync-en; + status = "okay"; +}; + + + + +&i2s3_plat { + tdm-num = <3>; + tx-pin = <0 1 2 3>; + tx-pin0-map0 = <0x76543210>; + tx-pin0-map1 = <0xFEDCBA98>; + tx-pin1-map0 = <0x76543210>; + tx-pin1-map1 = <0xFEDCBA98>; + tx-pin2-map0 = <0x76543210>; + tx-pin2-map1 = <0xFEDCBA98>; + tx-pin3-map0 = <0x76543210>; + tx-pin3-map1 = <0xFEDCBA98>; + rx-pin = <0>; + + tx-hub-en; + rx-sync-en; + dai-type = "hdmi"; + status = "okay"; +}; + +&i2s3_mach { + soundcard-mach,format = "i2s"; + soundcard-mach,frame-master = <&i2s3_cpu>; + soundcard-mach,bitclock-master = <&i2s3_cpu>; + /* soundcard-mach,frame-inversion; */ + /* soundcard-mach,bitclock-inversion; */ + soundcard-mach,name = "allwinner-hdmi"; + soundcard-mach,slot-num = <2>; + soundcard-mach,slot-width = <32>; + status = "okay"; + i2s3_cpu: soundcard-mach,cpu { + sound-dai = <&i2s3_plat>; + soundcard-mach,pll-fs = <1>; + soundcard-mach,mclk-fs = <0>; + }; + i2s3_codec: soundcard-mach,codec { + sound-dai = <&hdmi_codec>; + }; +}; + +&ledc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ledc_pins_a>; + pinctrl-1 = <&ledc_pins_b>; + led_count = <34>; + output_mode = "GRB"; + reset_ns = <84>; + t1h_ns = <800>; + t1l_ns = <320>; + t0h_ns = <300>; + t0l_ns = <800>; + wait_time0_ns = <84>; + wait_time1_ns = <84>; + wait_data_time_ns = <600000>; + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <®_dcdc5>; +}; + +&dsufreq { + dsu-supply = <®_dcdc5>; +}; + +&cpu6 { + cpu-supply = <®_dcdc3>; +}; + +&i2s1_mach { + soundcard-mach,format = "dsp_a"; + soundcard-mach,frame-master = <&i2s1_cpu>; + soundcard-mach,bitclock-master = <&i2s1_cpu>; + /* soundcard-mach,frame-inversion; */ + soundcard-mach,bitclock-inversion; + soundcard-mach,slot-num = <2>; + soundcard-mach,slot-width = <16>; + status = "disabled"; + i2s1_cpu: soundcard-mach,cpu { + sound-dai = <&i2s1_plat>; + soundcard-mach,pll-fs = <1>; + soundcard-mach,mclk-fp; + soundcard-mach,mclk-fs = <1>; + }; + i2s1_codec: soundcard-mach,codec { + soundcard-mach,pll-fs = <1>; + }; +}; + +&npu { + npu-setvol = <0>; + npu-supply = <®_dcdc2>; + status = "okay"; +}; + +&gpu { + gpu-supply = <®_dcdc4>; +}; diff --git a/arch/arm64/boot/dts/sunxi/sun60iw2p1-cpu-vf.dtsi b/arch/arm64/boot/dts/sunxi/sun60iw2p1-cpu-vf.dtsi new file mode 100644 index 000000000..fe4e60fff --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/sun60iw2p1-cpu-vf.dtsi @@ -0,0 +1,2512 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/{ + vf_mapping_table: vf_mapping_table { + vf-version = "V0.91"; + table = < + 0x00 0x0000 + 0x01 0x0100 + 0x11 0x0101 + 0x02 0x0200 + 0x12 0x0201 + 0x03 0x0300 + 0x04 0x0400 + 0x05 0x0500 + 0x06 0x0600 + 0x07 0x0700 + 0x08 0x0800 + 0x14 0x0401 + 0x15 0x0501 + >; + }; + + cluster0_opp_table: cluster0-opp-table { + compatible = "allwinner,sun50i-operating-points"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@720000000 { + opp-hz = /bits/ 64 <720000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@792000000 { + opp-hz = /bits/ 64 <792000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1104000000 { + opp-hz = /bits/ 64 <1104000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <850000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1296000000 { + opp-hz = /bits/ 64 <1296000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <900000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1392000000 { + opp-hz = /bits/ 64 <1392000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <950000>; + opp-microvolt-vf0200 = <850000>; + opp-microvolt-vf0300 = <860000>; + opp-microvolt-vf0400 = <840000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <840000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <860000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1416000000 { + opp-hz = /bits/ 64 <1416000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1512000000 { + opp-hz = /bits/ 64 <1512000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <1000000>; + opp-microvolt-vf0200 = <900000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <880000>; + opp-microvolt-vf0500 = <820000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <820000>; + opp-microvolt-vf0800 = <900000>; + opp-microvolt-vf0401 = <820000>; + opp-microvolt-vf0501 = <820000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1608000000 { + opp-hz = /bits/ 64 <1608000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <900000>; + opp-microvolt-vf0100 = <1050000>; + opp-microvolt-vf0200 = <950000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <920000>; + opp-microvolt-vf0500 = <860000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <860000>; + opp-microvolt-vf0800 = <950000>; + opp-microvolt-vf0401 = <860000>; + opp-microvolt-vf0501 = <840000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1704000000 { + opp-hz = /bits/ 64 <1704000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <1000000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <960000>; + opp-microvolt-vf0500 = <900000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <900000>; + opp-microvolt-vf0501 = <860000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <1000000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <1050000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <1000000>; + opp-microvolt-vf0500 = <950000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <950000>; + opp-microvolt-vf0501 = <900000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@416000000 { + opp-hz = /bits/ 64 <416000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@728000000 { + opp-hz = /bits/ 64 <728000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@780000000 { + opp-hz = /bits/ 64 <780000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1014000000 { + opp-hz = /bits/ 64 <1014000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1092000000 { + opp-hz = /bits/ 64 <1092000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1196000000 { + opp-hz = /bits/ 64 <1196000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <850000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <900000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1404000000 { + opp-hz = /bits/ 64 <1404000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <950000>; + opp-microvolt-26m-vf0200 = <850000>; + opp-microvolt-26m-vf0300 = <860000>; + opp-microvolt-26m-vf0400 = <840000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <840000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <860000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1508000000 { + opp-hz = /bits/ 64 <1508000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <1000000>; + opp-microvolt-26m-vf0200 = <900000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <880000>; + opp-microvolt-26m-vf0500 = <820000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <820000>; + opp-microvolt-26m-vf0800 = <900000>; + opp-microvolt-26m-vf0401 = <820000>; + opp-microvolt-26m-vf0501 = <820000>; + }; + + opp@1586000000 { + opp-hz = /bits/ 64 <1586000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <900000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1612000000 { + opp-hz = /bits/ 64 <1612000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <1050000>; + opp-microvolt-26m-vf0200 = <950000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <920000>; + opp-microvolt-26m-vf0500 = <860000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <860000>; + opp-microvolt-26m-vf0800 = <950000>; + opp-microvolt-26m-vf0401 = <860000>; + opp-microvolt-26m-vf0501 = <840000>; + }; + + opp@1716000000 { + opp-hz = /bits/ 64 <1716000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <1000000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <960000>; + opp-microvolt-26m-vf0500 = <900000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <900000>; + opp-microvolt-26m-vf0501 = <860000>; + }; + + opp@1794000000 { + opp-hz = /bits/ 64 <1794000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <1000000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <1050000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <1000000>; + opp-microvolt-26m-vf0500 = <950000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <950000>; + opp-microvolt-26m-vf0501 = <900000>; + }; + }; + + cluster1_opp_table: cluster1-opp-table { + compatible = "allwinner,sun50i-operating-points"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@720000000 { + opp-hz = /bits/ 64 <720000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@792000000 { + opp-hz = /bits/ 64 <792000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1296000000 { + opp-hz = /bits/ 64 <1296000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1392000000 { + opp-hz = /bits/ 64 <1392000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <850000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <820000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <820000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1512000000 { + opp-hz = /bits/ 64 <1512000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <900000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <860000>; + opp-microvolt-vf0400 = <820000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <860000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1608000000 { + opp-hz = /bits/ 64 <1608000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <850000>; + opp-microvolt-vf0100 = <950000>; + opp-microvolt-vf0200 = <850000>; + opp-microvolt-vf0300 = <900000>; + opp-microvolt-vf0400 = <840000>; + opp-microvolt-vf0500 = <820000>; + opp-microvolt-vf0600 = <850000>; + opp-microvolt-vf0700 = <820000>; + opp-microvolt-vf0800 = <900000>; + opp-microvolt-vf0401 = <820000>; + opp-microvolt-vf0501 = <820000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1704000000 { + opp-hz = /bits/ 64 <1704000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <900000>; + opp-microvolt-vf0100 = <1000000>; + opp-microvolt-vf0200 = <900000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <870000>; + opp-microvolt-vf0500 = <850000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <850000>; + opp-microvolt-vf0800 = <950000>; + opp-microvolt-vf0401 = <850000>; + opp-microvolt-vf0501 = <840000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <950000>; + opp-microvolt-vf0100 = <1050000>; + opp-microvolt-vf0200 = <950000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <920000>; + opp-microvolt-vf0500 = <900000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <900000>; + opp-microvolt-vf0800 = <1000000>; + opp-microvolt-vf0401 = <900000>; + opp-microvolt-vf0501 = <870000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1896000000 { + opp-hz = /bits/ 64 <1896000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <1000000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <970000>; + opp-microvolt-vf0500 = <940000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <940000>; + opp-microvolt-vf0501 = <900000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1920000000 { + opp-hz = /bits/ 64 <1920000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <1000000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1944000000 { + opp-hz = /bits/ 64 <1944000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <1000000>; + opp-microvolt-vf0500 = <970000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <970000>; + opp-microvolt-vf0501 = <930000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1992000000 { + opp-hz = /bits/ 64 <1992000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <1050000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <1050000>; + opp-microvolt-vf0500 = <1000000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <1000000>; + opp-microvolt-vf0501 = <960000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@416000000 { + opp-hz = /bits/ 64 <416000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@728000000 { + opp-hz = /bits/ 64 <728000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@780000000 { + opp-hz = /bits/ 64 <780000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1014000000 { + opp-hz = /bits/ 64 <1014000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1196000000 { + opp-hz = /bits/ 64 <1196000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1300000000 { + opp-hz = /bits/ 64 <1300000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1404000000 { + opp-hz = /bits/ 64 <1404000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <850000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <820000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <820000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1508000000 { + opp-hz = /bits/ 64 <1508000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <900000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <860000>; + opp-microvolt-26m-vf0400 = <820000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <860000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1586000000 { + opp-hz = /bits/ 64 <1586000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <850000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1612000000 { + opp-hz = /bits/ 64 <1612000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <950000>; + opp-microvolt-26m-vf0200 = <850000>; + opp-microvolt-26m-vf0300 = <900000>; + opp-microvolt-26m-vf0400 = <840000>; + opp-microvolt-26m-vf0500 = <820000>; + opp-microvolt-26m-vf0600 = <850000>; + opp-microvolt-26m-vf0700 = <820000>; + opp-microvolt-26m-vf0800 = <900000>; + opp-microvolt-26m-vf0401 = <820000>; + opp-microvolt-26m-vf0501 = <820000>; + }; + + opp@1690000000 { + opp-hz = /bits/ 64 <1690000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <900000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1716000000 { + opp-hz = /bits/ 64 <1716000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <1000000>; + opp-microvolt-26m-vf0200 = <900000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <870000>; + opp-microvolt-26m-vf0500 = <850000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <850000>; + opp-microvolt-26m-vf0800 = <950000>; + opp-microvolt-26m-vf0401 = <850000>; + opp-microvolt-26m-vf0501 = <840000>; + }; + + opp@1794000000 { + opp-hz = /bits/ 64 <1794000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <950000>; + opp-microvolt-26m-vf0100 = <1050000>; + opp-microvolt-26m-vf0200 = <950000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <920000>; + opp-microvolt-26m-vf0500 = <900000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <900000>; + opp-microvolt-26m-vf0800 = <1000000>; + opp-microvolt-26m-vf0401 = <900000>; + opp-microvolt-26m-vf0501 = <870000>; + }; + + opp@1898000000 { + opp-hz = /bits/ 64 <1898000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <1000000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <1000000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <970000>; + opp-microvolt-26m-vf0500 = <940000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <940000>; + opp-microvolt-26m-vf0501 = <900000>; + }; + + opp@1950000000 { + opp-hz = /bits/ 64 <1950000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <1000000>; + opp-microvolt-26m-vf0500 = <970000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <970000>; + opp-microvolt-26m-vf0501 = <930000>; + }; + + opp@1976000000 { + opp-hz = /bits/ 64 <1976000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <1050000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@2002000000 { + opp-hz = /bits/ 64 <2002000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <1050000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <1050000>; + opp-microvolt-26m-vf0500 = <1000000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <1000000>; + opp-microvolt-26m-vf0501 = <960000>; + }; + }; + + dsu_opp_table: dsu-opp-table { + compatible = "allwinner,dsu-operating-points"; + + opp@288000000 { + opp-hz = /bits/ 64 <288000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@312000000 { + opp-hz = /bits/ 64 <312000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@528000000 { + opp-hz = /bits/ 64 <528000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@744000000 { + opp-hz = /bits/ 64 <744000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@792000000 { + opp-hz = /bits/ 64 <792000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@840000000 { + opp-hz = /bits/ 64 <840000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@888000000 { + opp-hz = /bits/ 64 <888000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@912000000 { + opp-hz = /bits/ 64 <912000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <850000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@984000000 { + opp-hz = /bits/ 64 <984000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <900000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1032000000 { + opp-hz = /bits/ 64 <1032000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1056000000 { + opp-hz = /bits/ 64 <1056000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <950000>; + opp-microvolt-vf0200 = <850000>; + opp-microvolt-vf0300 = <860000>; + opp-microvolt-vf0400 = <840000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <840000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <860000>; + opp-microvolt-vf0401 = <800000>; + opp-microvolt-vf0501 = <800000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1152000000 { + opp-hz = /bits/ 64 <1152000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <900000>; + opp-microvolt-vf0100 = <1000000>; + opp-microvolt-vf0200 = <900000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <880000>; + opp-microvolt-vf0500 = <820000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <820000>; + opp-microvolt-vf0800 = <900000>; + opp-microvolt-vf0401 = <820000>; + opp-microvolt-vf0501 = <820000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <1050000>; + opp-microvolt-vf0200 = <950000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <920000>; + opp-microvolt-vf0500 = <860000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <860000>; + opp-microvolt-vf0800 = <950000>; + opp-microvolt-vf0401 = <860000>; + opp-microvolt-vf0501 = <840000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1224000000 { + opp-hz = /bits/ 64 <1224000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <1000000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <960000>; + opp-microvolt-vf0500 = <900000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <900000>; + opp-microvolt-vf0501 = <860000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1248000000 { + opp-hz = /bits/ 64 <1248000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <1050000>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <1000000>; + opp-microvolt-vf0500 = <950000>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <950000>; + opp-microvolt-vf0501 = <900000>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <1000000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <960000>; + opp-microvolt-26m-vf0500 = <900000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <900000>; + opp-microvolt-26m-vf0501 = <860000>; + }; + + opp@1296000000 { + opp-hz = /bits/ 64 <1296000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <1000000>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@546000000 { + opp-hz = /bits/ 64 <546000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@598000000 { + opp-hz = /bits/ 64 <598000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@780000000 { + opp-hz = /bits/ 64 <780000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@832000000 { + opp-hz = /bits/ 64 <832000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <800000>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@910000000 { + opp-hz = /bits/ 64 <910000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <850000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + opp-microvolt-26m-vf0400 = <800000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <800000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <800000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@988000000 { + opp-hz = /bits/ 64 <988000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <900000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1066000000 { + opp-hz = /bits/ 64 <1066000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0100 = <950000>; + opp-microvolt-26m-vf0200 = <850000>; + opp-microvolt-26m-vf0300 = <860000>; + opp-microvolt-26m-vf0400 = <840000>; + opp-microvolt-26m-vf0500 = <800000>; + opp-microvolt-26m-vf0600 = <840000>; + opp-microvolt-26m-vf0700 = <800000>; + opp-microvolt-26m-vf0800 = <860000>; + opp-microvolt-26m-vf0401 = <800000>; + opp-microvolt-26m-vf0501 = <800000>; + }; + + opp@1144000000 { + opp-hz = /bits/ 64 <1144000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <1000000>; + opp-microvolt-26m-vf0200 = <900000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <880000>; + opp-microvolt-26m-vf0500 = <820000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <820000>; + opp-microvolt-26m-vf0800 = <900000>; + opp-microvolt-26m-vf0401 = <820000>; + opp-microvolt-26m-vf0501 = <820000>; + }; + + opp@1196000000 { + opp-hz = /bits/ 64 <1196000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <900000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + opp@1222000000 { + opp-hz = /bits/ 64 <1222000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <1050000>; + opp-microvolt-26m-vf0200 = <950000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <920000>; + opp-microvolt-26m-vf0500 = <860000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <860000>; + opp-microvolt-26m-vf0800 = <950000>; + opp-microvolt-26m-vf0401 = <860000>; + opp-microvolt-26m-vf0501 = <840000>; + }; + + opp@1274000000 { + opp-hz = /bits/ 64 <1274000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <0>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <1050000>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <1000000>; + opp-microvolt-26m-vf0500 = <950000>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <950000>; + opp-microvolt-26m-vf0501 = <900000>; + }; + + opp@1352000000 { + opp-hz = /bits/ 64 <1352000000>; + clock-latency-ns = <244144>; + opp-microvolt-vf0000 = <0>; + opp-microvolt-vf0100 = <0>; + opp-microvolt-vf0200 = <0>; + opp-microvolt-vf0300 = <0>; + opp-microvolt-vf0400 = <0>; + opp-microvolt-vf0500 = <0>; + opp-microvolt-vf0600 = <0>; + opp-microvolt-vf0700 = <0>; + opp-microvolt-vf0800 = <0>; + opp-microvolt-vf0401 = <0>; + opp-microvolt-vf0501 = <0>; + opp-microvolt-26m-vf0000 = <1000000>; + opp-microvolt-26m-vf0100 = <0>; + opp-microvolt-26m-vf0200 = <0>; + opp-microvolt-26m-vf0300 = <0>; + opp-microvolt-26m-vf0400 = <0>; + opp-microvolt-26m-vf0500 = <0>; + opp-microvolt-26m-vf0600 = <0>; + opp-microvolt-26m-vf0700 = <0>; + opp-microvolt-26m-vf0800 = <0>; + opp-microvolt-26m-vf0401 = <0>; + opp-microvolt-26m-vf0501 = <0>; + }; + + }; + + npu_opp_table: npu-opp-table { + compatible = "allwinner,npu-operating-points"; + + npu_opp_table_492: opp-492 { + opp-hz = /bits/ 64 <492000000>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0201 = <800000>; + opp-microvolt-vf0202 = <800000>; + opp-microvolt-vf0203 = <800000>; + opp-microvolt-vf0204 = <800000>; + opp-microvolt-vf0205 = <800000>; + opp-microvolt-vf0206 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0201 = <800000>; + opp-microvolt-26m-vf0202 = <800000>; + opp-microvolt-26m-vf0203 = <800000>; + opp-microvolt-26m-vf0204 = <800000>; + opp-microvolt-26m-vf0205 = <800000>; + opp-microvolt-26m-vf0206 = <800000>; + opp-microvolt-26m-vf0300 = <800000>; + }; + + npu_opp_table_852: opp-852 { + opp-hz = /bits/ 64 <852000000>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0201 = <800000>; + opp-microvolt-vf0202 = <880000>; + opp-microvolt-vf0203 = <880000>; + opp-microvolt-vf0204 = <880000>; + opp-microvolt-26m-vf0000 = <800000>; + opp-microvolt-26m-vf0200 = <800000>; + opp-microvolt-26m-vf0201 = <800000>; + opp-microvolt-26m-vf0202 = <880000>; + opp-microvolt-26m-vf0203 = <880000>; + opp-microvolt-26m-vf0204 = <800000>; + }; + + npu_opp_table_1008: opp-1008 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt-vf0000 = <960000>; + opp-microvolt-vf0202 = <1030000>; + opp-microvolt-vf0203 = <1030000>; + opp-microvolt-vf0204 = <1000000>; + opp-microvolt-vf0205 = <960000>; + opp-microvolt-vf0206 = <900000>; + opp-microvolt-vf0300 = <900000>; + opp-microvolt-26m-vf0000 = <960000>; + opp-microvolt-26m-vf0202 = <1030000>; + opp-microvolt-26m-vf0203 = <1030000>; + opp-microvolt-26m-vf0204 = <1000000>; + opp-microvolt-26m-vf0205 = <960000>; + opp-microvolt-26m-vf0206 = <900000>; + opp-microvolt-26m-vf0300 = <900000>; + }; + + npu_opp_table_1120: opp-1120 { + opp-hz = /bits/ 64 <1120000000>; + opp-microvolt-vf0205 = <1080000>; + opp-microvolt-vf0206 = <1040000>; + opp-microvolt-vf0300 = <1040000>; + opp-microvolt-26m-vf0205 = <1080000>; + opp-microvolt-26m-vf0206 = <1040000>; + opp-microvolt-26m-vf0300 = <1040000>; + }; + }; + + ve_opp_table: ve-opp-table { + compatible = "allwinner,ve-operating-points"; + + opp-vf0000 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0100 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0101 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0200 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0201 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0300 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0400 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0500 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0600 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0700 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0800 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0401 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + opp-vf0501 { + opp-hz-0 = /bits/ 64 <624000000>; + opp-microvolt-0 = <800000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/sunxi/sun60iw2p1.dtsi b/arch/arm64/boot/dts/sunxi/sun60iw2p1.dtsi new file mode 100644 index 000000000..fb368aeba --- /dev/null +++ b/arch/arm64/boot/dts/sunxi/sun60iw2p1.dtsi @@ -0,0 +1,5079 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sun60iw2p1-cpu-vf.dtsi" +/ { + model = "BPI-M8"; + interrupt-parent = <&wakeupgen>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + sunxi-mmc0 = &sdc0; + sunxi-mmc2 = &sdc3; + twi0 = &twi0; + twi1 = &twi1; + twi2 = &twi2; + twi3 = &twi3; + twi4 = &twi4; + twi5 = &twi5; + twi6 = &twi6; + twi7 = &twi7; + twi8 = &twi8; + twi9 = &twi9; + twi10 = &twi10; + twi11 = &twi11; + twi12 = &twi12; + twi13 = &s_twi0; + twi14 = &s_twi1; + twi15 = &s_twi2; + pwm0 = &pwm0; + pwm1 = &pwm1; + pwm2 = &s_pwm0; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &r_spi; + gpadc0 = &gpadc0; + ir0 = &irrx; + ir1 = &s_irrx; + ir2 = &irtx; + }; + + reg_vdd_sys: vdd-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd_sys"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + bl31 { + reg = <0x0 0x48000000 0x0 0x01000000>; + }; + }; + + chosen { + bootargs = "earlyprintk=sunxi-uart,0x2500000 loglevel=8 initcall_debug=0 console=ttyS0 init=/init"; + linux,initrd-start = <0x0 0x0>; + linux,initrd-end = <0x0 0x0>; + rng-seed; /* This random value should be provided by bootloader */ + kaslr-seed; /* This random value should be provided by bootloader */ + }; + + /* avoid panic when memory-node err(from uboot) */ + memory@40000000 { + device_type = "memory"; + reg = <0x00000000 0x40000000 0x00000000 0x20000000>; + }; + + firmware { + android { + compatible = "android,firmware"; + name = "android"; + boot_devices = "soc@3000000/4020000.sdmmc,soc@3000000/4022000.sdmmc,soc@3000000/4023000.sdmmc,soc@3000000/4520000.ufs,soc@3000000"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,vbmeta_system,vbmeta_vendor,boot,init_boot"; + }; + }; + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + arm_pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <430>; + clocks = <&cpupll_ccu CLK_PLL_CPU_L>; + operating-points-v2 = <&cluster0_opp_table>; + dynamic-power-coefficient = <162>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <430>; + clocks = <&cpupll_ccu CLK_PLL_CPU_L>; + operating-points-v2 = <&cluster0_opp_table>; + dynamic-power-coefficient = <162>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <430>; + clocks = <&cpupll_ccu CLK_PLL_CPU_L>; + operating-points-v2 = <&cluster0_opp_table>; + dynamic-power-coefficient = <162>; + #cooling-cells = <2>; + + cpu2_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <430>; + clocks = <&cpupll_ccu CLK_PLL_CPU_L>; + operating-points-v2 = <&cluster0_opp_table>; + dynamic-power-coefficient = <162>; + #cooling-cells = <2>; + + cpu3_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <430>; + clocks = <&cpupll_ccu CLK_PLL_CPU_L>; + operating-points-v2 = <&cluster0_opp_table>; + dynamic-power-coefficient = <162>; + #cooling-cells = <2>; + + cpu4_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <430>; + clocks = <&cpupll_ccu CLK_PLL_CPU_L>; + operating-points-v2 = <&cluster0_opp_table>; + dynamic-power-coefficient = <162>; + #cooling-cells = <2>; + + cpu5_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; + clocks = <&cpupll_ccu CLK_PLL_CPU_B>; + operating-points-v2 = <&cluster1_opp_table>; + dynamic-power-coefficient = <598>; + #cooling-cells = <2>; + + cpu6_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <1024>; + clocks = <&cpupll_ccu CLK_PLL_CPU_B>; + operating-points-v2 = <&cluster1_opp_table>; + dynamic-power-coefficient = <598>; + #cooling-cells = <2>; + + cpu7_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + core4 { + cpu = <&cpu4>; + }; + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + core1 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <46>; + exit-latency-us = <59>; + min-residency-us = <3570>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <47>; + exit-latency-us = <74>; + min-residency-us = <5000>; + local-timer-stop; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + arm_pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; /* GIC-600 */ + //interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + dcxo19_2M: dcxo19_2M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + clock-output-names = "dcxo19_2M"; + }; + + dcxo24M: dcxo24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "dcxo24M"; + }; + + dcxo26M: dcxo26M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + clock-output-names = "dcxo26M"; + }; + + sys24M: sys24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sys24M"; + }; + + rc_16m: rc16m_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "rc-16m"; + }; + + ext_32k: ext32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + gic: interrupt-controller@3400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x03400000 0 0x10000>, /* GIC Dist */ + <0x0 0x03460000 0 0xFF004>; /* GIC Re */ + interrupt-parent = <&gic>; + }; + + wakeupgen: interrupt-controller@0 { + compatible = "allwinner,sunxi-wakeupgen"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-parent = <&gic>; + }; + + + timer_arch { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + interrupt-parent = <&gic>; + arm,no-tick-in-suspend; + }; + + nmi_intc: intc-nmi@7010320 { + compatible = "allwinner,sun8i-nmi"; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x07010320 0 0xc>; + interrupts = ; + }; + + mmu_aw: iommu@3900000 { + compatible = "allwinner,iommu-v20"; + reg = <0x0 0x03900000 0x0 0x20000>; + interrupts = , + ; + interrupt-names = "iommu-irq1","iommu-irq2"; + clocks = <&ccu CLK_IOMMU0_SYS_H>, + <&ccu CLK_IOMMU0_SYS_P>, + <&ccu CLK_IOMMU0_SYS_MBUS>, + <&ccu CLK_IOMMU1_SYS_H>, + <&ccu CLK_IOMMU1_SYS_P>, + <&ccu CLK_IOMMU1_SYS_MBUS> + ; + clock-names = "iommu0-sys-hclk", + "iommu0-sys-pclk", + "iommu0-sys-mclk", + "iommu1-sys-hclk", + "iommu1-sys-pclk", + "iommu1-sys-mclk" + ; + resets = <&ccu RST_BUS_IOMMU0_SY>, <&ccu RST_BUS_IOMMU1_SY>; + /* clock-frequency = <24000000>; */ + #iommu-cells = <2>; + version=<0x16>; + tlb_prefetch = <0x3007f>; + tlb_invalid_mode = <0x1>; + ptw_invalid_mode = <0x1>; + masters = "USB", "CSI", "ISP", "VE_ENC", "dummy04", "dummy05", + "VE_DEC0", "VE_DEC1", "DE0","DI","G2D","EINK", "DEBUG_MODE"; + + usb_iommu { + iommu-master; + id=<0>; + }; + + csi_iommu { + iommu-master; + id=<1>; + power-domains = <&pd SUN60IW2_PCK_VI>; + }; + + isp_iommu { + iommu-master; + id=<2>; + power-domains = <&pd SUN60IW2_PCK_VI>; + }; + + ve_enc_iommu { + iommu-master; + id=<3>; + power-domains = <&pd SUN60IW2_PCK_VE_ENC>; + }; + + dummy04 { + iommu-master; + id=<4>; + skip; + }; + dummy05 { + iommu-master; + id=<5>; + skip; + }; + + ve_dec0_iommu { + iommu-master; + id=<6>; + power-domains = <&pd SUN60IW2_PCK_VE_DEC>; + }; + + ve_dec1_iommu { + iommu-master; + id=<7>; + power-domains = <&pd SUN60IW2_PCK_VE_DEC>; + }; + + de0_iommu { + iommu-master; + id=<8>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + }; + + di_iommu { + iommu-master; + id=<9>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + }; + + g2d_iommu { + iommu-master; + id=<10>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + }; + + eink_iommu { + iommu-master; + id=<11>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + }; + }; + + dsufreq: dsufreq@0 { + compatible = "allwinner,dsufreq"; + reg = <0x0 0x08860000 0x0 0x1000>; + clocks = <&cpupll_ccu CLK_PLL_CPU_DSU>; + operating-points-v2 = <&dsu_opp_table>; + }; + + + thermal_zones: thermal-zones { + cpul_thermal_zone: cpul_thermal_zone { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths 3>; + sustainable-power = <756>; + + cpul_trips: trips { + cpul_threshold: trip-point@0 { + temperature = <70000>; + type = "passive"; + hysteresis = <2000>; + }; + cpul_target: trip-point@1 { + temperature = <90000>; + type = "passive"; + hysteresis = <2000>; + }; + cpul_crit: cpu_crit@0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpul_target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + cpub_thermal_zone: cpub_thermal_zone { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths 0>; + sustainable-power = <914>; + + cpub_trips: trips { + cpub_threshold: trip-point@0 { + temperature = <70000>; + type = "passive"; + hysteresis = <2000>; + }; + cpub_target: trip-point@1 { + temperature = <90000>; + type = "passive"; + hysteresis = <2000>; + }; + cpub_crit: cpu_crit@0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpub_target>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + cpul_idle_zone: cpul_idle_zone { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths 5>; + + cpul_idle_trips: trips { + cpul_thres: trip-point@0 { + temperature = <90000>; + type = "passive"; + hysteresis = <2000>; + }; + cpul_overshot: trip-point@1{ + temperature = <100000>; + type = "passive"; + hysteresis = <2000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpul_overshot>; + cooling-device = <&cpu2_idle 0 50>, + <&cpu3_idle 0 50>, + <&cpu4_idle 0 50>, + <&cpu5_idle 0 50>; + contribution = <1024>; + }; + }; + }; + + cpub_idle_zone: cpub_idle_zone { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths 6>; + + cpub_idle_trips: trips { + cpub_thres: trip-point@0 { + temperature = <90000>; + type = "passive"; + hysteresis = <2000>; + }; + cpub_overshot: trip-point@1{ + temperature = <100000>; + type = "passive"; + hysteresis = <2000>; + }; + }; + + cooling-maps { + map0 { + trip = <&cpub_overshot>; + cooling-device = <&cpu6_idle 0 100>, + <&cpu7_idle 0 100>; + contribution = <1024>; + }; + }; + }; + + gpu_thermal_zone: gpu_thermal_zone { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths 4>; + sustainable-power = <2400>; + + gpu_trips: trips { + gpu_threshold: trip-point@0 { + temperature = <60000>; + type = "passive"; + hysteresis = <0>; + }; + gpu_target: trip-point@1 { + temperature = <90000>; + type = "passive"; + hysteresis = <0>; + }; + gpu_crit: gpu_crit@0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_threshold>; + cooling-device = <&gpu + 0 + 0>; + contribution = <1024>; + }; + map1 { + trip = <&gpu_target>; + cooling-device = <&gpu + 0 + 3>; + contribution = <1024>; + }; + map2 { + trip = <&gpu_crit>; + cooling-device = <&gpu + 3 + 3>; + contribution = <1024>; + }; + + }; + }; + + npu_thermal_zone: npu_thermal_zone { + polling-delay-passive = <100>; + polling-delay = <1000>; + thermal-sensors = <&ths 2>; + + npu_trips: trips { + npu_crit: npu_crit@0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + ddr_thermal_zone: ddr_thermal_zone { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + + ddr_trips: trips { + ddr_crit: ddr_crit@0 { + temperature = <110000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + + skin_zone { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 7>; + + skin_trips: trips { + skin_crit: skin_crit@0 { + temperature = <50000>; + type = "critical"; + hysteresis = <0>; + }; + }; + }; + }; + + pck: pck-600@7060000 { + compatible = "allwinner,sun60iw2-pck", "syscon", "simple-mfd"; + reg = <0x0 0x07060000 0x0 0xB000>; + + pd: power-controller { + compatible = "allwinner,sun60iw2-pck-600"; + clocks = <&r_ccu CLK_R_PPU>; + clock-names = "pck"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vi@SUN60IW2_PCK_VI { + reg = ; + }; + pd_ve_dec@SUN60IW2_PCK_VE_DEC { + reg = ; + }; + pd_ve_enc@SUN60IW2_PCK_VE_ENC { + reg = ; + }; + /* + pd_gpu_top@SUN60IW2_PCK_GPU_TOP { + reg = ; + }; + pd_gpu_core@SUN60IW2_PCK_GPU_CORE { + reg = ; + }; + */ + + pd_pcie@SUN60IW2_PCK_PCIE { + reg = ; + }; + + pd_npu@SUN60IW2_PCK_NPU { + reg = ; + }; + + pd_usb2@SUN60IW2_PCK_USB2 { + reg = ; + }; + + pd_de_sys@SUN60IW2_PCK_DE_SYS { + reg = ; + }; + + pd_vo@SUN60IW2_PCK_VO { + reg = ; + }; + + pd_vo1@SUN60IW2_PCK_VO1 { + reg = ; + }; + }; + }; + + + dram: dram { + compatible = "allwinner,dram"; + clocks = <&ccu CLK_PLL_DDR>; + clock-names = "pll_ddr"; + }; + + ddr_clk: clk_ddr { + compatible = "allwinner,sun60iw2_clock_ddr"; + reg = <0x0 0x02002000 0x0 0x1000>; + clocks = <&ccu CLK_PLL_DDR>; + clock-names = "pll_ddr"; + #clock-cells = <0>; + }; + + dram_opp_table: opp_table { + compatible = "operating-points-v2"; + opp@150000000 { + opp-hz = /bits/ 64 <150000000>; + clock-latency-ns = <150000>; + opp-microvolt = <900000>; + }; + }; + + sunxi_dmcfreq: dmcfreq@3120000 { + compatible = "allwinner,sun60iw2-dmc", "syscon"; + reg = <0x0 0x0a020000 0x0 0x2000>, + <0x0 0x02020000 0x0 0x4000>, + <0x0 0x0a100000 0x0 0x11000>; + interrupts = ; + clocks = <&ddr_clk>, <&ccu CLK_NSI>; + clock-names = "dram", "bus"; + operating-points-v2 = <&dram_opp_table>; + upthreshold = <50>; + downdifferential = <20>; + holdtime = <25>; + vddcore-supply = <®_vdd_sys>; + normalvoltage = <900000>; + boostvoltage = <900000>; + }; + + soc: soc@3000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + ve: ve@1c0e000 { + compatible = "allwinner,sunxi-cedar-ve"; + reg = <0x0 0x01c0e000 0x0 0x3000>, + <0x0 0x03000000 0x0 0x10>; + interrupts = ; + clocks = <&ccu CLK_PLL_VE0>, + <&ccu CLK_VE_AHB_GATE>, + <&ccu CLK_DEC_MBUS_GATE>, + <&ccu CLK_VE_DEC_MBUS>, + <&ccu CLK_BUS_VE_DEC>, + <&ccu CLK_VE_DEC>; + clock-names = "pll_ve", + "ahb_gate", + "mbus_gate", + "mbus_ve", + "bus_ve", + "ve"; + resets = <&ccu RST_BUS_VE_DEC>; + reset-names = "reset_ve"; + operating-points-v2 = <&ve_opp_table>; + iommus = <&mmu_aw 6 1>; + nsi = <&nsi0 7>; + power-domains = <&pd SUN60IW2_PCK_VE_DEC>; + }; + ve1: ve1@1c0e000 { + compatible = "allwinner,sunxi-cedar-ve1"; + iommus = <&mmu_aw 7 1>; + nsi = <&nsi0 8>; + }; + ve2: ve2@1c10000 { + compatible = "allwinner,sunxi-cedar-ve2"; + reg = <0x0 0x01c10000 0x0 0x1000>, + <0x0 0x03000000 0x0 0x10>; + interrupts = ; + clocks = <&ccu CLK_PLL_VE1>, + <&ccu CLK_VE_ENC_AHB_GATE>, + <&ccu CLK_MBUS_VE_GATE>, + <&ccu CLK_MBUS_VE>, + <&ccu CLK_BUS_VE_ENC>, + <&ccu CLK_VE_ENC0>; + clock-names = "pll_ve", + "ahb_gate", + "mbus_gate", + "mbus_ve", + "bus_ve", + "ve"; + resets = <&ccu RST_BUS_VE_ENC0>; + reset-names = "reset_ve"; + operating-points-v2 = <&ve_opp_table>; + iommus = <&mmu_aw 3 1>; + nsi = <&nsi0 9>; + power-domains = <&pd SUN60IW2_PCK_VE_ENC>; + ve_top_reg_offset = <0x800>; + }; + rtc_ccu: rtc_ccu@7090000 { + compatible = "allwinner,sun60iw2-rtc-ccu"; + reg = <0x0 0x07090000 0x0 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cpupll_ccu: cpupll_ccu@8870000 { + compatible = "allwinner,sun60iw2-cpupll"; + reg = <0x0 0x08870000 0x0 0x3034>; + clocks = <&rtc_ccu CLK_DCXO>; + clock-names = "dcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ccu: ccu@2002000 { + compatible = "allwinner,sun60iw2-ccu"; + reg = <0x0 0x02002000 0x0 0x2000>; + clocks = <&dcxo24M>, <&rtc_ccu CLK_OSC32K>, <&rc_16m>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + /* + * for example + * sdm_info: sdm_info { + * pll-video0 { + * sdm-enable = <1>; // required + * sdm-factor = <4>; // required + * freq-mod = ; // optional: default TR_N + * sdm-freq = ; // optional: default FREQ_31_5 + * }; + * }; + */ + }; + + r_ccu: r_ccu@7010000 { + compatible = "allwinner,sun60iw2-r-ccu"; + reg = <0x0 0x07010000 0x0 0x340>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dump_reg:dump_reg@44000 { + compatible = "allwinner,sunxi-dump-reg"; + reg = <0x0 0x00044000 0x0 0x0004>; + }; + + soc_timer0: timer@3009000{ + compatible = "allwinner,sun50i-timer"; + device_type = "soc_timer"; + reg = <0x0 0x03009000 0x0 0x400>; + interrupt-parent = <&gic>; + interrupts = ; + clock-names = "parent", "bus", "timer0-mod", "timer1-mod"; + clocks = <&sys24M>, <&ccu CLK_BUS_TIMER>, <&ccu CLK_TIMER0>, <&ccu CLK_TIMER1>; + resets = <&ccu RST_BUS_TIMER0>; + }; + + + rtc: rtc@7090000 { + compatible = "allwinner,rtc-v201"; + device_type = "rtc"; + wakeup-source; + reg = <0x0 0x07090000 0x0 0x320>; + interrupts = ; + clocks = <&r_ccu CLK_RTC>, <&rtc_ccu CLK_RTC_1K>, <&rtc_ccu CLK_RTC_SPI>; + clock-names = "r-ahb-rtc", "rtc-1k", "rtc-spi"; + resets = <&r_ccu RST_BUS_RTC>; + gpr_cur_pos = <6>; + gpr_bootcount_pos = <7>; + }; + + pio: pinctrl@2000000 { + //#address-cells = <1>; + //#size-cells = <0>; + compatible = "allwinner,sun60iw2-pinctrl"; + reg = <0x0 0x02000000 0x0 0x600>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&rtc_ccu CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + sdc0_pins_f: sdc0@5 { + pins = "PF2"; + function = "sdc0"; + drive-strength = <30>; + bias-pull-up; + power-source = <3300>; + }; + + sdc0_pins_g: sdc0@6 { + pins = "PF2"; + function = "sdc0"; + drive-strength = <30>; + bias-pull-up; + power-source = <1800>; + }; + + sdc0_pins_a: sdc0@0 { + pins = "PF0", "PF1", + "PF3", "PF4", "PF5"; + function = "sdc0"; + drive-strength = <10>; + bias-pull-up; + power-source = <3300>; + }; + + sdc0_pins_b: sdc0@1 { + pins = "PF0", "PF1", + "PF3", "PF4", "PF5"; + function = "sdc0"; + drive-strength = <10>; + bias-pull-up; + power-source = <1800>; + }; + + sdc0_pins_c: sdc0@2 { + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "gpio_in"; + power-source = <3300>; + }; + + /* TODO: add jtag pin */ + sdc0_pins_d: sdc0@3 { + pins = "PF2", "PF4"; + function = "uart0"; + drive-strength = <10>; + bias-pull-up; + power-source = <3300>; + }; + + sdc0_pins_e: sdc0@4 { + pins = "PF0", "PF1", "PF3", + "PF5"; + function = "jtag"; + drive-strength = <10>; + bias-pull-up; + power-source = <3300>; + }; + + sdc1_pins_a: sdc1@0 { + pins = "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "sdc1"; + drive-strength = <10>; + bias-pull-up; + }; + + sdc1_pins_b: sdc1@1 { + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "gpio_in"; + }; + + sdc1_pins_c: sdc1@2 { + pins = "PG0"; + function = "sdc1"; + drive-strength = <20>; + bias-pull-up; + }; + + sdc2_pins_a: sdc2@0 { + pins = "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function = "sdc2"; + drive-strength = <20>; + bias-pull-up; + }; + + sdc2_pins_b: sdc2@1 { + pins = "PC0", "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function = "gpio_in"; + }; + + sdc2_pins_c: sdc2@2 { + pins = "PC0"; + function = "sdc2"; + drive-strength = <40>; + bias-pull-down; + }; + + sdc2_pins_d: sdc2@3 { + pins = "PC5", "PC1"; + function = "sdc2"; + drive-strength = <40>; + bias-pull-up; + }; + + sdc3_pins_a: sdc3@0 { + pins = "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function = "sdc3"; + drive-strength = <20>; + bias-pull-up; + }; + + sdc3_pins_b: sdc3@1 { + pins = "PC0", "PC1", "PC5", "PC6", + "PC8", "PC9", "PC10", "PC11", + "PC13", "PC14", "PC15", "PC16"; + function = "gpio_in"; + }; + + sdc3_pins_c: sdc3@2 { + pins = "PC0"; + function = "sdc3"; + drive-strength = <40>; + bias-pull-down; + }; + + sdc3_pins_d: sdc3@3 { + pins = "PC5", "PC1"; + function = "sdc3"; + drive-strength = <40>; + bias-pull-up; + }; + + csi_mclk0_pins_a: csi_mclk0@0 { + pins = "PE0"; + function = "mcsi0"; + drive-strength = <20>; + }; + + csi_mclk0_pins_b: csi_mclk0@1 { + pins = "PE0"; + function = "gpio_in"; + }; + + csi_mclk1_pins_a: csi_mclk1@0 { + pins = "PE5"; + function = "mcsi1"; + drive-strength = <20>; + }; + + csi_mclk1_pins_b: csi_mclk1@1 { + pins = "PE5"; + function = "gpio_in"; + }; + + csi_mclk2_pins_a: csi_mclk2@0 { + pins = "PE9"; + function = "mcsi2"; + drive-strength = <20>; + }; + + csi_mclk2_pins_b: csi_mclk2@1 { + pins = "PE9"; + function = "gpio_in"; + }; + + ncsi0_8bit_pins_a: ncsi0_8bit@0 { + pins = "PE0", "PE1", "PE2", + "PE3", "PE4", "PE6", "PE7", + "PE8", "PE9", "PE10"; + function = "ncsi0"; + drive-strength = <20>; + }; + + ncsi0_8bit_pins_b: ncsi0_8bit@1 { + pins = "PE0", "PE1", "PE2", + "PE3", "PE4", "PE6", "PE7", + "PE8", "PE9", "PE10"; + function = "gpio_in"; + }; + + ncsi1_8bit_pins_a: ncsi1_8bit@0 { + pins = "PK0", "PK1", "PK2", + "PK19", "PK18", "PK17", "PK16", + "PK15", "PK14", "PK13", "PK12"; + function = "ncsi1"; + drive-strength = <20>; + }; + + ncsi1_8bit_pins_b: ncsi1_8bit@1 { + pins = "PK0", "PK1", "PK2", + "PK19", "PK18", "PK17", "PK16", + "PK15", "PK14", "PK13", "PK12"; + function = "gpio_in"; + }; + + ncsi1_16bit_pins_a: ncsi1_16bit@0 { + pins = "PK0", "PK1", "PK2", + "PK19", "PK18", "PK17", "PK16", + "PK15", "PK14", "PK13", "PK12", + "PK11", "PK10", "PK9", "PK8", + "PK7", "PK6", "PK5", "PK4"; + function = "ncsi1"; + drive-strength = <20>; + }; + + ncsi1_16bit_pins_b: ncsi1_16bit@1 { + pins = "PK0", "PK1", "PK2", + "PK19", "PK18", "PK17", "PK16", + "PK15", "PK14", "PK13", "PK12", + "PK11", "PK10", "PK9", "PK8", + "PK7", "PK6", "PK5", "PK4"; + function = "gpio_in"; + }; + + mipia_pins_a: mipia@0 { + pins = "PK0", "PK1", "PK2", "PK3", "PK4", + "PK5", "PK6", "PK7", "PK8", "PK9"; + function = "mcsia"; + drive-strength = <10>; + + }; + + mipia_pins_b: mipia@1 { + pins = "PK0", "PK1", "PK2", "PK3", "PK4", + "PK5", "PK6", "PK7", "PK8", "PK9"; + function = "gpio_in"; + }; + + mipib_pins_a: mipib@0 { + pins = "PK10", "PK11", "PK12", "PK13", "PK14", + "PK15", "PK16", "PK17", "PK18", "PK19"; + function = "mcsib"; + drive-strength = <10>; + }; + + mipib_pins_b: mipib@1 { + pins = "PK10", "PK11", "PK12", "PK13", "PK14", + "PK15", "PK16", "PK17", "PK18", "PK19"; + function = "gpio_in"; + + }; + + mipic_pins_a: mipic@0 { + pins = "PK20", "PK21", "PK22", + "PK23", "PK24", "PK25"; + function = "mcsic"; + drive-strength = <10>; + + }; + + mipic_pins_b: mipic@1 { + pins = "PK20", "PK21", "PK22", + "PK23", "PK24", "PK25"; + function = "gpio_in"; + }; + + dsi0_4lane_pins_a: dsi0_4lane@0 { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; + function = "dsi0"; + drive-strength = <30>; + bias-disable; + }; + + dsi0_4lane_pins_b: dsi0_4lane@1 { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; + function = "io_disabled"; + bias-disable; + }; + + dsi1_4lane_pins_a: dsi1_4lane@0 { + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19"; + function = "dsi1"; + drive-strength = <30>; + bias-disable; + }; + + dsi1_4lane_pins_b: dsi1_4lane@1 { + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19"; + function = "io_disabled"; + bias-disable; + }; + + lvds0_pins_a: lvds0@0 { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; + function = "lvds0"; + drive-strength = <30>; + }; + + lvds0_pins_b: lvds0@1 { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9"; + function = "gpio_in"; + }; + + lvds1_pins_a: lvds1@0 { + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19"; + function = "lvds1"; + drive-strength = <30>; + }; + + lvds1_pins_b: lvds1@1 { + pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19"; + function = "gpio_in"; + }; + + lvds2_pins_a: lvds2@0 { + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", "PJ8", "PJ9"; + function = "lvds2"; + drive-strength = <30>; + }; + + lvds2_pins_b: lvds2@1 { + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", "PJ8", "PJ9"; + function = "gpio_in"; + }; + + lvds3_pins_a: lvds3@0 { + pins = "PJ10", "PJ11", "PJ12", "PJ13", "PJ14", "PJ15", "PJ16", "PJ17", "PJ18", "PJ19"; + function = "lvds3"; + drive-strength = <30>; + }; + + lvds3_pins_b: lvds3@1 { + pins = "PJ10", "PJ11", "PJ12", "PJ13", "PJ14", "PJ15", "PJ16", "PJ17", "PJ18", "PJ19"; + function = "gpio_in"; + }; + + rgb0_24pins_a: rgb0@0 { + pins = "PG0", "PG1", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PG2", "PG3", "PD6", "PD7", "PD8", "PD9", \ + "PD10", "PD11", "PG4", "PG5", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \ + "PD20", "PD21"; + function = "lcd0"; + drive-strength = <10>; + }; + + rgb0_24pins_b: rgb0@1 { + pins = "PG0", "PG1", "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PG2", "PG3", "PD6", "PD7", "PD8", "PD9", \ + "PD10", "PD11", "PG4", "PG5", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \ + "PD20", "PD21"; + function = "gpio_in"; + }; + + rgb1_24pins_a: rgb1@0 { + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", "PJ10", "PJ11", "PJ12", \ + "PJ13", "PJ14", "PJ15", "PJ16", "PJ17", "PJ18", "PJ19", "PJ20", "PJ21", "PJ22", "PJ23", "PJ24", \ + "PJ25", "PJ26", "PJ27"; + function = "lcd1"; + drive-strength = <10>; + }; + + rgb1_24pins_b: rgb1@1 { + pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", "PJ10", "PJ11", "PJ12", \ + "PJ13", "PJ14", "PJ15", "PJ16", "PJ17", "PJ18", "PJ19", "PJ20", "PJ21", "PJ22", "PJ23", "PJ24", \ + "PJ25", "PJ26", "PJ27"; + function = "gpio_in"; + }; + + test_pins_a: test_pins@0 { + pins = "PB9", "PB10"; + function = "test"; + drive-strength = <10>; + bias-pull-up; + }; + + test_pins_b: test_pins@1 { + pins = "PB9", "PB10"; + function = "gpio_in"; + }; + }; + + r_pio: pinctrl@7025000 { + #address-cells = <1>; + compatible = "allwinner,sun60iw2-r-pinctrl"; + reg = <0x0 0x07025000 0x0 0x410>; + interrupts = , /* GPIOL */ + ; + clocks = <&r_ccu CLK_R_APBS0>, <&dcxo24M>, <&rtc_ccu CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + wdt: watchdog@2050000 { + compatible = "allwinner,wdt-v103"; + reg = <0x0 0x02050000 0x0 0x20>; + interrupts = ; + }; + + dma: dma-controller@4601000 { + compatible = "allwinner,dma-v106"; + reg = <0x0 0x04601000 0x0 0x2000>; + interrupts = ; + clocks = <&ccu CLK_DMA0>, <&ccu CLK_MBUS_DMA0>; + clock-names = "bus", "mbus"; + dma-channels = <16>; + dma-requests = <64>; + resets = <&ccu RST_BUS_DMA0>; + #dma-cells = <1>; + }; + + sid: sid@3006000 { + compatible = "allwinner,sunxi-sid"; + reg = <0x0 0x03006000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + non-secure-maxoffset = <0x7C>; + non-secure-maxlen = <0x20>; + + secure_status { + reg = <0x0 0>; + offset = <0xa0>; + size = <0x4>; + }; + chipid { + reg = <0x0 0>; + offset = <0x200>; + size = <0x10>; + }; + rotpk { + reg = <0x0 0>; + offset = <0x140>; + size = <0x20>; + }; + ufs_cal_word_l { + offset = <0x260>; + mask = <0xfffffff>; + shift = <0>; + }; + ufs_cal_word_h { + offset = <0x264>; + mask = <0xfffffff>; + shift = <0>; + }; + dvfs_ori { + offset = <0x24C>; + mask = <0xff>; + shift = <8>; + }; + dvfs_bak { + offset = <0x24C>; + mask = <0xff>; + shift = <16>; + }; + }; + + sram_ctrl: sram_ctrl@3000000 { + compatible = "allwinner,sram_ctrl"; + reg = <0x0 0x03000000 0 0x184>; + soc_ver { + offset = <0x24>; + mask = <0x7>; + shift = <0>; + }; + }; + + ths: ths@2522000 { + compatible = "allwinner,sun60iw2p1-ths"; + reg = <0x0 0x02522000 0x0 0x500>; + clocks = <&ccu CLK_THS0>,<&ccu CLK_GPADC0_24M>; + clock-names = "bus","gpadc"; + resets = <&ccu RST_BUS_THS0>; + #thermal-sensor-cells = <1>; + }; + + nsi0: nsi-controller@2020000 { + compatible = "allwinner,sunxi-nsi-v2"; + interrupts = ; + reg = <0x0 0x02020000 0x0 0x10000>, + <0x0 0x0A030000 0x0 0x20000>; + clocks = <&ccu CLK_PLL_DDR>, <&ccu CLK_MBUS> , <&ccu CLK_NSI>, + <&ccu CLK_PLL_PERI0_600M>, <&ccu CLK_GIC>, <&ccu CLK_NSI_CFG>, + <&ccu CLK_PLL_PERI0_600M>, <&ccu CLK_DRAM0>; + clock-names = "pll", "bus", "nsi", "nsi-p","gic", "nsi-cfg", "bus-p", "cpu_direct"; + resets = <&ccu RST_BUS_NSI>, <&ccu RST_BUS_NSI_CFG>; + reset-names = "bus_nsi", "bus_nsi_cfg"; + clock-frequency = <600000000>,<600000000>; + #nsi-cells = <1>; + clk_path_type = <1>; + topology_type = <2>; + channel_type = <2>; + master_clks = <6 2>,<10 4>,<18 2>,<19 2>,<20 2>,<32 2>,<33 2>; + ia_pmu_data_unit = <16>; + ra_pmu_data_unit = <64>; + ta_pmu_data_unit = <64>; + cpu_pmu_data_unit = <64>; + sub_node_id_mapping; + + cpu0{ + id = <19>; + cpu_direct_reg = <0x0A030000 0x2000>; + cpu_direct_mux = <0x8000200 0x0 0>; + }; + cpu1{ + id = <20>; + cpu_direct_reg = <0x0A034000 0x2000>; + cpu_direct_mux = <0x8000200 0x0 0>; + }; + + npu{ + id = <18>; + power-domains = <&pd SUN60IW2_PCK_NPU>; + }; + + usb_pcie{ + id=<13>; + power-domains = <&pd SUN60IW2_PCK_PCIE>; + }; + + gpu{ + id = <6>; + power-domains = <&pd SUN60IW2_PCK_GPU_TOP>; + }; + + iommu0{ + id = <14>; + mode = <0>; + pri = <3>; + select = <1>; + }; + + iommu1{ + id = <15>; + mode = <0>; + pri = <3>; + select = <1>; + }; + + de { + id = <2>; + mode = <0>; + pri = <2>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + }; + + eink { + id = <3>; + mode = <0>; + pri = <1>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + }; + + di { + id = <4>; + mode = <0>; + pri = <1>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + }; + + g2d { + id = <5>; + mode = <0>; + pri = <1>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + }; + + ve0 { + id = <7>; + mode = <0>; + pri = <1>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_VE_DEC>; + }; + + ve1 { + id = <8>; + mode = <0>; + pri = <1>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_VE_DEC>; + }; + + ve2 { + id = <9>; + mode = <0>; + pri = <1>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_VE_ENC>; + }; + + + isp { + id = <16>; + mode = <0>; + pri = <2>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_VI>; + }; + + csi { + id = <17>; + mode = <0>; + pri = <2>; + select = <1>; + power-domains = <&pd SUN60IW2_PCK_VI>; + }; + }; + + pinctrl_test: pinctrl_test@2000000 { + reg = <0x0 0x0 0x0 0x0>; + compatible = "allwinner,sunxi-pinctrl-test"; + device_type = "pinctrl-test"; + pinctrl-0 = <&test_pins_a>; + pinctrl-1 = <&test_pins_b>; + pinctrl-names = "default", "sleep"; + test-gpios = <&r_pio PM 4 GPIO_ACTIVE_LOW>; + suspend-gpios = <&r_pio PM 5 GPIO_ACTIVE_LOW>; + wakeup-source; + interrupt-parent = <&pio>; + interrupts = ; + }; + + uart0: uart@2500000 { + compatible = "allwinner,uart-v100"; + reg = <0x0 0x02500000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <64>; + clocks = <&ccu CLK_UART0>; + resets = <&ccu RST_BUS_UART0>; + uart0_port = <0>; + uart0_type = <2>; + status = "disabled"; + }; + + uart1: uart@2501000 { + compatible = "allwinner,uart-v100"; + device_type = "uart1"; + reg = <0x0 0x02501000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <256>; + clocks = <&ccu CLK_UART1>; + resets = <&ccu RST_BUS_UART1>; + uart1_port = <1>; + uart1_type = <4>; + dmas = <&dma 15>,<&dma 15>; + dma-names = "fake_tx","fake_rx"; + //dma-names = "tx","rx"; + status = "disabled"; + }; + + uart2: uart@2502000 { + compatible = "allwinner,uart-v100"; + device_type = "uart2"; + reg = <0x0 0x02502000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <256>; + clocks = <&ccu CLK_UART2>; + resets = <&ccu RST_BUS_UART2>; + uart2_port = <2>; + uart2_type = <4>; + dmas = <&dma 16>,<&dma 16>; + dma-names = "fake_tx","fake_rx"; + //dma-names = "tx","rx"; + status = "disabled"; + }; + + uart3: uart@2503000 { + compatible = "allwinner,uart-v100"; + device_type = "uart3"; + reg = <0x0 0x02503000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <256>; + clocks = <&ccu CLK_UART3>; + resets = <&ccu RST_BUS_UART3>; + uart3_port = <3>; + uart3_type = <4>; + dmas = <&dma 17>,<&dma 17>; + dma-names = "fake_tx","fake_rx"; + //dma-names = "tx","rx"; + status = "disabled"; + }; + + uart4: uart@2504000 { + compatible = "allwinner,uart-v100"; + device_type = "uart4"; + reg = <0x0 0x02504000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <256>; + clocks = <&ccu CLK_UART4>; + resets = <&ccu RST_BUS_UART4>; + uart4_port = <4>; + uart4_type = <4>; + dmas = <&dma 18>,<&dma 18>; + dma-names = "fake_tx","fake_rx"; + //dma-names = "tx","rx"; + status = "disabled"; + }; + + uart5: uart@2505000 { + compatible = "allwinner,uart-v100"; + device_type = "uart5"; + reg = <0x0 0x02505000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <256>; + clocks = <&ccu CLK_UART5>; + resets = <&ccu RST_BUS_UART5>; + uart5_port = <5>; + uart5_type = <4>; + dmas = <&dma 19>,<&dma 19>; + dma-names = "fake_tx","fake_rx"; + //dma-names = "tx","rx"; + status = "disabled"; + }; + + uart6: uart@2506000 { + compatible = "allwinner,uart-v100"; + device_type = "uart6"; + reg = <0x0 0x02506000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <256>; + clocks = <&ccu CLK_UART6>; + resets = <&ccu RST_BUS_UART6>; + uart6_port = <6>; + uart6_type = <4>; + dmas = <&dma 20>,<&dma 20>; + dma-names = "fake_tx","fake_rx"; + //dma-names = "tx","rx"; + status = "disabled"; + }; + + uart7: uart@7080000 { + compatible = "allwinner,uart-v100"; + device_type = "uart7"; + reg = <0x0 0x07080000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <64>; + clocks = <&r_ccu CLK_R_UART0>; + resets = <&r_ccu RST_BUS_R_UART0>; + uart7_port = <7>; + uart7_type = <2>; + dmas = <&dma 50>,<&dma 50>; + dma-names = "fake_tx","fake_rx"; + //dma-names = "tx","rx"; + status = "disabled"; + }; + + uart8: uart@7081000 { + compatible = "allwinner,uart-v100"; + device_type = "uart8"; + reg = <0x0 0x07081000 0x0 0x400>; + interrupts = ; + sunxi,uart-fifosize = <64>; + clocks = <&r_ccu CLK_R_UART0>; + resets = <&r_ccu RST_BUS_R_UART1>; + uart8_port = <8>; + uart8_type = <2>; + dmas = <&dma 51>,<&dma 51>; + dma-names = "fake_tx","fake_rx"; + //dma-names = "tx","rx"; + status = "disabled"; + }; + + twi0: twi@2510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi0"; + reg = <0x0 0x02510000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI0>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI0>; + dmas = <&dma 37>, <&dma 37>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi1: twi@2511000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi1"; + reg = <0x0 0x02511000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI1>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI1>; + dmas = <&dma 38>, <&dma 38>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi2: twi@2512000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi2"; + reg = <0x0 0x02512000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI2>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI2>; + dmas = <&dma 39>, <&dma 39>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi3: twi@2513000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi3"; + reg = <0x0 0x02513000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI3>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI3>; + dmas = <&dma 40>, <&dma 40>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi4: twi@2514000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi4"; + reg = <0x0 0x02514000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI4>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI4>; + dmas = <&dma 41>, <&dma 41>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi5: twi@2515000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi5"; + reg = <0x0 0x02515000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI5>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI5>; + dmas = <&dma 42>, <&dma 42>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi6: twi@2516000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi6"; + reg = <0x0 0x02516000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI6>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI6>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi7: twi@2517000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi7"; + reg = <0x0 0x02517000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI7>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI7>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi8: twi@2518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi8"; + reg = <0x0 0x02518000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI8>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI8>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi9: twi@2519000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi9"; + reg = <0x0 0x02519000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI9>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI9>; + dmas = <&dma 58>, <&dma 58>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi10: twi@251A000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi10"; + reg = <0x0 0x0251A000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI10>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI10>; + dmas = <&dma 59>, <&dma 59>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi11: twi@251B000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi11"; + reg = <0x0 0x0251B000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI11>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI11>; + dmas = <&dma 60>, <&dma 60>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + twi12: twi@251C000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "twi12"; + reg = <0x0 0x0251C000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_TWI12>; + clock-names = "bus"; + resets = <&ccu RST_BUS_TWI12>; + dmas = <&dma 61>, <&dma 61>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + s_twi0: twi@7083000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "s_twi0"; + reg = <0x0 0x07083000 0x0 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_TWI0>; + clock-names = "bus"; + resets = <&r_ccu RST_BUS_R_TWI0>; + dmas = <&dma 47>, <&dma 47>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + s_twi1: twi@7084000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "s_twi1"; + reg = <0x0 0x07084000 0x0 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_TWI1>; + clock-names = "bus"; + resets = <&r_ccu RST_BUS_R_TWI1>; + dmas = <&dma 48>, <&dma 48>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + s_twi2: twi@7085000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-twi-v101"; + device_type = "s_twi2"; + reg = <0x0 0x07085000 0x0 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_TWI2>; + clock-names = "bus"; + resets = <&r_ccu RST_BUS_R_TWI2>; + dmas = <&dma 49>, <&dma 49>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + pwm0: pwm@2527000 { + #pwm-cells = <0x3>; + compatible = "allwinner,sunxi-pwm-v203"; + reg = <0x0 0x02527000 0x0 0x400>; + clocks = <&ccu CLK_PWM0>; + interrupts = ; + resets = <&ccu RST_BUS_PWM0>; + pwm-number = <10>; + pwm-base = <0x0>; + sunxi-pwms = <&pwm0_0>, <&pwm0_1>, <&pwm0_2>, <&pwm0_3>, <&pwm0_4>, + <&pwm0_5>, <&pwm0_6>, <&pwm0_7>, <&pwm0_8>, <&pwm0_9>; + status = "okay"; + }; + + pwm0_0: pwm0@2527010 { + compatible = "allwinner,sunxi-pwm0"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527010 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_1: pwm0@2527011 { + compatible = "allwinner,sunxi-pwm1"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527011 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_2: pwm0@2527012 { + compatible = "allwinner,sunxi-pwm2"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527012 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_3: pwm0@2527013 { + compatible = "allwinner,sunxi-pwm3"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527013 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_4: pwm0@2527014 { + compatible = "allwinner,sunxi-pwm4"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527014 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_5: pwm0@2527015 { + compatible = "allwinner,sunxi-pwm5"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527015 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_6: pwm0@2527016 { + compatible = "allwinner,sunxi-pwm6"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527016 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_7: pwm0@2527017 { + compatible = "allwinner,sunxi-pwm7"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527017 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_8: pwm0@2527018 { + compatible = "allwinner,sunxi-pwm8"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527018 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm0_9: pwm0@2527019 { + compatible = "allwinner,sunxi-pwm9"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02527019 0x0 0x4>; + reg_base = <0x02527000>; + status = "disabled"; + }; + + pwm1: pwm@2528000 { + #pwm-cells = <0x3>; + compatible = "allwinner,sunxi-pwm-v203"; + reg = <0x0 0x02528000 0x0 0x400>; + clocks = <&ccu CLK_PWM1>; + interrupts = ; + resets = <&ccu RST_BUS_PWM1>; + pwm-number = <10>; + pwm-base = <0xa>; + sunxi-pwms = <&pwm1_0>, <&pwm1_1>, <&pwm1_2>, <&pwm1_3>, + <&pwm1_4>, <&pwm1_5>, <&pwm1_6>, <&pwm1_7>, <&pwm1_8>, <&pwm1_9>; + status = "okay"; + }; + + pwm1_0: pwm1@2528010 { + compatible = "allwinner,sunxi-pwm10"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528010 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_1: pwm1@2528011 { + compatible = "allwinner,sunxi-pwm11"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528011 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_2: pwm1@2528012 { + compatible = "allwinner,sunxi-pwm12"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528012 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_3: pwm1@2528013 { + compatible = "allwinner,sunxi-pwm13"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528013 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_4: pwm1@2528014 { + compatible = "allwinner,sunxi-pwm14"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528014 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_5: pwm1@2528015 { + compatible = "allwinner,sunxi-pwm15"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528015 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_6: pwm1@2528016 { + compatible = "allwinner,sunxi-pwm16"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528016 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_7: pwm1@2528017 { + compatible = "allwinner,sunxi-pwm17"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528017 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_8: pwm1@2528018 { + compatible = "allwinner,sunxi-pwm18"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528018 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + pwm1_9: pwm1@2528019 { + compatible = "allwinner,sunxi-pwm19"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x02528019 0x0 0x4>; + reg_base = <0x02528000>; + status = "disabled"; + }; + + s_pwm0: pwm@7023000 { + #pwm-cells = <0x3>; + compatible = "allwinner,sunxi-pwm-v204"; + reg = <0x0 0x07023000 0x0 0x400>; + clocks = <&r_ccu CLK_R_PWM>,<&r_ccu CLK_R_BUS_PWM>; + interrupts = ; + clock-names = "clk_pwm","clk_bus_pwm"; + resets = <&r_ccu RST_BUS_R_PWM>; + pwm-number = <10>; + pwm-base = <0x14>; + sunxi-pwms = <&s_pwm0_0>, <&s_pwm0_1>, <&s_pwm0_2>, <&s_pwm0_3>, + <&s_pwm0_4>, <&s_pwm0_5>, <&s_pwm0_6>, <&s_pwm0_7>, <&s_pwm0_8>, <&s_pwm0_9>; + status = "okay"; + }; + + s_pwm0_0: s_pwm0@7023010 { + compatible = "allwinner,sunxi-pwm20"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023010 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_1: s_pwm0@7023011 { + compatible = "allwinner,sunxi-pwm21"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023011 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_2: s_pwm0@7023012 { + compatible = "allwinner,sunxi-pwm22"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023012 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_3: s_pwm0@7023013 { + compatible = "allwinner,sunxi-pwm23"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023013 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_4: s_pwm0@7023014 { + compatible = "allwinner,sunxi-pwm24"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023014 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_5: s_pwm0@7023015 { + compatible = "allwinner,sunxi-pwm25"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023015 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_6: s_pwm0@7023016 { + compatible = "allwinner,sunxi-pwm26"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023016 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_7: s_pwm0@7023017 { + compatible = "allwinner,sunxi-pwm27"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023017 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_8: s_pwm0@7023018 { + compatible = "allwinner,sunxi-pwm28"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023018 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + s_pwm0_9: s_pwm0@7023019 { + compatible = "allwinner,sunxi-pwm29"; + pinctrl-names = "active", "sleep"; + reg = <0x0 0x07023019 0x0 0x4>; + reg_base = <0x07023000>; + status = "disabled"; + }; + + lradc: lradc@2524000 { + compatible = "allwinner,keyboard_1350mv"; + reg = <0x0 0x02524000 0x0 0x100>; + interrupts = ; + clocks = <&ccu CLK_LRADC>; + resets = <&ccu RST_BUS_LRADC>; + status = "okay"; + }; + + gpadc0: gpadc@2521000 { + compatible = "allwinner,sunxi-gpadc-v101"; + reg = <0x0 0x02521000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_GPADC0>, <&ccu CLK_GPADC0_24M>; + clock-names = "bus", "hosc"; + resets = <&ccu RST_BUS_GPADC0>; + status = "disabled"; + }; + + irrx: irrx@2526000 { + compatible = "allwinner,irrx"; + reg = <0x0 0x02526000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_IRRX_GATE>, <&sys24M>, <&ccu CLK_IRRX>; + clock-names = "bus", "pclk", "mclk"; + resets = <&ccu RST_BUS_IRRX>; + status = "disabled"; + }; + + s_irrx: irrx@7040000 { + compatible = "allwinner,irrx"; + reg = <0x0 0x07040000 0x0 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_R_BUS_IRRX>, <&ccu CLK_PLL_REF>, <&r_ccu CLK_R_IRRX>; + clock-names = "bus", "pclk", "mclk"; + resets = <&r_ccu RST_BUS_R_IRRX>; + status = "disabled"; + }; + + irtx: irtx@2525000 { + compatible = "allwinner,irtx"; + reg = <0x0 0x02525000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_IRTX_GATE>, <&sys24M>, <&ccu CLK_IRTX>; + clock-names = "bus", "pclk", "mclk"; + resets = <&ccu RST_BUS_IRTX>; + status = "disabled"; + }; + + ledc: ledc@2520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-leds"; + reg = <0x0 0x02520000 0x0 0x400>; + interrupts = ; + clocks = <&ccu CLK_LEDC>, <&ccu CLK_BUS_LEDC>; + clock-names = "clk_ledc", "clk_cpuapb"; + resets = <&ccu RST_BUS_LEDC>; + reset-names = "ledc_reset"; + dmas = <&dma 46>; + dma-names = "tx"; + status = "disabled"; + }; + + npu: npu@3600000 { + compatible = "allwinner,npu"; + reg = <0x0 0x03600000 0x0 0x1000>; + device_type = "npu"; + dev_name = "npu"; + interrupts = ; + interrupt-names = "npu"; + clocks = <&ccu CLK_NPU>, <&ccu CLK_PLL_NPU>, <&ccu CLK_BUS_NPU>, <&ccu CLK_MBUS_NPU_GATE>, <&ccu CLK_NPU_AHB_GATE>; + clock-names = "clk_npu", "clk_parent", "clk_bus", "clk_mbus_gate", "clk_ahb_gate"; + operating-points-v2 = <&npu_opp_table>; + resets = <&ccu RST_BUS_NPU_CORE>, <&ccu RST_BUS_NPU_AXI>, <&ccu RST_BUS_NPU_AHB>; + reset-names = "npu_rst", "npu_axi_rst", "npu_ahb_rst"; + power-domains = <&pd SUN60IW2_PCK_NPU>; + npu-vf = <1008>; + status = "disable"; + }; + + hwspinlock: hwspinlock@3005000 { + compatible = "allwinner,sunxi-hwspinlock"; + reg = <0x0 0x3005000 0x0 0x1000>; + #hwlock-cells = <1>; + clocks = <&ccu CLK_SPINLOCK>; + clock-names = "clk_hwspinlock_bus"; + resets = <&ccu RST_BUS_SPINLOCK>; + reset-names = "rst"; + num-locks = <32>; + status = "disabled"; + }; + + /* + * channel0~3 : arm -> cpus + */ + msgbox: msgbox@3004000 { + compatible = "allwinner,sun60iw2-msgbox"; + #mbox-cells = <1>; + reg = <0x0 0x03004000 0x0 0x1000>, + <0x0 0x07094000 0x0 0x1000>; + interrupts = , + ; + clocks = <&ccu CLK_MSGBOX0>; + clock-names = "msgbox"; + resets = <&ccu RST_BUS_MSGBOX0>; + reset-names = "rst"; + local_id = <0>; + status = "disabled"; + }; + + a55_rproc: a55_rproc@0 { + compatible = "allwinner,arm64-rproc"; + status = "disabled"; + }; + + cryptoengine: ce@4603000 { + compatible = "allwinner,sunxi-ce"; + device_name = "ce"; + reg = <0x0 0x04603000 0x0 0xa0>, /* non-secure space */ + <0x0 0x04603800 0x0 0xa0>; /* secure space */ + interrupts = , /*non-secure*/ + ; /* secure*/ + clock-frequency = <400000000>; /* 400MHz */ + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>, + <&ccu CLK_PLL_PERI0_400M>, <&ccu CLK_CE_SYS>; + clock-names = "bus_ce", "ce_clk", "mbus_ce", "clk_src", "ce_sys_clk"; + resets = <&ccu RST_BUS_CE>; + status = "okay"; + }; + + usbc0: usbc0@10 { + device_type = "usbc0"; + compatible = "allwinner,sunxi-otg-manager"; + reg = <0x0 0x10 0x0 0x1000>; + usb_port_type = <2>; + usb_detect_type = <1>; + usb_detect_mode = <0>; + usb_id_gpio; + usb_det_vbus_gpio; + usb_regulator_io = "nocare"; + usb_wakeup_suspend = <0>; + usb_luns = <3>; + usb_serial_unique = <0>; + usb_serial_number = "20080411"; + rndis_wceis = <1>; + status = "disabled"; + }; + + udc:udc-controller@4100000 { + compatible = "allwinner,sunxi-udc"; + reg = <0x0 0x04100000 0x0 0x1000>, /* udc base */ + <0x0 0x00000000 0x0 0x100>; /* sram base */ + interrupts = ; + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB0_DEVICE>, <&ccu CLK_RES_DCAP_24M>, + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>; + clock-names = "hosc", "bus_otg", "res_dcap", "usb_sys_ahb", "msi_lite"; + resets = <&ccu RST_USB_0_DEVICE>, <&ccu RST_USB_0_PHY_RSTN>; + reset-names = "otg", "phy"; + aw,dma_addr_extend; + aw,dma_wordaddr_bypass = <0x1>; + status = "disabled"; + }; + + ehci0:ehci0-controller@4101000 { + compatible = "allwinner,sunxi-ehci0"; + reg = <0x0 0x04101000 0x0 0xFFF>, /*hci0 base*/ + <0x0 0x00000000 0x0 0x100>, /*sram base*/ + <0x0 0x04100000 0x0 0x1000>; /*otg base*/ + interrupts = ; + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB0_EHCI>, <&ccu CLK_RES_DCAP_24M>, + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>; + clock-names = "hosc", "bus_hci", "res_dcap", "usb_sys_ahb", "msi_lite"; + resets = <&ccu RST_USB_0_EHCI>, <&ccu RST_USB_0_PHY_RSTN>; + reset-names = "hci", "phy"; + hci_ctrl_no = <0>; + status = "disabled"; + }; + + ohci0:ohci0-controller@4101400 { + compatible = "allwinner,sunxi-ohci0"; + reg = <0x0 0x04101400 0x0 0xFFF>, /*hci0 base*/ + <0x0 0x00000000 0x0 0x100>, /*sram base*/ + <0x0 0x04100000 0x0 0x1000>; /*otg base*/ + interrupts = ; + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB0_OHCI>, <&ccu CLK_USB>, <&ccu CLK_RES_DCAP_24M>, + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>; + clock-names = "hosc", "bus_hci", "ohci", "res_dcap", "usb_sys_ahb", "msi_lite"; + resets = <&ccu RST_USB_0_OHCI>, <&ccu RST_USB_0_PHY_RSTN>; + reset-names = "hci", "phy"; + hci_ctrl_no = <0>; + status = "disabled"; + }; + + usbc1: usbc1@11 { + device_type = "usbc1"; + reg = <0x0 0x11 0x0 0x1000>; + usb_regulator_io = "nocare"; + usb_wakeup_suspend = <0>; + status = "disabled"; + }; + + ehci1: ehci1-controller@4200000 { + compatible = "allwinner,sunxi-ehci1"; + reg = <0x0 0x04200000 0x0 0xFFF>, /*ehci1 base*/ + <0x0 0x00000000 0x0 0x100>, /*sram base*/ + <0x0 0x04100000 0x0 0x1000>; /*otg base*/ + interrupts = ; + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB1_EHCI>, <&ccu CLK_RES_DCAP_24M>, + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>; + clock-names = "hosc", "bus_hci", "res_dcap", "usb_sys_ahb", "msi_lite"; + resets = <&ccu RST_USB_1_EHCI>, <&ccu RST_USB_1_PHY_RSTN>; + reset-names = "hci", "phy"; + hci_ctrl_no = <1>; + status = "disabled"; + }; + + ohci1: ohci1-controller@4200400 { + compatible = "allwinner,sunxi-ohci1"; + reg = <0x0 0x04200400 0x0 0xFFF>, /*ohci1 base*/ + <0x0 0x00000000 0x0 0x100>, /*sram base*/ + <0x0 0x04100000 0x0 0x1000>; /*otg base*/ + interrupts = ; + clocks = <&ccu CLK_USB_REF>, <&ccu CLK_USB1_OHCI>, <&ccu CLK_USB1>, <&ccu CLK_RES_DCAP_24M>, + <&ccu CLK_USB_SYS_AHB_GATE>, <&ccu CLK_MSI_LITE2>; + clock-names = "hosc", "bus_hci", "ohci", "res_dcap", "usb_sys_ahb", "msi_lite"; + resets = <&ccu RST_USB_1_OHCI>, <&ccu RST_USB_1_PHY_RSTN>; + reset-names = "hci", "phy"; + hci_ctrl_no = <1>; + status = "disabled"; + }; + + usbc2:usbc2@12 { + device_type = "usbc2"; + compatible = "allwinner,sunxi-plat-dwc3"; + reg = <0x0 0x12 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + aw,inv-sync-hdr-quirk; + status = "disabled"; + + xhci2: xhci2-controller@6a00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x06a00000 0x0 0x100000>; + interrupts = ; + dr_mode = "otg"; // dr_mode option: host, peripheral, otg + clocks = <&ccu CLK_USB2_MF>, <&ccu CLK_USB2_U2_REF>, <&ccu CLK_USB2_SUSPEND>; + clock-names = "bus_clk", "ref_clk", "suspend"; + assigned-clocks = <&ccu CLK_USB2_SUSPEND>; + assigned-clock-rates = <24000000>; + resets = <&ccu RST_USB_2>; + reset-names = "hci"; + power-domains = <&pd SUN60IW2_PCK_USB2>; + maximum-speed = "super-speed-plus"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; + phys = <&u2phy>, <&combo0_usb>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + }; + + u2phy: phy@6b00000 { + compatible = "allwinner,sunxi-plat-phy"; + reg = <0x0 0x06b00000 0x0 0x800>, /* Application Registers */ + <0x0 0x03000000 0x0 0x300>; /* SYSCFG Registers */ + reg-names = "u2_base", "res_base"; + clocks = <&ccu CLK_RES_DCAP_24M>; + clock-names = "res_dcap"; + aw,rext_mode = <2>; + aw,phy_tune_param = <0x143338D6>; + #phy-cells = <0>; + status = "disabled"; + }; + + vind0: vind@5800800 { + compatible = "allwinner,sunxi-vin-media", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + device_id = <0>; + csi_top = <600000000>; + csi_isp = <540000000>; + reg = <0x0 0x05800800 0x0 0x200>, + <0x0 0x05800000 0x0 0x800>, + <0x0 0x05810000 0x0 0x100>; + interrupts = ; + clocks = <&ccu CLK_CSI>, <&ccu CLK_PLL_VIDEO0_4X>, + <&ccu CLK_CSI_MASTER0>, <&sys24M>, <&ccu CLK_PLL_VIDEO0_3X>, + <&ccu CLK_CSI_MASTER1>, <&sys24M>, <&ccu CLK_PLL_VIDEO0_3X>, + <&ccu CLK_CSI_MASTER2>, <&sys24M>, <&ccu CLK_PLL_VIDEO0_3X>, + <&ccu CLK_ISP>, <&ccu CLK_PLL_VIDEO0_4X>, + <&ccu CLK_BUS_CSI>, <&ccu CLK_CSI_MBUS>, <&ccu CLK_ISP_MBUS>; + clock-names = "csi_top", "csi_top_src", + "csi_mclk0", "csi_mclk0_24m", "csi_mclk0_pll", + "csi_mclk1", "csi_mclk1_24m", "csi_mclk1_pll", + "csi_mclk2", "csi_mclk2_24m", "csi_mclk2_pll", + "csi_isp", "csi_isp_src", + "csi_bus", "csi_mbus", "csi_isp_mbus"; + resets = <&ccu RST_BUS_CSI>, <>; + reset-names = "csi_ret", "isp_ret"; + pinctrl-names = "mclk0-default", "mclk0-sleep", "mclk1-default", "mclk1-sleep", + "mclk2-default", "mclk2-sleep"; + pinctrl-0 = <&csi_mclk0_pins_a>; + pinctrl-1 = <&csi_mclk0_pins_b>; + pinctrl-2 = <&csi_mclk1_pins_a>; + pinctrl-3 = <&csi_mclk1_pins_b>; + pinctrl-4 = <&csi_mclk2_pins_a>; + pinctrl-5 = <&csi_mclk2_pins_b>; + power-domains = <&pd SUN60IW2_PCK_VI>; + status = "okay"; + + csi0: csi@5820000 { + compatible = "allwinner,sunxi-csi"; + reg = <0x0 0x05820000 0x0 0x1000>; + interrupts = ; + device_id = <0>; + status = "okay"; + }; + csi1: csi@5821000 { + compatible = "allwinner,sunxi-csi"; + reg = <0x0 0x05821000 0x0 0x1000>; + interrupts = ; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&ncsi0_8bit_pins_a>; + pinctrl-1 = <&ncsi0_8bit_pins_b>; + device_id = <1>; + status = "disabled"; + }; + csi2: csi@5822000 { + compatible = "allwinner,sunxi-csi"; + reg = <0x0 0x05822000 0x0 0x1000>; + interrupts = ; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&ncsi1_8bit_pins_a>; + pinctrl-1 = <&ncsi1_8bit_pins_b>; + device_id = <2>; + status = "disabled"; + }; + mipi0: mipi@5810100 { + compatible = "allwinner,sunxi-mipi"; + reg = <0x0 0x05810100 0x0 0x100>, + <0x0 0x05811000 0x0 0x400>; + interrupts = ; + pinctrl-names = "mipi0-default","mipi0-sleep"; + pinctrl-0 = <&mipia_pins_a>; + pinctrl-1 = <&mipia_pins_b>; + device_id = <0>; + status = "okay"; + }; + mipi1: mipi@5810200 { + compatible = "allwinner,sunxi-mipi"; + reg = <0x0 0x05810200 0x0 0x100>, + <0x0 0x05811400 0x0 0x400>; + pinctrl-names = "mipi1-default","mipi1-sleep"; + pinctrl-0 = <&mipib_pins_a>; + pinctrl-1 = <&mipib_pins_b>; + device_id = <1>; + status = "okay"; + }; + mipi2: mipi@5810300 { + compatible = "allwinner,sunxi-mipi"; + reg = <0x0 0x05810300 0x0 0x100>, + <0x0 0x05811800 0x0 0x400>; + pinctrl-names = "mipi2-default","mipi2-sleep"; + pinctrl-0 = <&mipic_pins_a>; + pinctrl-1 = <&mipic_pins_b>; + device_id = <2>; + status = "okay"; + }; + tdm0: tdm@5908000 { + compatible = "allwinner,sunxi-tdm"; + reg = <0x0 0x05908000 0x0 0x400>; + interrupts = ; + work_mode = <0x0>; + device_id = <0>; + iommus = <&mmu_aw 2 0>; + status = "okay"; + }; + isp00:isp@5900000 { + compatible = "allwinner,sunxi-isp"; + reg = <0x0 0x05900000 0x0 0x1300>; + interrupts = ; + work_mode = <0x0>; + device_id = <0>; + iommus = <&mmu_aw 2 0>; + status = "okay"; + }; + isp01:isp@58ffffc { + compatible = "allwinner,sunxi-isp"; + reg = <0x0 0x058ffffc 0x0 0x1304>; + interrupts = ; + work_mode = <0xff>; + device_id = <1>; + iommus = <&mmu_aw 2 0>; + status = "okay"; + }; + isp02:isp@58ffff8 { + compatible = "allwinner,sunxi-isp"; + reg = <0x0 0x058ffff8 0x0 0x1308>; + interrupts = ; + work_mode = <0xff>; + device_id = <2>; + iommus = <&mmu_aw 2 0>; + status = "okay"; + }; + isp03:isp@58ffff4 { + compatible = "allwinner,sunxi-isp"; + reg = <0x0 0x058ffff4 0x0 0x130c>; + interrupts = ; + work_mode = <0xff>; + device_id = <3>; + iommus = <&mmu_aw 2 0>; + status = "okay"; + }; + isp10:isp@4 { + compatible = "allwinner,sunxi-isp"; + device_id = <4>; + iommus = <&mmu_aw 2 0>; + status = "okay"; + }; + isp20:isp@5 { + compatible = "allwinner,sunxi-isp"; + device_id = <5>; + iommus = <&mmu_aw 2 0>; + status = "okay"; + }; + isp30:isp@6 { + compatible = "allwinner,sunxi-isp"; + device_id = <6>; + iommus = <&mmu_aw 2 0>; + status = "okay"; + }; + scaler00:scaler@5910000 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x05910000 0x0 0x400>; + interrupts = ; + work_mode = <0x0>; + device_id = <0>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler01:scaler@590fffc { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x0590fffc 0x0 0x404>; + work_mode = <0xff>; + device_id = <1>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler02:scaler@590fff8 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x0590fff8 0x0 0x408>; + work_mode = <0xff>; + device_id = <2>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler03:scaler@590fff4 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x0590fff4 0x0 0x40c>; + work_mode = <0xff>; + device_id = <3>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler10:scaler@5910400 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x05910400 0x0 0x400>; + interrupts = ; + work_mode = <0x0>; + device_id = <4>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler11:scaler@59103fc { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x059103fc 0x0 0x404>; + work_mode = <0xff>; + device_id = <5>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler12:scaler@59103f8 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x059103f8 0x0 0x408>; + work_mode = <0xff>; + device_id = <6>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler13:scaler@59103f4 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x059103f4 0x0 0x40c>; + work_mode = <0xff>; + device_id = <7>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler20:scaler@5910800 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x05910800 0x0 0x400>; + interrupts = ; + work_mode = <0x0>; + device_id = <8>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler21:scaler@59107fc { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x059107fc 0x0 0x404>; + work_mode = <0xff>; + device_id = <9>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler22:scaler@59107f8 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x059107f8 0x0 0x408>; + work_mode = <0xff>; + device_id = <10>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler23:scaler@59107f4 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x059107f4 0x0 0x40c>; + work_mode = <0xff>; + device_id = <11>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler30:scaler@5910c00 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x05910c00 0x0 0x400>; + interrupts = ; + work_mode = <0x0>; + device_id = <12>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler31:scaler@5910bfc { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x05910bfc 0x0 0x404>; + work_mode = <0xff>; + device_id = <13>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler32:scaler@5910bf8 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x05910bf8 0x0 0x408>; + work_mode = <0xff>; + device_id = <14>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler33:scaler@5910bf4 { + compatible = "allwinner,sunxi-scaler"; + reg = <0x0 0x05910bf4 0x0 0x40c>; + work_mode = <0xff>; + device_id = <15>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler40:scaler@16 { + compatible = "allwinner,sunxi-scaler"; + device_id = <16>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + scaler50:scaler@17 { + compatible = "allwinner,sunxi-scaler"; + device_id = <17>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + actuator0: actuator@2108180 { + compatible = "allwinner,sunxi-actuator"; + device_type = "actuator0"; + reg = <0x0 0x02108180 0x0 0x10>; + actuator0_name = "ad5820_act"; + actuator0_slave = <0x18>; + actuator0_af_pwdn = <>; + actuator0_afvdd = "afvcc-csi"; + actuator0_afvdd_vol = <2800000>; + status = "disabled"; + }; + flash0: flash@2108190 { + device_type = "flash0"; + compatible = "allwinner,sunxi-flash"; + reg = <0x0 0x02108190 0x0 0x10>; + flash0_type = <2>; + flash0_en = <>; + flash0_mode = <>; + flash0_flvdd = ""; + flash0_flvdd_vol = <>; + device_id = <0>; + status = "disabled"; + }; + sensor0: sensor@5812000 { + reg = <0x0 0x05812000 0x0 0x10>; + device_type = "sensor0"; + compatible = "allwinner,sunxi-sensor"; + sensor0_mname = "ov5640"; + sensor0_twi_cci_id = <2>; + sensor0_twi_addr = <0x78>; + sensor0_mclk_id = <0>; + sensor0_pos = "rear"; + sensor0_isp_used = <0>; + sensor0_fmt = <0>; + sensor0_stby_mode = <0>; + sensor0_vflip = <0>; + sensor0_hflip = <0>; + sensor0_iovdd-supply = <>; + sensor0_iovdd_vol = <>; + sensor0_avdd-supply = <>; + sensor0_avdd_vol = <>; + sensor0_dvdd-supply = <>; + sensor0_dvdd_vol = <>; + sensor0_power_en = <>; + sensor0_reset = <>; + sensor0_pwdn = <>; + sensor0_sm_vs = <>; + flash_handle = <&flash0>; + act_handle = <&actuator0>; + device_id = <0>; + status = "disabled"; + }; + sensor1: sensor@5812010 { + reg = <0x0 0x05812010 0x0 0x10>; + device_type = "sensor1"; + compatible = "allwinner,sunxi-sensor"; + sensor1_mname = "ov5647"; + sensor1_twi_cci_id = <3>; + sensor1_twi_addr = <0x6c>; + sensor1_mclk_id = <1>; + sensor1_pos = "front"; + sensor1_isp_used = <0>; + sensor1_fmt = <0>; + sensor1_stby_mode = <0>; + sensor1_vflip = <0>; + sensor1_hflip = <0>; + sensor1_iovdd-supply = <>; + sensor1_iovdd_vol = <>; + sensor1_avdd-supply = <>; + sensor1_avdd_vol = <>; + sensor1_dvdd-supply = <>; + sensor1_dvdd_vol = <>; + sensor1_power_en = <>; + sensor1_reset = <>; + sensor1_pwdn = <>; + sensor1_sm_vs = <>; + flash_handle = <>; + act_handle = <>; + device_id = <1>; + status = "disabled"; + }; + sensor2: sensor@5812020 { + reg = <0x0 0x05812020 0x0 0x10>; + device_type = "sensor2"; + compatible = "allwinner,sunxi-sensor"; + sensor2_mname = "imx386_mipi"; + sensor2_twi_cci_id = <3>; + sensor2_twi_addr = <0x6c>; + sensor2_mclk_id = <1>; + sensor2_pos = "rear"; + sensor2_isp_used = <0>; + sensor2_fmt = <0>; + sensor2_stby_mode = <0>; + sensor2_vflip = <0>; + sensor2_hflip = <0>; + sensor2_iovdd-supply = <>; + sensor2_iovdd_vol = <>; + sensor2_avdd-supply = <>; + sensor2_avdd_vol = <>; + sensor2_dvdd-supply = <>; + sensor2_dvdd_vol = <>; + sensor2_power_en = <>; + sensor2_reset = <>; + sensor2_pwdn = <>; + sensor2_sm_vs = <>; + flash_handle = <>; + act_handle = <>; + device_id = <2>; + status = "disabled"; + }; + sensor_list0:sensor_list@5812040 { + reg = <0x0 0x05812040 0x0 0x10>; + device_type = "sensor_list0"; + compatible = "allwinner,sunxi-sensor-list"; + csi_sel = <0>; + sensor00_mname = "ov5675_mipi_b"; + sensor00_twi_addr = <0x60>; + sensor00_type = <1>; + sensor00_hflip = <1>; + sensor00_vflip = <0>; + sensor00_act_used = <1>; + sensor00_act_name = "dw9714_act"; + sensor00_act_twi_addr = <0x18>; + sensor01_mname = "gc05a2_mipi_b"; + sensor01_twi_addr = <0x62>; + sensor01_type = <1>; + sensor01_hflip = <0>; + sensor01_vflip = <0>; + sensor01_act_used = <1>; + sensor01_act_name = "dw9714_act"; + sensor01_act_twi_addr = <0x18>; + sensor02_mname = "gc5035_mipi_b"; + sensor02_twi_addr = <0x64>; + sensor02_type = <1>; + sensor02_hflip = <0>; + sensor02_vflip = <0>; + sensor02_act_used = <1>; + sensor02_act_name = "dw9714_act"; + sensor02_act_twi_addr = <0x18>; + device_id = <0>; + status = "disabled"; + }; + sensor_list1:sensor_list@5812050 { + reg = <0x0 0x05812050 0x0 0x10>; + device_type = "sensor_list1"; + compatible = "allwinner,sunxi-sensor-list"; + csi_sel = <0>; + sensor10_mname = "ov02a10_mipi_f"; + sensor10_twi_addr = <0x70>; + sensor10_type = <1>; + sensor10_hflip = <1>; + sensor10_vflip = <0>; + sensor10_act_used = <0>; + sensor10_act_name = ""; + sensor10_act_twi_addr = <>; + sensor11_mname = "gc02m1_mipi_f"; + sensor11_twi_addr = <0x72>; + sensor11_type = <1>; + sensor11_hflip = <1>; + sensor11_vflip = <0>; + sensor11_act_used = <0>; + sensor11_act_name = ""; + sensor11_act_twi_addr = <>; + sensor12_mname = "gc02m2_mipi_f"; + sensor12_twi_addr = <0x74>; + sensor12_type = <1>; + sensor12_hflip = <0>; + sensor12_vflip = <0>; + sensor12_act_used = <0>; + sensor12_act_name = ""; + sensor12_act_twi_addr = <>; + device_id = <1>; + status = "disabled"; + }; + vinc00:vinc@5830000 { + device_type = "vinc0"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05830000 0x0 0x1000>; + interrupts = ; + vinc0_csi_sel = <1>; + vinc0_mipi_sel = <0xff>; + vinc0_isp_sel = <0>; + vinc0_isp_tx_ch = <0>; + vinc0_tdm_rx_sel = <0>; + vinc0_rear_sensor_sel = <0>; + vinc0_front_sensor_sel = <0>; + vinc0_sensor_list = <0>; + device_id = <0>; + work_mode = <0x0>; + iommus = <&mmu_aw 1 0>; + status = "okay"; + }; + vinc01:vinc@582fffc { + device_type = "vinc1"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x0582fffc 0x0 0x1004>; + vinc1_csi_sel = <1>; + vinc1_mipi_sel = <0xff>; + vinc1_isp_sel = <1>; + vinc1_isp_tx_ch = <0>; + vinc1_tdm_rx_sel = <1>; + vinc1_rear_sensor_sel = <0>; + vinc1_front_sensor_sel = <0>; + vinc1_sensor_list = <0>; + device_id = <1>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + + vinc02:vinc@582fff8 { + device_type = "vinc2"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x0582fff8 0x0 0x1008>; + vinc2_csi_sel = <2>; + vinc2_mipi_sel = <0xff>; + vinc2_isp_sel = <2>; + vinc2_isp_tx_ch = <2>; + vinc2_tdm_rx_sel = <2>; + vinc2_rear_sensor_sel = <0>; + vinc2_front_sensor_sel = <0>; + vinc2_sensor_list = <0>; + device_id = <2>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc03:vinc@582fff4 { + device_type = "vinc3"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x0582fff4 0x0 0x100c>; + vinc3_csi_sel = <0>; + vinc3_mipi_sel = <0xff>; + vinc3_isp_sel = <0>; + vinc3_isp_tx_ch = <0>; + vinc3_tdm_rx_sel = <0>; + vinc3_rear_sensor_sel = <1>; + vinc3_front_sensor_sel = <1>; + vinc3_sensor_list = <0>; + device_id = <3>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc10:vinc@5831000 { + device_type = "vinc4"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05831000 0x0 0x1000>; + interrupts = ; + vinc4_csi_sel = <1>; + vinc4_mipi_sel = <0xff>; + vinc4_isp_sel = <0>; + vinc4_isp_tx_ch = <0>; + vinc4_tdm_rx_sel = <0>; + vinc4_rear_sensor_sel = <0>; + vinc4_front_sensor_sel = <0>; + vinc4_sensor_list = <0>; + device_id = <4>; + work_mode = <0x0>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc11:vinc@5830ffc { + device_type = "vinc5"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05830ffc 0x0 0x1004>; + vinc5_csi_sel = <2>; + vinc5_mipi_sel = <0xff>; + vinc5_isp_sel = <1>; + vinc5_isp_tx_ch = <1>; + vinc5_tdm_rx_sel = <1>; + vinc5_rear_sensor_sel = <0>; + vinc5_front_sensor_sel = <0>; + vinc5_sensor_list = <0>; + device_id = <5>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc12:vinc@5830ff8 { + device_type = "vinc6"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05830ff8 0x0 0x1008>; + vinc6_csi_sel = <2>; + vinc6_mipi_sel = <0xff>; + vinc6_isp_sel = <0>; + vinc6_isp_tx_ch = <0>; + vinc6_tdm_rx_sel = <0>; + vinc6_rear_sensor_sel = <0>; + vinc6_front_sensor_sel = <0>; + vinc6_sensor_list = <0>; + device_id = <6>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc13:vinc@5830ff4 { + device_type = "vinc7"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05830ff4 0x0 0x100c>; + vinc7_csi_sel = <2>; + vinc7_mipi_sel = <0xff>; + vinc7_isp_sel = <0>; + vinc7_isp_tx_ch = <0>; + vinc7_tdm_rx_sel = <0>; + vinc7_rear_sensor_sel = <0>; + vinc7_front_sensor_sel = <0>; + vinc7_sensor_list = <0>; + device_id = <7>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc20:vinc@5832000 { + device_type = "vinc8"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05832000 0x0 0x1000>; + interrupts = ; + vinc8_csi_sel = <2>; + vinc8_mipi_sel = <0xff>; + vinc8_isp_sel = <4>; + vinc8_isp_tx_ch = <3>; + vinc8_tdm_rx_sel = <3>; + vinc8_rear_sensor_sel = <0>; + vinc8_front_sensor_sel = <0>; + vinc8_sensor_list = <0>; + device_id = <8>; + work_mode = <0x0>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc21:vinc@5831ffc { + device_type = "vinc9"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05831ffc 0x0 0x1004>; + vinc9_csi_sel = <2>; + vinc9_mipi_sel = <0xff>; + vinc9_isp_sel = <0>; + vinc9_isp_tx_ch = <0>; + vinc9_tdm_rx_sel = <0>; + vinc9_rear_sensor_sel = <0>; + vinc9_front_sensor_sel = <0>; + vinc9_sensor_list = <0>; + device_id = <9>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc22:vinc@5831ff8 { + device_type = "vinc10"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05831ff8 0x0 0x1008>; + vinc10_csi_sel = <2>; + vinc10_mipi_sel = <0xff>; + vinc10_isp_sel = <0>; + vinc10_isp_tx_ch = <0>; + vinc10_tdm_rx_sel = <0>; + vinc10_rear_sensor_sel = <0>; + vinc10_front_sensor_sel = <0>; + vinc10_sensor_list = <0>; + device_id = <10>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc23:vinc@5831ff4 { + device_type = "vinc11"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05831ff4 0x0 0x100c>; + vinc11_csi_sel = <2>; + vinc11_mipi_sel = <0xff>; + vinc11_isp_sel = <0>; + vinc11_isp_tx_ch = <0>; + vinc11_tdm_rx_sel = <0>; + vinc11_rear_sensor_sel = <0>; + vinc11_front_sensor_sel = <0>; + vinc11_sensor_list = <0>; + device_id = <11>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc30:vinc@5833000 { + device_type = "vinc12"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05833000 0x0 0x1000>; + interrupts = ; + vinc12_csi_sel = <2>; + vinc12_mipi_sel = <0xff>; + vinc12_isp_sel = <0>; + vinc12_isp_tx_ch = <0>; + vinc12_tdm_rx_sel = <0>; + vinc12_rear_sensor_sel = <0>; + vinc12_front_sensor_sel = <0>; + vinc12_sensor_list = <0>; + device_id = <12>; + work_mode = <0x0>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc31:vinc@5832ffc { + device_type = "vinc13"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05832ffc 0x0 0x1004>; + vinc13_csi_sel = <2>; + vinc13_mipi_sel = <0xff>; + vinc13_isp_sel = <0>; + vinc13_isp_tx_ch = <0>; + vinc13_tdm_rx_sel = <0>; + vinc13_rear_sensor_sel = <0>; + vinc13_front_sensor_sel = <0>; + vinc13_sensor_list = <0>; + device_id = <13>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc32:vinc@5832ff8 { + device_type = "vinc14"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05832ff8 0x0 0x1008>; + vinc14_csi_sel = <2>; + vinc14_mipi_sel = <0xff>; + vinc14_isp_sel = <0>; + vinc14_isp_tx_ch = <0>; + vinc14_tdm_rx_sel = <0>; + vinc14_rear_sensor_sel = <0>; + vinc14_front_sensor_sel = <0>; + vinc14_sensor_list = <0>; + device_id = <14>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc33:vinc@5832ff4 { + device_type = "vinc15"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05832ff4 0x0 0x100c>; + vinc15_csi_sel = <2>; + vinc15_mipi_sel = <0xff>; + vinc15_isp_sel = <0>; + vinc15_isp_tx_ch = <0>; + vinc15_tdm_rx_sel = <0>; + vinc15_rear_sensor_sel = <0>; + vinc15_front_sensor_sel = <0>; + vinc15_sensor_list = <0>; + device_id = <15>; + work_mode = <0xff>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc40:vinc@5834000 { + device_type = "vinc16"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05834000 0x0 0x1000>; + interrupts = ; + vinc16_csi_sel = <2>; + vinc16_mipi_sel = <0xff>; + vinc16_isp_sel = <0>; + vinc16_isp_tx_ch = <0>; + vinc16_tdm_rx_sel = <0>; + vinc16_rear_sensor_sel = <0>; + vinc16_front_sensor_sel = <0>; + vinc16_sensor_list = <0>; + device_id = <16>; + work_mode = <0x0>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + vinc50:vinc@5835000 { + device_type = "vinc17"; + compatible = "allwinner,sunxi-vin-core"; + reg = <0x0 0x05835000 0x0 0x1000>; + interrupts = ; + vinc17_csi_sel = <2>; + vinc17_mipi_sel = <0xff>; + vinc17_isp_sel = <0>; + vinc17_isp_tx_ch = <0>; + vinc17_tdm_rx_sel = <0>; + vinc17_rear_sensor_sel = <0>; + vinc17_front_sensor_sel = <0>; + vinc17_sensor_list = <0>; + device_id = <17>; + work_mode = <0x0>; + iommus = <&mmu_aw 1 0>; + status = "disabled"; + }; + }; + + di:deinterlace@5400000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-deinterlace"; + reg = <0x0 0x05400000 0x0 0x040000>; + interrupts = ; + iommus = <&mmu_aw 9 1>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + status = "okay"; + + clocks = <&ccu CLK_DI>, <&ccu CLK_DI_GATE>; + clock-names = "clk_di", "clk_bus_di"; + clock-frequency = <300000000>; + + resets = <&ccu RST_BUS_DI>, <&ccu RST_BUS_DE_SY>; + reset-names = "rst_bus_di", "rst_bus_desys"; + }; + + g2d: g2d@5440000 { + compatible = "allwinner,sunxi-g2d"; + reg = <0x0 0x05440000 0x0 0x30000>; + interrupts = ; + clocks = <&ccu CLK_G2D_GATE>, <&ccu CLK_G2D>, + <&ccu CLK_MBUS_DESYS_GATE>, <&ccu CLK_DE_AHB_GATE>; + clock-names = "bus", "g2d", "mbus_desys", "ahb_de"; + resets = <&ccu RST_BUS_G2D>, <&ccu RST_BUS_DE_SY>; + reset-names = "rst_bus_g2d", "rst_bus_desys"; + iommus = <&mmu_aw 10 1>; + //nsi = <&nsi0 5>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + power-domain-names = "pd_de_sys"; + assigned-clocks = <&ccu CLK_G2D>; + assigned-clock-rates = <300000000>; + }; + + pd_vi_test: pd_vi_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_VI>; + status = "okay"; + }; + + pd_ve_dec_test: pd_ve_dec_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_VE_DEC>; + status = "okay"; + }; + + pd_ve_enc_test: pd_ve_enc_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_VE_ENC>; + status = "okay"; + }; + + pd_npu_test: pd_npu_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_NPU>; + status = "okay"; + }; + + pd_gpu_top_test: pd_gpu_top_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_GPU_TOP>; + status = "okay"; + }; + + pd_gpu_core_test: pd_gpu_core_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_GPU_CORE>; + status = "okay"; + }; + + pd_pcie_test: pd_pcie_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_PCIE>; + status = "okay"; + }; + + pd_usb2_test: pd_usb2_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_USB2>; + status = "okay"; + }; + + pd_de_sys_test: pd_de_sys_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + status = "okay"; + }; + + pd_vo_test: pd_vo_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_VO>; + status = "okay"; + }; + + pd_vo1_test: pd_vo1_test@0 { + compatible = "allwinner,sunxi-power-domain-test"; + power-domains = <&pd SUN60IW2_PCK_VO1>; + status = "okay"; + }; + + gmac_stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 16 8 4>; + }; + + gmac_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac_mtl_tx_setup: tx_queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0: ethernet@4500000 { + compatible = "allwinner,sunxi-gmac-210", "snps,dwmac-5.20"; + reg = <0x0 0x04500000 0x0 0x8000>, <0x0 0x04508000 0x0 0x1000>; + interrupts = , , + , ; + interrupt-names = "macirq", "eth_lpi", "tx0_irq", "rx0_irq"; + clocks = <&ccu CLK_GMAC0>, <&ccu CLK_GMAC0_MBUS>, <&ccu CLK_GMAC0_PHY>, <&ccu CLK_GMAC_PTP>; + clock-names = "stmmaceth", "pclk", "phy", "ptp_ref"; + assigned-clocks = <&ccu CLK_GMAC0_PHY>; + assigned-clock-rates = <25000000>; + resets = <&ccu RST_BUS_GMAC0_AXI>, <&ccu RST_BUS_GMAC0>; + reset-names = "stmmaceth", "ahb"; + phy-mode = "rgmii"; + phy-handle = <&gmac0_phy0>; + status = "disabled"; + + aw,rgmii-clk-ext; + snps,fixed-burst; + snps,en-tx-lpi-clockgating; + snps,axi-config = <&gmac_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac_mtl_tx_setup>; + + mdio0: mdio0@0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + gmac0_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + max-speed = <1000>; /* Max speed capability */ + reset-gpios = <&pio PA 14 GPIO_ACTIVE_LOW>; + /* PHY datasheet rst time */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; + }; + }; + }; + + gmac1: ethernet@4510000 { + compatible = "allwinner,sunxi-gmac-210", "snps,dwmac-5.20"; + reg = <0x0 0x04510000 0x0 0x8000>, <0x0 0x04518000 0x0 0x1000>; + interrupts = , , + , ; + interrupt-names = "macirq", "eth_lpi", "tx0_irq", "rx0_irq"; + clocks = <&ccu CLK_GMAC1>, <&ccu CLK_GMAC1_MBUS>, <&ccu CLK_GMAC1_PHY>, <&ccu CLK_GMAC_PTP>; + clock-names = "stmmaceth", "pclk", "phy25m", "ptp_ref"; + assigned-clocks = <&ccu CLK_GMAC1_PHY>; + assigned-clock-rates = <25000000>; + resets = <&ccu RST_BUS_GMAC1_AXI>, <&ccu RST_BUS_GMAC1>; + reset-names = "stmmaceth", "ahb"; + phy-mode = "rgmii"; + phy-handle = <&gmac1_phy0>; + status = "disabled"; + + aw,rgmii-clk-ext; + snps,fixed-burst; + snps,en-tx-lpi-clockgating; + snps,axi-config = <&gmac_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac_mtl_tx_setup>; + + mdio1: mdio1@0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + gmac1_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + max-speed = <1000>; /* Max speed capability */ + reset-gpios = <&pio PA 14 GPIO_ACTIVE_LOW>; + /* PHY datasheet rst time */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; + }; + }; + }; + + uio0: uio@4500000 { + compatible = "allwinner,sunxi-uio"; + reg = <0x0 0x04500000 0x0 0x10000>; + sunxi,ethernet = <&gmac0>; + status = "disabled"; + }; + + uio1: uio@4510000 { + compatible = "allwinner,sunxi-uio"; + reg = <0x0 0x04510000 0x0 0x10000>; + sunxi,ethernet = <&gmac1>; + status = "disabled"; + }; + + rfkill: rfkill { + compatible = "allwinner,sunxi-rfkill"; + status = "disabled"; + }; + + addr_mgt: addr_mgt { + compatible = "allwinner,sunxi-addr_mgt"; + status = "disabled"; + }; + + btlpm: btlpm { + compatible = "allwinner,sunxi-btlpm"; + }; + + spi0: spi@2540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-spi-v1.3"; + device_type = "spi0"; + reg = <0x0 0x02540000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>; + clock-names = "pll", "mod", "bus"; + clock-frequency = <100000000>; + resets = <&ccu RST_BUS_SPI0>; + dmas = <&dma 23>, <&dma 23>; + dma-names = "tx", "rx"; + sunxi,spi-num-cs = <2>; + status = "disabled"; + }; + + spi1: spi@2541000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-spi-v1.4"; + device_type = "spi1"; + reg = <0x0 0x02541000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI1>, <&ccu CLK_BUS_SPI1>; + clock-names = "pll", "mod", "bus"; + clock-frequency = <100000000>; + resets = <&ccu RST_BUS_SPI1>; + dmas = <&dma 24>, <&dma 24>; + dma-names = "tx", "rx"; + sunxi,spi-num-cs = <1>; + status = "disabled"; + }; + + spi2: spi@2542000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-spi-v1.3"; + device_type = "spi2"; + reg = <0x0 0x02542000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI2>, <&ccu CLK_BUS_SPI2>; + clock-names = "pll", "mod", "bus"; + clock-frequency = <100000000>; + resets = <&ccu RST_BUS_SPI2>; + dmas = <&dma 25>, <&dma 25>; + dma-names = "tx", "rx"; + sunxi,spi-num-cs = <1>; + status = "disabled"; + }; + + spi3: spi@2543000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-spi-v1.3"; + device_type = "spi3"; + reg = <0x0 0x02543000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI3>, <&ccu CLK_BUS_SPI3>; + clock-names = "pll", "mod", "bus"; + clock-frequency = <100000000>; + resets = <&ccu RST_BUS_SPI3>; + dmas = <&dma 26>, <&dma 26>; + dma-names = "tx", "rx"; + sunxi,spi-num-cs = <1>; + status = "disabled"; + }; + + spi4: spi@2544000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-spi-v1.3"; + device_type = "spi4"; + reg = <0x0 0x02544000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_PLL_PERI0_300M>, <&ccu CLK_SPI4>, <&ccu CLK_BUS_SPI4>; + clock-names = "pll", "mod", "bus"; + clock-frequency = <100000000>; + resets = <&ccu RST_BUS_SPI4>; + dmas = <&dma 54>, <&dma 54>; + dma-names = "tx", "rx"; + sunxi,spi-num-cs = <1>; + status = "disabled"; + }; + + r_spi: spi@7092000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "allwinner,sunxi-spi-v1.3"; + device_type = "r_spi"; + reg = <0x0 0x07092000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_PLL_PERI0_300M>, <&r_ccu CLK_R_SPI>, <&r_ccu CLK_R_BUS_SPI>; + clock-names = "pll", "mod", "bus"; + clock-frequency = <100000000>; + resets = <&r_ccu RST_BUS_R_SPI>; + dmas = <&dma 53>, <&dma 53>; + dma-names = "tx", "rx"; + sunxi,spi-num-cs = <1>; + status = "disabled"; + }; + + serdes: serdes@6c00000 { + compatible = "allwinner,cadence-combophy"; + reg = <0x0 0x06c00000 0x0 0x400>, /* serdes top register part-1 */ + <0x0 0x06c06000 0x0 0x2000>, /* serdes top register part-2 */ + <0x0 0x0709016c 0x0 0x4>; /* sys-rtc */ + clocks = <&ccu CLK_SERDES_PHY_CFG>, + <&rtc_ccu CLK_RTC_DCXO_SERDES0>, + <&rtc_ccu CLK_RTC_DCXO_SERDES1>; + clock-names = "serdes-clk", + "dcxo-serdes0-clk", + "dcxo-serdes1-clk"; + resets = <&ccu RST_BUS_SERDES>; + reset-names = "serdes-reset"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + combophy0: combo-phy0@6c01000 { + reg = <0x0 0x06c01000 0x0 0xa00>, /* combophy0 top register */ + <0x0 0x06c80000 0x0 0x20000>; /* combophy0 phy register*/ + combo0_dp: combo0-dp-phy { + #phy-cells = <0>; + status = "okay"; + }; + combo0_usb: combo0-usb-phy { + #phy-cells = <0>; + status = "okay"; + }; + }; + + combophy1: combo-phy1@6c02000 { + reg = <0x0 0x06c02000 0x0 0xa00>, /* combophy1 top register */ + <0x0 0x06ca0000 0x0 0x20000>; /* combophy1 phy register*/ + combo1_usb: combo1-usb-phy { + #phy-cells = <0>; + status = "okay"; + }; + combo1_pcie: combo1-pcie-phy { + #phy-cells = <0>; + status = "okay"; + }; + }; + + aux_hpd: aux-hpd@6c01e00 { + reg = <0x0 0x06c01e00 0x0 0x200>; /* aux_hpd top register */ + aux_hpd_phy: aux-hpd-phy { + #phy-cells = <0>; + status = "okay"; + }; + }; + }; + + sunxi_drm: sunxi-drm { + compatible = "allwinner,sunxi-drm"; + fb_base = <0>; + status = "okay"; + }; + + de: de@5000000 { + compatible = "allwinner,display-engine-v352"; + iommus = <&mmu_aw 8 1>; + nsi = <&nsi0 2>; + power-domains = <&pd SUN60IW2_PCK_DE_SYS>; + reg = <0x0 0x5000000 0x0 0x400000>; + interrupts = , + ; + clocks = <&ccu CLK_DE0>, + <&ccu CLK_BUS_DE0>, + <&ccu CLK_DE_AHB_GATE>, + <&ccu CLK_MBUS_DESYS_GATE>; + clock-names = "clk_de", + "clk_bus_de", + "ahb_vid_out", + "mbus_vo_sys"; + resets = <&ccu RST_BUS_DE0>, + <&ccu RST_BUS_DE_SY>; + reset-names = "rst_bus_de", + "rst_bus_de_sys"; + assigned-clocks = <&ccu CLK_DE0>; + assigned-clock-parents = <&ccu CLK_PLL_DE_3X>; + assigned-clock-rates = <600000000>; + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + disp0: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + disp0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_disp0>; + }; + disp0_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_disp0>; + }; + disp0_out_tcon2: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon2_in_disp0>; + }; + disp0_out_tcon3: endpoint@3 { + reg = <4>; + remote-endpoint = <&tcon3_in_disp0>; + }; + disp0_out_tcon4: endpoint@4 { + reg = <5>; + remote-endpoint = <&tcon4_in_disp0>; + }; + }; + disp1: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + disp1_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_disp1>; + }; + disp1_out_tcon1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon1_in_disp1>; + }; + disp1_out_tcon2: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon2_in_disp1>; + }; + disp1_out_tcon3: endpoint@3 { + reg = <4>; + remote-endpoint = <&tcon3_in_disp1>; + }; + disp1_out_tcon4: endpoint@4 { + reg = <5>; + remote-endpoint = <&tcon4_in_disp1>; + }; + }; + }; + }; + + vo0: vo0@5500000 { + compatible = "allwinner,tcon-top0"; + reg = <0x0 0x05500000 0x0 0x1000>; + clocks = <&ccu CLK_DPSS_TOP0>, + <&ccu CLK_VID_OUT0_AHB_GATE>; + clock-names = "clk_bus_dpss_top", + "clk_ahb_gate"; + resets = <&ccu RST_BUS_DPSS_TOP0>, + <&ccu RST_BUS_VIDEO_OUT0>; + reset-names = "rst_bus_dpss_top", + "rst_bus_reg"; + power-domains = <&pd SUN60IW2_PCK_VO>; + status = "disabled"; + }; + + vo1: vo1@5510000 { + compatible = "allwinner,tcon-top1"; + reg = <0x0 0x05510000 0x0 0x1000>; + clocks = <&ccu CLK_DPSS_TOP1>, + <&ccu CLK_VID_OUT1_AHB_GATE>; + clock-names = "clk_bus_dpss_top", + "clk_ahb_gate"; + resets = <&ccu RST_BUS_DPSS_TOP1>, + <&ccu RST_BUS_VIDEO_OUT1>; + reset-names = "rst_bus_dpss_top", + "rst_bus_reg"; + power-domains = <&pd SUN60IW2_PCK_VO1>; + status = "disabled"; + }; + + dlcd0: tcon0@5501000 { + compatible = "allwinner,tcon-lcd"; + reg = <0x0 0x05501000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_VO0_TCONLCD0>; + clock-names = "clk_bus_tcon"; + resets = <&ccu RST_BUS_VO0_TCONLCD0>; + reset-names = "rst_bus_tcon"; + top = <&vo0>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + tcon0_in_disp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&disp0_out_tcon0>; + }; + tcon0_in_disp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&disp1_out_tcon0>; + }; + }; + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + tcon0_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_tcon0>; + }; + tcon0_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_tcon0>; + }; + tcon0_out_lvds0: endpoint@2 { + reg = <2>; + remote-endpoint = <&lvds0_in_tcon0>; + }; + tcon0_out_rgb0: endpoint@3 { + reg = <3>; + remote-endpoint = <&rgb0_in_tcon0>; + }; + }; + }; + }; + + dlcd1: tcon1@5502000 { + compatible = "allwinner,tcon-lcd"; + reg = <0x0 0x05502000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_VO0_TCONLCD1>; + clock-names = "clk_bus_tcon"; + resets = <&ccu RST_BUS_VO0_TCONLCD1>; + reset-names = "rst_bus_tcon"; + top = <&vo0>; + status = "disabled"; + // TODO find panel used of_graph? + ports { + #address-cells = <1>; + #size-cells = <0>; + tcon1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + tcon1_in_disp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&disp0_out_tcon1>; + }; + tcon1_in_disp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&disp1_out_tcon1>; + }; + }; + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + tcon1_out_dsi1: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi1_in_tcon1>; + }; + }; + }; + }; + + dlcd2: tcon2@5503000 { + compatible = "allwinner,tcon-lcd"; + reg = <0x0 0x05503000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_VO0_TCONLCD2>, + <&ccu CLK_BUS_VO0_TCONLCD2>; + clock-names = "clk_tcon", + "clk_bus_tcon"; + resets = <&ccu RST_BUS_VO0_TCONLCD2>; + reset-names = "rst_bus_tcon"; + assigned-clocks = <&ccu CLK_VO0_TCONLCD2>; + assigned-clock-parents = <&ccu CLK_PLL_VIDEO2_4X>; + top = <&vo0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + tcon2_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + tcon2_in_disp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&disp0_out_tcon2>; + }; + tcon2_in_disp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&disp1_out_tcon2>; + }; + }; + tcon2_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + tcon2_out_lvds1: endpoint@0 { + reg = <0>; + remote-endpoint = <&lvds1_in_tcon2>; + }; + tcon2_out_rgb1: endpoint@1 { + reg = <1>; + remote-endpoint = <&rgb1_in_tcon2>; + }; + }; + }; + }; + + dsi0combophy: phy@5507000 { + compatible = "allwinner,sunxi-dsi-combo-phy0,sun60iw2"; + reg = <0x0 0x05507000 0x0 0x1ff>; + clocks = <&ccu CLK_BUS_DSI0>; + clock-names = "phy_gating_clk"; + resets = <&ccu RST_BUS_DSI0>; + reset-names = "phy_rst_clk"; + #clock-cells = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + + dsi0: dsi0@5506000 { + compatible = "allwinner,dsi0"; + reg = <0x0 0x05506000 0x0 0xfff>; + interrupts = ; + clocks = <&ccu CLK_DSI0>, + <&ccu CLK_BUS_DSI0>, + <&dsi0combophy CLK_DSI_HS>, + <&dsi0combophy CLK_DSI_LS>; + clock-names = "dsi_clk", + "dsi_gating_clk", + "displl_hs", + "displl_ls"; + resets = <&ccu RST_BUS_DSI0>; + reset-names = "dsi_rst_clk"; + assigned-clocks = <&ccu CLK_DSI0>; + assigned-clock-parents = <&ccu CLK_PLL_PERI0_150M>; + phys = <&dsi0combophy>; + phy-names = "combophy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + dsi0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsi0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_dsi0>; + }; + }; + }; + }; + + dsi1combophy: phy@5509000 { + compatible = "allwinner,sunxi-dsi-combo-phy1,sun60iw2"; + reg = <0x0 0x05509000 0x0 0x1ff>; + clocks = <&ccu CLK_BUS_DSI1>; + clock-names = "phy_gating_clk"; + resets = <&ccu RST_BUS_DSI1>; + reset-names = "phy_rst_clk"; + #clock-cells = <1>; + #phy-cells = <0>; + status = "disabled"; + }; + + dsi1: dsi1@5508000 { + compatible = "allwinner,dsi1"; + reg = <0x0 0x05508000 0x0 0xfff>; + interrupts = ; + clocks = <&ccu CLK_DSI1>, + <&ccu CLK_BUS_DSI1>, + <&dsi1combophy CLK_DSI_HS>, + <&dsi1combophy CLK_DSI_LS>; + clock-names = "dsi_clk", + "dsi_gating_clk", + "displl_hs", + "displl_ls"; + resets = <&ccu RST_BUS_DSI1>; + reset-names = "dsi_rst_clk"; + assigned-clocks = <&ccu CLK_DSI1>; + assigned-clock-parents = <&ccu CLK_PLL_PERI0_150M>; + phys = <&dsi1combophy>; + phy-names = "combophy"; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + dsi1_in_tcon1: endpoint@1 { + reg = <0>; + remote-endpoint = <&tcon1_out_dsi1>; + }; + dsi1_in_tcon0: endpoint@0 { + reg = <1>; + remote-endpoint = <&tcon0_out_dsi1>; + }; + }; + }; + }; + rgb0: rgb0@0001000 { + compatible = "allwinner,rgb0"; + phys = <&dsi0combophy>; + phy-names = "combophy0"; + clocks = <&dsi0combophy CLK_LVDS_OR_RGB>; + clock-names = "rgb_pclk"; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + rgb0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rgb0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_rgb0>; + }; + }; + }; + }; + + lvds0: lvds0@0001000 { + compatible = "allwinner,lvds0"; + clocks = <&dsi0combophy CLK_LVDS_OR_RGB>; + clock-names = "lvds_pclk"; + resets = <&ccu RST_BUS_LVDS0>; + reset-names = "rst_bus_lvds"; + phys = <&dsi0combophy>, <&dsi1combophy>; + phy-names = "combophy0", "combophy1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + lvds0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + lvds0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_lvds0>; + }; + }; + }; + }; + rgb1: rgb1@0001000 { + compatible = "allwinner,rgb1"; + reg = <0>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + rgb1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rgb1_in_tcon2: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon2_out_rgb1>; + }; + }; + }; + }; + + lvds1: lvds1@0001000 { + compatible = "allwinner,lvds1"; + resets = <&ccu RST_BUS_LVDS1>; + reset-names = "rst_bus_lvds"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + lvds1_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + lvds1_in_tcon2: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon2_out_lvds1>; + }; + }; + }; + }; + + tv0: tcon3@5730000 { + compatible = "allwinner,tcon-tv"; + reg = <0x0 0x05730000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_TCONTV0>; + clock-names = "clk_bus_tcon"; + resets = <&ccu RST_BUS_TCONTV0>; + reset-names = "rst_bus_tcon"; + top = <&vo1>; + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + tcon3_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + tcon3_in_disp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&disp0_out_tcon3>; + }; + tcon3_in_disp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&disp1_out_tcon3>; + }; + }; + tcon3_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + tcon3_out_hdmi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi0_in_tcon3>; + }; + }; + }; + }; + + tv1: tcon4@5731000 { + compatible = "allwinner,tcon-tv"; + reg = <0x0 0x05731000 0x0 0x1000>; + interrupts = ; + clocks = <&ccu CLK_EDP_TV>, + <&ccu CLK_TCONTV1>; + clock-names = "clk_tcon", + "clk_bus_tcon"; + resets = <&ccu RST_BUS_TCONTV1>; + reset-names = "rst_bus_tcon"; + top = <&vo1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + tcon4_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + tcon4_in_disp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&disp0_out_tcon4>; + }; + tcon4_in_disp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&disp1_out_tcon4>; + }; + }; + tcon4_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + tcon4_out_edp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp0_in_tcon4>; + }; + }; + }; + }; + + edp0: edp0@5720000 { + #sound-dai-cells = <0>; /* audio driver match method arg */ + compatible = "allwinner,drm-edp"; + reg = <0x0 0x05740000 0x0 0x1000>, /* edp base */ + <0x0 0x05760000 0x0 0x0020>; /* edp pad base */ + interrupts = ; + power-domains = <&pd SUN60IW2_PCK_VO1>; + clocks = <&ccu CLK_EDP_TV>, <&ccu CLK_EDP>; + clock-names = "clk_edp", "clk_bus_edp"; + resets = <&ccu RST_BUS_EDP>; + reset-names = "rst_bus_edp"; + assigned-clocks = <&ccu CLK_EDP_TV>; + assigned-clock-parents = <&ccu CLK_PLL_VIDEO1_4X>; + phys = <&combo0_dp>, <&aux_hpd_phy>; + phy-names = "dp-phy", "aux-phy"; + sys = <&vo1>; + pclk_limit = <200000>; /*KHz*/ + + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + edp0_in_tcon4: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon4_out_edp0>; + }; + }; + edp_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + hdmi0: hdmi0@5520000 { + compatible = "allwinner,sunxi-hdmi"; + reg = <0x0 0x05520000 0x0 0x100000>; + interrupts = ; + clocks = <&ccu CLK_HDMI_REF>, + <&ccu CLK_HDMI>, + <&ccu CLK_HDMI_SFR>, + <&ccu CLK_HDCP_ESM>, + <&rtc_ccu CLK_DCXO>; + clock-names = "clk_cec", + "clk_hdmi", + "clk_hdmi_24M", + "clk_hdcp", + "clk_dcxo"; + resets = <&ccu RST_BUS_HDMI_SUB>, + <&ccu RST_BUS_HDMI_MAIN>, + <&ccu RST_BUS_HDMI_HDCP>; + reset-names = "rst_bus_sub", + "rst_bus_main", + "rst_bus_hdcp"; + assigned-clocks = <&ccu CLK_HDMI>; + assigned-clock-rates = <0>, <0>; + power-domains = <&pd SUN60IW2_PCK_VO1>; + + status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + hdmi0_in_tcon3: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon3_out_hdmi0>; + }; + }; + }; + }; + + ufs: ufs@04520000 { + compatible = "allwinner,sunxi-ufs-v0"; + device_type = "ufs"; + reg = <0x0 0x4520000 0x0 0x1000>; + interrupts = ; + clocks = <&sys24M>, + <&ccu CLK_PLL_PERI0_200M>, + <&ccu CLK_PLL_PERI0_300M>, + <&ccu CLK_UFS_AXI>, + <&ccu CLK_UFS>, + <&ccu CLK_UFS_CFG>, + <&ccu CLK_STORE_AHB_GATE>, + <&ccu CLK_MBUS_STORE_GATE>, + <&ccu CLK_MSI_LITE1>, + <&rtc_ccu CLK_RTC_DCXO_WAKEUP>; + clock-names = "osc24m","pll_periph","pll_periph_2", + "axi_clk_gate","ahb_gate", "cfg_clk_gate", + "store_ahb","store_mbus","msi_lite","dcxo_wakeup"; + resets = <&ccu RST_BUS_UFS_CORE>, + <&ccu RST_BUS_UFS_PHY>, + <&ccu RST_BUS_UFS_AXI>, + <&ccu RST_BUS_UFS_AHB>; + reset-names = "controller_rst", "phy_rst", "axi_rst", "ahb_rst"; + status = "disabled"; + }; + + sdc2: sdmmc@4022000 { + compatible = "allwinner,sunxi-mmc-v4p6x"; + device_type = "sdc2"; + reg = <0x0 0x04022000 0x0 0x1000>; + interrupts = ; + clocks = <&sys24M>, + <&ccu CLK_PLL_PERI1_800M>, + <&ccu CLK_PLL_PERI1_600M>, + <&ccu CLK_SMHC2>, + <&ccu CLK_BUS_SMHC2>, + <&ccu CLK_STORE_AHB_GATE>, + <&ccu CLK_MBUS_STORE_GATE>, + <&ccu CLK_MSI_LITE1>; + clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb","mmc_store","mmc_mbus","mmc_msi_lite"; + resets = <&ccu RST_BUS_SMHC2>; + reset-names = "rst"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&sdc2_pins_a &sdc2_pins_c &sdc2_pins_d>; + pinctrl-1 = <&sdc2_pins_b>; + bus-width = <8>; + req-page-count = <2>; + cap-mmc-highspeed; + cap-cmd23; + mmc-cache-ctrl; + non-removable; + /*max-frequency = <200000000>;*/ + max-frequency = <50000000>; + cap-erase; + mmc-high-capacity-erase-size; + no-sdio; + no-sd; + /*-- speed mode --*/ + /*sm0: DS26_SDR12*/ + /*sm1: HSSDR52_SDR25*/ + /*sm2: HSDDR52_DDR50*/ + /*sm3: HS200_SDR104*/ + /*sm4: HS400*/ + /*-- frequency point --*/ + /*f0: CLK_400K*/ + /*f1: CLK_25M*/ + /*f2: CLK_50M*/ + /*f3: CLK_100M*/ + /*f4: CLK_150M*/ + /*f5: CLK_200M*/ + ctl-spec-caps = <0x328>; + sdc_tm4_sm0_freq0 = <0>; + sdc_tm4_sm0_freq1 = <0>; + sdc_tm4_sm1_freq0 = <0x00000000>; + sdc_tm4_sm1_freq1 = <0>; + sdc_tm4_sm2_freq0 = <0x00000000>; + sdc_tm4_sm2_freq1 = <0>; + sdc_tm4_sm3_freq0 = <0x05000000>; + sdc_tm4_sm3_freq1 = <0x00000005>; + sdc_tm4_sm4_freq0 = <0x00050000>; + sdc_tm4_sm4_freq1 = <0x00000004>; + sdc_tm4_sm4_freq0_cmd = <0>; + sdc_tm4_sm4_freq1_cmd = <0>; + + /*vmmc-supply = <®_3p3v>;*/ + /*vqmc-supply = <®_3p3v>;*/ + /*vdmc-supply = <®_3p3v>;*/ + /*vmmc = "vcc-card";*/ + /*vqmc = "";*/ + /*vdmc = "";*/ + /*sunxi-power-save-mode;*/ + status = "okay"; + }; + + sdc3: sdmmc@4023000 { + compatible = "allwinner,sunxi-mmc-v5p6x"; + device_type = "sdc3"; + reg = <0x0 0x04023000 0x0 0x1000>; + interrupts = ; + clocks = <&sys24M>, + <&ccu CLK_PLL_PERI1_800M>, + <&ccu CLK_PLL_PERI1_600M>, + <&ccu CLK_SMHC3>, + <&ccu CLK_BUS_SMHC3>, + <&ccu CLK_MBUS_STORE_GATE>, + <&ccu CLK_MSI_LITE1>; + clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb","mmc_mbus","mmc_msi_lite"; + resets = <&ccu RST_BUS_SMHC3>; + reset-names = "rst"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&sdc3_pins_a &sdc3_pins_c &sdc3_pins_d>; + pinctrl-1 = <&sdc3_pins_b>; + bus-width = <8>; + req-page-count = <2>; + cap-mmc-highspeed; + cap-cmd23; + mmc-cache-ctrl; + non-removable; + /*max-frequency = <200000000>;*/ + max-frequency = <50000000>; + cap-erase; + mmc-high-capacity-erase-size; + no-sdio; + no-sd; + /*-- speed mode --*/ + /*sm0: DS26_SDR12*/ + /*sm1: HSSDR52_SDR25*/ + /*sm2: HSDDR52_DDR50*/ + /*sm3: HS200_SDR104*/ + /*sm4: HS400*/ + /*-- frequency point --*/ + /*f0: CLK_400K*/ + /*f1: CLK_25M*/ + /*f2: CLK_50M*/ + /*f3: CLK_100M*/ + /*f4: CLK_150M*/ + /*f5: CLK_200M*/ + ctl-spec-caps = <0x328>; + sdc_tm4_sm0_freq0 = <0>; + sdc_tm4_sm0_freq1 = <0>; + sdc_tm4_sm1_freq0 = <0x00000000>; + sdc_tm4_sm1_freq1 = <0>; + sdc_tm4_sm2_freq0 = <0x00000000>; + sdc_tm4_sm2_freq1 = <0>; + sdc_tm4_sm3_freq0 = <0x05000000>; + sdc_tm4_sm3_freq1 = <0x00000005>; + sdc_tm4_sm4_freq0 = <0x00050000>; + sdc_tm4_sm4_freq1 = <0x00000004>; + sdc_tm4_sm4_freq0_cmd = <0>; + sdc_tm4_sm4_freq1_cmd = <0>; + + /*vmmc-supply = <®_3p3v>;*/ + /*vqmc-supply = <®_3p3v>;*/ + /*vdmc-supply = <®_3p3v>;*/ + /*vmmc = "vcc-card";*/ + /*vqmc = "";*/ + /*vdmc = "";*/ + /*sunxi-power-save-mode;*/ + status = "disabled"; + }; + + sdc0: sdmmc@4020000 { + compatible = "allwinner,sunxi-mmc-v5p3x"; + device_type = "sdc0"; + reg = <0x0 0x04020000 0x0 0x1000>; + interrupts = ; + clocks = <&sys24M>, + <&ccu CLK_PLL_PERI1_400M>, + <&ccu CLK_PLL_PERI1_300M>, + <&ccu CLK_SMHC0>, + <&ccu CLK_BUS_SMHC0>, + <&ccu CLK_STORE_AHB_GATE>, + <&ccu CLK_MBUS_STORE_GATE>, + <&ccu CLK_MSI_LITE1>; + clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb","mmc_store","mmc_mbus","mmc_msi_lite"; + resets = <&ccu RST_BUS_SMHC0>; + reset-names = "rst"; + pinctrl-names = "default","mmc_1v8","sleep","uart_jtag"; + pinctrl-0 = <&sdc0_pins_a &sdc0_pins_f>; + pinctrl-1 = <&sdc0_pins_b &sdc0_pins_g>; + pinctrl-2 = <&sdc0_pins_c>; + pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>; + max-frequency = <50000000>; + bus-width = <4>; + req-page-count = <2>; + /*non-removable;*/ + /*broken-cd;*/ + /*cd-inverted*/ + /*cd-gpios = <&pio PF 6 GPIO_ACTIVE_LOW>;*/ + /* vmmc-supply = <®_3p3v>;*/ + /* vqmc-supply = <®_3p3v>;*/ + /* vdmc-supply = <®_3p3v>;*/ + /*vmmc = "vcc-card";*/ + /*vqmc = "";*/ + /*vdmc = "";*/ + cap-sd-highspeed; + cap-wait-while-busy; + /*sd-uhs-sdr50;*/ + /*sd-uhs-ddr50;*/ + /*cap-sdio-irq;*/ + /*keep-power-in-suspend;*/ + /*ignore-pm-notify;*/ + /*sunxi-power-save-mode;*/ + /*sunxi-dly-400k = <1 0 0 0>; */ + /*sunxi-dly-26M = <1 0 0 0>;*/ + /*sunxi-dly-52M = <1 0 0 0>;*/ + /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/ + /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/ + /*sunxi-dly-104M = <1 0 0 0>;*/ + /*sunxi-dly-208M = <1 0 0 0>;*/ + /*sunxi-dly-104M-ddr = <1 0 0 0>;*/ + /*sunxi-dly-208M-ddr = <1 0 0 0>;*/ + ctl-spec-caps = <0x428>; + status = "okay"; + }; + + sdc1: sdmmc@4021000 { + compatible = "allwinner,sunxi-mmc-v5p3x"; + device_type = "sdc1"; + reg = <0x0 0x04021000 0x0 0x1000>; + interrupts = ; + clocks = <&sys24M>, + <&ccu CLK_PLL_PERI1_400M>, + <&ccu CLK_PLL_PERI1_300M>, + <&ccu CLK_SMHC1>, + <&ccu CLK_BUS_SMHC1>, + <&ccu CLK_STORE_AHB_GATE>, + <&ccu CLK_MBUS_STORE_GATE>, + <&ccu CLK_MSI_LITE1>; + clock-names = "osc24m","pll_periph","pll_periph_2","mmc","ahb","mmc_store","mmc_mbus","mmc_msi_lite"; + resets = <&ccu RST_BUS_SMHC1>; + reset-names = "rst"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&sdc1_pins_a &sdc1_pins_c>; + pinctrl-1 = <&sdc1_pins_b>; + max-frequency = <50000000>; + bus-width = <4>; + /*broken-cd;*/ + /*cd-inverted*/ + /*cd-gpios = <&pio PG 6 6 1 2 0>;*/ + /* vmmc-supply = <®_3p3v>;*/ + /* vqmc-supply = <®_3p3v>;*/ + /* vdmc-supply = <®_3p3v>;*/ + /*vmmc = "vcc-card";*/ + /*vqmc = "";*/ + /*vdmc = "";*/ + cap-sd-highspeed; + cap-sdio-irq; + ignore-pm-notify; + /*sd-uhs-sdr50;*/ + /*sd-uhs-ddr50;*/ + /*sd-uhs-sdr104;*/ + /*cap-sdio-irq;*/ + keep-power-in-suspend; + /*ignore-pm-notify;*/ + /*sunxi-power-save-mode;*/ + /*sunxi-dly-400k = <0xff 0xff 0xff 0xff 0xff 0xff>; */ + /*sunxi-dly-26M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/ + /*sunxi-dly-52M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/ + /*sunxi-dly-52M-ddr4 = <0xff 0xff 0xff 0xff 0xff 0xff>;*/ + /*sunxi-dly-52M-ddr8 = <0xff 0xff 0xff 0xff 0xff 0xff>;*/ + /*sunxi-dly-104M = <0xff 0xff 0xff 0xff 0xff 0xff>;*/ + /*sunxi-dly-208M = <0xff 0xff 0xff 0xff 0xff 0xff> ;*/ + /*sunxi-dly-104M-ddr = <0xff 0xff 0xff 0xff 0xff 0xff>;*/ + /*sunxi-dly-208M-ddr = <0xff 0xff 0xff 0xff 0xff 0xff>;*/ + sunxi-dly-208M = <0xff 0x1 0xff 0xff 0xff 0xff>; + execute_tuning_in_kernel; + ctl-spec-caps = <0x428>; + status = "okay"; + }; + + gpu: gpu@1800000 { + device_type = "gpu"; + compatible = "img,gpu"; + reg = <0x0 0x01800000 0x0 0x8ffff>; + interrupts = , + ; + interrupt-names = "IRQGPU", "IRQGPUDVFS"; + clocks = <&ccu CLK_PLL_GPU0>, + <&ccu CLK_GPU0>, + <&ccu CLK_BUS_GPU0>, + <&ccu CLK_PLL_PERI0_800M>, + <&ccu CLK_PLL_PERI0_600M>, + <&ccu CLK_PLL_PERI0_400M>, + <&ccu CLK_PLL_PERI0_300M>, + <&ccu CLK_PLL_PERI0_200M>; + clock-names = "clk_parent", "clk", "clk_bus", + "clk_800", "clk_600", "clk_400", + "clk_300", "clk_200"; + resets = <&ccu RST_BUS_GPU0>; + reset-names = "reset_bus"; + /*power-domains = <&pd SUN60IW2_PCK_GPU_TOP>;*/ + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "allwinner, img-operating-points"; + + /*opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <800000>; + opp-microvolt-vfdefault = <800000>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0201 = <800000>; + opp-microvolt-vf0202 = <800000>; + opp-microvolt-vf0302 = <800000>; + opp-microvolt-vf0402 = <800000>; + opp-microvolt-vf0502 = <800000>; + opp-microvolt-vf0602 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf1400 = <800000>; + opp-microvolt-vf1500 = <800000>; + };*/ + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <800000>; + opp-microvolt-vfdefault = <800000>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0101 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0201 = <800000>; + opp-microvolt-vf0202 = <800000>; + opp-microvolt-vf0302 = <800000>; + opp-microvolt-vf0402 = <800000>; + opp-microvolt-vf0502 = <800000>; + opp-microvolt-vf0602 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf1400 = <800000>; + opp-microvolt-vf1500 = <800000>; + }; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + opp-microvolt-vfdefault = <800000>; + opp-microvolt-vf0000 = <800000>; + opp-microvolt-vf0100 = <800000>; + opp-microvolt-vf0101 = <800000>; + opp-microvolt-vf0200 = <800000>; + opp-microvolt-vf0201 = <800000>; + opp-microvolt-vf0202 = <800000>; + opp-microvolt-vf0302 = <800000>; + opp-microvolt-vf0402 = <800000>; + opp-microvolt-vf0502 = <800000>; + opp-microvolt-vf0602 = <800000>; + opp-microvolt-vf0300 = <800000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0800 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf1400 = <800000>; + opp-microvolt-vf1500 = <800000>; + }; + + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <840000>; + opp-microvolt-vfdefault = <840000>; + opp-microvolt-vf0000 = <840000>; + opp-microvolt-vf0100 = <840000>; + opp-microvolt-vf0101 = <800000>; + opp-microvolt-vf0200 = <840000>; + opp-microvolt-vf0201 = <800000>; + opp-microvolt-vf0202 = <800000>; + opp-microvolt-vf0302 = <800000>; + opp-microvolt-vf0402 = <800000>; + opp-microvolt-vf0502 = <800000>; + opp-microvolt-vf0602 = <800000>; + opp-microvolt-vf0300 = <820000>; + opp-microvolt-vf0400 = <800000>; + opp-microvolt-vf0500 = <800000>; + opp-microvolt-vf0600 = <800000>; + opp-microvolt-vf0700 = <800000>; + opp-microvolt-vf0800 = <820000>; + opp-microvolt-vf1400 = <800000>; + opp-microvolt-vf1500 = <800000>; + }; + + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <960000>; + opp-microvolt-vfdefault = <960000>; + opp-microvolt-vf0000 = <960000>; + opp-microvolt-vf0100 = <960000>; + opp-microvolt-vf0101 = <920000>; + opp-microvolt-vf0200 = <960000>; + opp-microvolt-vf0201 = <880000>; + opp-microvolt-vf0202 = <920000>; + opp-microvolt-vf0302 = <920000>; + opp-microvolt-vf0402 = <900000>; + opp-microvolt-vf0502 = <880000>; + opp-microvolt-vf0602 = <860000>; + opp-microvolt-vf0300 = <940000>; + opp-microvolt-vf0400 = <900000>; + opp-microvolt-vf0500 = <880000>; + opp-microvolt-vf0600 = <920000>; + opp-microvolt-vf0700 = <880000>; + opp-microvolt-vf0800 = <940000>; + opp-microvolt-vf1400 = <880000>; + opp-microvolt-vf1500 = <860000>; + }; + }; + + hdmi_codec: hdmi_codec { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-snd-codec-hdmi"; + status = "disabled"; + }; + + /* audio dirver module -> I2S/PCM */ + i2s0_plat:i2s0_plat@2532000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-snd-plat-i2s"; + reg = <0x0 0x02532000 0x0 0xA0>; + resets = <&ccu RST_BUS_I2SPCM0>; + clocks = <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_AUDIO1_DIV2>, + <&ccu CLK_PLL_AUDIO1_DIV5>, + <&ccu CLK_PLL_PERI0_200M>, + <&ccu CLK_BUS_I2SPCM0>, + <&ccu CLK_I2SPCM0>; + clock-names = "clk_pll_audio0_4x", + "clk_pll_audio1_div2", + "clk_pll_audio1_div5", + "clk_i2s_asrc", + "clk_bus_i2s", + "clk_i2s"; + dmas = <&dma 3>, <&dma 3>; + dma-names = "tx", "rx"; + playback-cma = <128>; + capture-cma = <128>; + tx-fifo-size = <128>; + rx-fifo-size = <128>; + status = "disabled"; + }; + + i2s0_mach:i2s0_mach{ + compatible = "allwinner,sunxi-snd-mach"; + soundcard-mach,name = "sndi2s0"; + soundcard-mach,format = "i2s"; + soundcard-mach,slot-num = <2>; + soundcard-mach,slot-width = <32>; + status = "disabled"; + soundcard-mach,cpu { + sound-dai = <&i2s0_plat>; + }; + soundcard-mach,codec { + }; + }; + + i2s1_plat:i2s1_plat@2533000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-snd-plat-i2s"; + reg = <0x0 0x02533000 0x0 0xA0>; + resets = <&ccu RST_BUS_I2SPCM1>; + clocks = <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_AUDIO1_DIV2>, + <&ccu CLK_PLL_AUDIO1_DIV5>, + <&ccu CLK_PLL_PERI0_200M>, + <&ccu CLK_BUS_I2SPCM1>, + <&ccu CLK_I2SPCM1>; + clock-names = "clk_pll_audio0_4x", + "clk_pll_audio1_div2", + "clk_pll_audio1_div5", + "clk_i2s_asrc", + "clk_bus_i2s", + "clk_i2s"; + dmas = <&dma 4>, <&dma 4>; + dma-names = "tx", "rx"; + playback-cma = <128>; + capture-cma = <128>; + tx-fifo-size = <128>; + rx-fifo-size = <128>; + status = "disabled"; + }; + + i2s1_mach:i2s1_mach{ + compatible = "allwinner,sunxi-snd-mach"; + soundcard-mach,name = "sndi2s1"; + soundcard-mach,format = "i2s"; + soundcard-mach,slot-num = <2>; + soundcard-mach,slot-width = <32>; + status = "disabled"; + soundcard-mach,cpu { + sound-dai = <&i2s1_plat>; + }; + soundcard-mach,codec { + }; + }; + + i2s2_plat:i2s2_plat@2534000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-snd-plat-i2s"; + reg = <0x0 0x02534000 0x0 0xA0>; + resets = <&ccu RST_BUS_I2SPCM2>; + clocks = <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_AUDIO1_DIV2>, + <&ccu CLK_PLL_AUDIO1_DIV5>, + <&ccu CLK_PLL_PERI0_200M>, + <&ccu CLK_BUS_I2SPCM2>, + <&ccu CLK_I2SPCM2>; + clock-names = "clk_pll_audio0_4x", + "clk_pll_audio1_div2", + "clk_pll_audio1_div5", + "clk_i2s_asrc", + "clk_bus_i2s", + "clk_i2s"; + dmas = <&dma 5>, <&dma 5>; + dma-names = "tx", "rx"; + playback-cma = <128>; + capture-cma = <128>; + tx-fifo-size = <128>; + rx-fifo-size = <128>; + status = "disabled"; + }; + + i2s2_mach:i2s2_mach{ + compatible = "allwinner,sunxi-snd-mach"; + soundcard-mach,name = "sndi2s2"; + soundcard-mach,format = "i2s"; + soundcard-mach,slot-num = <2>; + soundcard-mach,slot-width = <32>; + status = "disabled"; + soundcard-mach,cpu { + sound-dai = <&i2s2_plat>; + }; + soundcard-mach,codec { + }; + }; + + i2s3_plat:i2s3_plat@2535000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-snd-plat-i2s"; + reg = <0x0 0x02535000 0x0 0xA0>; + resets = <&ccu RST_BUS_I2SPCM3>; + clocks = <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_AUDIO1_DIV2>, + <&ccu CLK_PLL_AUDIO1_DIV5>, + <&ccu CLK_PLL_PERI0_200M>, + <&ccu CLK_BUS_I2SPCM3>, + <&ccu CLK_I2SPCM3>; + clock-names = "clk_pll_audio0_4x", + "clk_pll_audio1_div2", + "clk_pll_audio1_div5", + "clk_i2s_asrc", + "clk_bus_i2s", + "clk_i2s"; + dmas = <&dma 6>, <&dma 6>; + dma-names = "tx", "rx"; + playback-cma = <128>; + capture-cma = <128>; + tx-fifo-size = <128>; + rx-fifo-size = <128>; + status = "disabled"; + }; + + i2s3_mach:i2s3_mach{ + compatible = "allwinner,sunxi-snd-mach"; + /* card name. hdmi: "sndhdmi"; edp: "sndedp" */ + soundcard-mach,name = "sndhdmi"; + soundcard-mach,format = "i2s"; + soundcard-mach,slot-num = <2>; + soundcard-mach,slot-width = <32>; + status = "disabled"; + soundcard-mach,cpu { + sound-dai = <&i2s3_plat>; + }; + soundcard-mach,codec { + }; + }; + + i2s4_plat:i2s4_plat@2536000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-snd-plat-i2s"; + reg = <0x0 0x02536000 0x0 0xA0>; + resets = <&ccu RST_BUS_I2SPCM4>; + clocks = <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_AUDIO1_DIV2>, + <&ccu CLK_PLL_AUDIO1_DIV5>, + <&ccu CLK_PLL_PERI0_200M>, + <&ccu CLK_BUS_I2SPCM4>, + <&ccu CLK_I2SPCM4>; + clock-names = "clk_pll_audio0_4x", + "clk_pll_audio1_div2", + "clk_pll_audio1_div5", + "clk_i2s_asrc", + "clk_bus_i2s", + "clk_i2s"; + dmas = <&dma 7>, <&dma 7>; + dma-names = "tx", "rx"; + playback-cma = <128>; + capture-cma = <128>; + tx-fifo-size = <128>; + rx-fifo-size = <128>; + status = "disabled"; + }; + + i2s4_mach:i2s4_mach{ + compatible = "allwinner,sunxi-snd-mach"; + soundcard-mach,name = "sndi2s4"; + soundcard-mach,format = "i2s"; + soundcard-mach,slot-num = <2>; + soundcard-mach,slot-width = <32>; + status = "disabled"; + soundcard-mach,cpu { + sound-dai = <&i2s4_plat>; + }; + soundcard-mach,codec { + }; + }; + + /* audio dirver module -> owa */ + owa_plat:owa_plat@2537000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-snd-plat-owa"; + reg = <0x0 0x02537000 0x0 0x58>; + interrupts = ; + resets = <&ccu RST_BUS_OWA>; + clocks = <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_AUDIO1_DIV2>, + <&ccu CLK_PLL_AUDIO1_DIV5>, + <&ccu CLK_BUS_OWA>, + <&ccu CLK_OWA_TX>, + <&ccu CLK_OWA_RX>; + clock-names = "clk_pll_audio0_4x", + "clk_pll_audio1_div2", + "clk_pll_audio1_div5", + "clk_bus_owa", + "clk_owa_tx", + "clk_owa_rx"; + dmas = <&dma 2>, <&dma 2>; + dma-names = "tx", "rx"; + playback-cma = <128>; + capture-cma = <128>; + tx-fifo-size = <128>; + rx-fifo-size = <128>; + status = "disabled"; + }; + + owa_mach:owa_mach { + compatible = "allwinner,sunxi-snd-mach"; + soundcard-mach,name = "sndowa"; + status = "disabled"; + soundcard-mach,cpu { + sound-dai = <&owa_plat>; + }; + soundcard-mach,codec { + }; + }; + + /* audio dirver module -> dmic */ + dmic_plat:dmic_plat@2531000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sunxi-snd-plat-dmic"; + reg = <0x0 0x02531000 0x0 0x50>; + resets = <&ccu RST_BUS_DMIC>; + clocks = <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_AUDIO1_DIV2>, + <&ccu CLK_PLL_AUDIO1_DIV5>, + <&ccu CLK_BUS_DMIC>, + <&ccu CLK_DMIC>; + clock-names = "clk_pll_audio0_4x", + "clk_pll_audio1_div2", + "clk_pll_audio1_div5", + "clk_bus_dmic", + "clk_dmic"; + dmas = <&dma 9>; + dma-names = "rx"; + capture-cma = <128>; + rx-fifo-size = <128>; + status = "disabled"; + }; + + dmic_mach:dmic_mach{ + compatible = "allwinner,sunxi-snd-mach"; + soundcard-mach,name = "snddmic"; + soundcard-mach,capture-only; + status = "disabled"; + soundcard-mach,cpu { + sound-dai = <&dmic_plat>; + }; + soundcard-mach,codec { + }; + }; + + pcie_rc: pcie@6000000 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "allwinner,sunxi-pcie-v300-rc"; + bus-range = <0x0 0xff>; + reg = <0 0x06000000 0 0x480000>; + reg-names = "dbi"; + device_type = "pci"; + ranges = <0x00000800 0 0x20000000 0x0 0x20000000 0 0x01000000 + 0x81000000 0 0x21000000 0x0 0x21000000 0 0x01000000 + 0x82000000 0 0x22000000 0x0 0x22000000 0 0x06000000>; + num-lanes = <1>; + phys = <&combo1_pcie>; + phy-names = "pcie-phy"; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "sii", "msi", "edma-w0", "edma-w1", "edma-w2", "edma-w3", + "edma-r0", "edma-r1", "edma-r2", "edma-r3"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + num-edma = <4>; + max-link-speed = <3>; + num-ib-windows = <16>; + num-ob-windows = <16>; + linux,pci-domain = <0>; + power-domains = <&pd SUN60IW2_PCK_PCIE>; + clocks = <&ccu CLK_PCIE0_AUX>, <&ccu CLK_PCIE0_AXI_SLV>, <&ccu CLK_ITS_PCIE0_A>; + clock-names = "pclk_aux", "pclk_slv", "its"; + resets = <&ccu RST_BUS_PCIE0>, <&ccu RST_BUS_PCIE0_PWRUP>, <&ccu RST_BUS_ITS_PCIE0>; + reset-names = "pclk_rst", "pwrup_rst", "its"; + busno = <0>; + status = "disabled"; + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; +}; diff --git a/arch/arm64/configs/sun60iw2p1_bsp_defconfig b/arch/arm64/configs/sun60iw2p1_bsp_defconfig new file mode 100644 index 000000000..ec3e09913 --- /dev/null +++ b/arch/arm64/configs/sun60iw2p1_bsp_defconfig @@ -0,0 +1,289 @@ +CONFIG_AW_BSP=y +CONFIG_AW_KERNEL_ORIGIN=y +CONFIG_ARCH_SUN60I=y +CONFIG_ARCH_SUN60IW2=y +CONFIG_AW_IC_BOARD=y +CONFIG_AW_SOC_NAME="A733" +# CONFIG_AW_UART is not set +CONFIG_AW_UART_NG=y +CONFIG_AW_SERIAL_CONSOLE=y +CONFIG_AW_TIMER_SUN50I=y +CONFIG_AW_DMA=y +CONFIG_AW_RTC=y +CONFIG_AW_RTC_REBOOT_FLAG=y +CONFIG_AW_RTC_POWEROFF_ALARM=y +CONFIG_AW_NSI=y +CONFIG_AW_WATCHDOG=y +CONFIG_AW_IOMMU=y +CONFIG_AW_IOMMU_V2=y +CONFIG_AW_MMC=y +CONFIG_AW_UFS=y +# CONFIG_AW_DISP2 is not set +CONFIG_AW_G2D=m +CONFIG_G2D_RCQ=y +# CONFIG_AW_DI is not set +CONFIG_AW_VIDEO_SUNXI_VIN=m +CONFIG_ACTUATOR=m +CONFIG_ACTUATOR_CN3927=m +CONFIG_SUPPORT_ISP_TDM=y +CONFIG_SENSOR_GC030A=m +CONFIG_SENSOR_GC05A2=m +CONFIG_SENSOR_OV13850=m +CONFIG_AW_DRM=y +CONFIG_AW_DRM_LVDS=y +CONFIG_AW_DRM_DSI=y +CONFIG_PANEL_DSI_GENERAL=y +CONFIG_PANEL_LVDS_GENERAL=y +CONFIG_AW_DRM_PHY=y +CONFIG_AW_DRM_DSI_COMBOPHY=y +CONFIG_AW_VIDEO_ENCODER_DECODER=m +CONFIG_AW_VIDEO_KERNEL_ENC=y +CONFIG_AW_VIDEO_KERNEL_DEC=y +# CONFIG_AW_VIDEO_DYNAMIC_DEBUG is not set +CONFIG_SND_SOC_AC101=y +CONFIG_SND_SOC_AC107=y +CONFIG_SND_SOC_SUNXI_OWA=y +CONFIG_SND_SOC_SUNXI_I2S=y +CONFIG_SND_SOC_SUNXI_CODEC_HDMI=y +CONFIG_SND_SOC_SUNXI_COMPONENTS=y +CONFIG_SND_SOC_SUNXI_DEBUG=y +CONFIG_SND_SOC_SUNXI_PULSEAUDIO=y +CONFIG_SND_SOC_AW87XXX=y +CONFIG_AW_SYS_INFO=y +CONFIG_AW_SMC=y +CONFIG_AW_SID=y +CONFIG_AW_DRM_HEAP=y +CONFIG_AW_CADENCE_COMBOPHY=y +CONFIG_USB_SUNXI_DWC3=y +CONFIG_PHY_SUNXI_PLAT=y +CONFIG_USB_EHCI_HCD_SUNXI=y +CONFIG_USB_OHCI_HCD_SUNXI=y +CONFIG_USB_SUNXI_HCD=y +CONFIG_USB_SUNXI_HCI=y +CONFIG_USB_SUNXI_EHCI0=y +CONFIG_USB_SUNXI_EHCI1=y +CONFIG_USB_SUNXI_OHCI0=y +CONFIG_USB_SUNXI_OHCI1=y +CONFIG_USB_SUNXI_USB=y +CONFIG_USB_SUNXI_USB_MANAGER=y +CONFIG_USB_SUNXI_USB_DEBUG=y +CONFIG_USB_SUNXI_USB_ADB=y +CONFIG_USB_SUNXI_UDC0=y +CONFIG_AW_TWI=y +CONFIG_AW_LEDC=y +CONFIG_AW_PWM=y +# CONFIG_AW_INPUT_SENSORINIT is not set +CONFIG_AW_STMMAC_ETH=m +CONFIG_REALTEK_PHY=y +CONFIG_RTL8852BS=m +CONFIG_RTL_BT_LPM=m +# CONFIG_AIC_WLAN_SUPPORT is not set +CONFIG_AW_WAKEUPGEN=y +CONFIG_AW_SUN8I_NMI=y +CONFIG_AW_THERMAL=y +CONFIG_NVMEM_AW_SID=y +CONFIG_NVMEM_SYSFS=y +CONFIG_EEPROM_AT24=m +CONFIG_AW_PCK600_DOMAINS=y +CONFIG_AW_POWER_DOMAIN_TEST=y +CONFIG_AW_MFD_AXP2101_I2C=y +CONFIG_AW_REGULATOR_AXP2101=y +CONFIG_AW_INPUT_AXP2101_PEK=y +CONFIG_AW_AXP515_POWER=y +CONFIG_AW_AXP8191_TEMP_CTRL=y +CONFIG_AW_TYPEC_CC_LOGIC=y +CONFIG_AW_CPUFREQ_DT=y +CONFIG_ARM_AW_SUN50I_CPUFREQ_NVMEM=y +CONFIG_AW_DMC_DEVFREQ=m +CONFIG_AW_EVENT_DDR=y +CONFIG_AW_NNA_VIP=m +CONFIG_NNA_VIP2=y +CONFIG_AW_RFKILL=y +CONFIG_AW_MACADDR_MGT=y +CONFIG_AW_GPU_TYPE="bxm" +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_EXPERT=y +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_FHANDLE is not set +CONFIG_KALLSYMS_ALL=y +# CONFIG_RSEQ is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_PROFILING=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=8 +CONFIG_COMPAT=y +# CONFIG_EFI is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +# CONFIG_SUSPEND is not set +# CONFIG_HIBERNATION is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_BLK_DEV is not set +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_BSG=y +CONFIG_NETDEVICES=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO_SERPORT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_PTP_1588_CLOCK is not set +# CONFIG_PINCTRL_SUN8I_H3_R is not set +# CONFIG_PINCTRL_SUN50I_A64 is not set +# CONFIG_PINCTRL_SUN50I_A64_R is not set +# CONFIG_PINCTRL_SUN50I_A100 is not set +# CONFIG_PINCTRL_SUN50I_A100_R is not set +# CONFIG_PINCTRL_SUN50I_H5 is not set +# CONFIG_PINCTRL_SUN50I_H6 is not set +# CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_SUN50I_H616 is not set +# CONFIG_PINCTRL_SUN50I_H616_R is not set +CONFIG_HWMON=y +CONFIG_SENSORS_PWM_FAN=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_IDLE_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_DRM=y +CONFIG_FB=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_STORAGE_ENE_UB6250=y +CONFIG_USB_UAS=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_HOST=y +# CONFIG_USB_DWC3_GADGET is not set +# CONFIG_USB_DWC3_DUAL_ROLE is not set +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_TYPEC=y +CONFIG_USB_ROLE_SWITCH=y +CONFIG_MMC=y +# CONFIG_PWRSEQ_EMMC is not set +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_MMC_CQHCI=y +CONFIG_MMC_HSQ=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_SYSFS_STATS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +# CONFIG_SUNXI_CCU is not set +# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set +# CONFIG_FSL_ERRATUM_A008585 is not set +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +CONFIG_EXT4_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_XZ_DEC=y +CONFIG_DMA_CMA=y +CONFIG_PRINTK_TIME=y +CONFIG_PRINTK_CALLER=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_DYNAMIC_DEBUG_CORE=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_MISC is not set +CONFIG_PANIC_ON_OOPS=y +# CONFIG_FTRACE is not set +# CONFIG_STRICT_DEVMEM is not set diff --git a/include/dt-bindings/clock/sun60iw2-ccu.h b/include/dt-bindings/clock/sun60iw2-ccu.h new file mode 100644 index 000000000..54689b563 --- /dev/null +++ b/include/dt-bindings/clock/sun60iw2-ccu.h @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */ +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + */ + +#ifndef _DT_BINDINGS_CLK_SUN60IW2_H_ +#define _DT_BINDINGS_CLK_SUN60IW2_H_ + +#define CLK_PLL_REF 0 +#define CLK_PLL_DDR 1 +#define CLK_PLL_PERI0 2 +#define CLK_PLL_PERI0_2X 3 +#define CLK_PLL_PERI0_800M 4 +#define CLK_PLL_PERI0_480M 5 +#define CLK_PLL_PERI0_600M 6 +#define CLK_PLL_PERI0_400M 7 +#define CLK_PLL_PERI0_300M 8 +#define CLK_PLL_PERI0_200M 9 +#define CLK_PLL_PERI0_160M 10 +#define CLK_PLL_PERI0_150M 11 +#define CLK_PLL_PERI1 12 +#define CLK_PLL_PERI1_2X 13 +#define CLK_PLL_PERI1_800M 14 +#define CLK_PLL_PERI1_480M 15 +#define CLK_PLL_PERI1_600M 16 +#define CLK_PLL_PERI1_400M 17 +#define CLK_PLL_PERI1_300M 18 +#define CLK_PLL_PERI1_200M 19 +#define CLK_PLL_PERI1_160M 20 +#define CLK_PLL_PERI1_150M 21 +#define CLK_HDMI_CEC_32K 22 +#define CLK_PLL_GPU0 23 +#define CLK_PLL_VIDEO0 24 +#define CLK_PLL_VIDEO0_4X 25 +#define CLK_PLL_VIDEO0_3X 26 +#define CLK_PLL_VIDEO1 27 +#define CLK_PLL_VIDEO1_4X 28 +#define CLK_PLL_VIDEO1_3X 29 +#define CLK_PLL_VIDEO2 30 +#define CLK_PLL_VIDEO2_4X 31 +#define CLK_PLL_VIDEO2_3X 32 +#define CLK_PLL_VE0 33 +#define CLK_PLL_VE1 34 +#define CLK_PLL_AUDIO0_4X 35 +#define CLK_PLL_AUDIO1 36 +#define CLK_PLL_AUDIO1_DIV2 37 +#define CLK_PLL_AUDIO1_DIV5 38 +#define CLK_PLL_NPU 39 +#define CLK_PLL_DE 40 +#define CLK_PLL_DE_4X 41 +#define CLK_PLL_DE_3X 42 +#define CLK_AHB 43 +#define CLK_APB0 44 +#define CLK_APB1 45 +#define CLK_APB_UART 46 +#define CLK_TRACE 47 +#define CLK_GIC 48 +#define CLK_CPU_PERI 49 +#define CLK_ITS_PCIE0_A 50 +#define CLK_NSI 51 +#define CLK_NSI_CFG 52 +#define CLK_MBUS 53 +#define CLK_IOMMU0_SYS_H 54 +#define CLK_IOMMU0_SYS_P 55 +#define CLK_IOMMU0_SYS_MBUS 56 +#define CLK_MSI_LITE0 57 +#define CLK_MSI_LITE1 58 +#define CLK_MSI_LITE2 59 +#define CLK_IOMMU1_SYS_H 60 +#define CLK_IOMMU1_SYS_P 61 +#define CLK_IOMMU1_SYS_MBUS 62 +#define CLK_CPUS_HCLK_GATE 63 +#define CLK_STORE_AHB_GATE 64 +#define CLK_MSILITE0_AHB_GATE 65 +#define CLK_USB_SYS_AHB_GATE 66 +#define CLK_SERDES_AHB_GATE 67 +#define CLK_GPU0_AHB_GATE 68 +#define CLK_NPU_AHB_GATE 69 +#define CLK_DE_AHB_GATE 70 +#define CLK_VID_OUT1_AHB_GATE 71 +#define CLK_VID_OUT0_AHB_GATE 72 +#define CLK_VID_IN_AHB_GATE 73 +#define CLK_VE_ENC_AHB_GATE 74 +#define CLK_VE_AHB_GATE 75 +#define CLK_MBUS_MSILITE2_GATE 76 +#define CLK_MBUS_STORE_GATE 77 +#define CLK_MBUS_MSILITE0_GATE 78 +#define CLK_MBUS_SERDES_GATE 79 +#define CLK_MBUS_VID_IN_GATE 80 +#define CLK_MBUS_NPU_GATE 81 +#define CLK_MBUS_GPU0_GATE 82 +#define CLK_DEC_MBUS_GATE 83 +#define CLK_MBUS_VE_GATE 84 +#define CLK_MBUS_DESYS_GATE 85 +#define CLK_IOMMU1_MBUS_GATE 86 +#define CLK_IOMMU0_MBUS_GATE 87 +#define CLK_VE_DEC_MBUS 88 +#define CLK_GMAC1_MBUS 89 +#define CLK_GMAC0_MBUS 90 +#define CLK_ISP_MBUS 91 +#define CLK_CSI_MBUS 92 +#define CLK_NAND_MBUS 93 +#define CLK_DMA1_MBUS 94 +#define CLK_MBUS_CE 95 +#define CLK_MBUS_VE 96 +#define CLK_MBUS_DMA0 97 +#define CLK_DMA0 98 +#define CLK_DMA1 99 +#define CLK_SPINLOCK 100 +#define CLK_MSGBOX0 101 +#define CLK_PWM0 102 +#define CLK_PWM1 103 +#define CLK_DBGSYS 104 +#define CLK_SYSDAP 105 +#define CLK_TIMER0 106 +#define CLK_TIMER1 107 +#define CLK_TIMER2 108 +#define CLK_TIMER3 109 +#define CLK_TIMER4 110 +#define CLK_TIMER5 111 +#define CLK_TIMER6 112 +#define CLK_TIMER7 113 +#define CLK_TIMER8 114 +#define CLK_TIMER9 115 +#define CLK_BUS_TIMER 116 +#define CLK_AVS 117 +#define CLK_DE0 118 +#define CLK_BUS_DE0 119 +#define CLK_DI 120 +#define CLK_DI_GATE 121 +#define CLK_G2D 122 +#define CLK_G2D_GATE 123 +#define CLK_EINK 124 +#define CLK_EINK_PANEL 125 +#define CLK_EINK_GATE 126 +#define CLK_VE_ENC0 127 +#define CLK_VE_DEC 128 +#define CLK_BUS_VE_DEC 129 +#define CLK_BUS_VE_ENC 130 +#define CLK_CE 131 +#define CLK_CE_SYS 132 +#define CLK_BUS_CE 133 +#define CLK_NPU 134 +#define CLK_BUS_NPU 135 +#define CLK_GPU0 136 +#define CLK_BUS_GPU0 137 +#define CLK_DRAM0 138 +#define CLK_BUS_DRAM0 139 +#define CLK_NAND0_CLK0 140 +#define CLK_NAND0_CLK1 141 +#define CLK_BUS_NAND0 142 +#define CLK_SMHC0 143 +#define CLK_BUS_SMHC0 144 +#define CLK_SMHC1 145 +#define CLK_BUS_SMHC1 146 +#define CLK_SMHC2 147 +#define CLK_BUS_SMHC2 148 +#define CLK_SMHC3 149 +#define CLK_BUS_SMHC3 150 +#define CLK_UFS_AXI 151 +#define CLK_UFS_CFG 152 +#define CLK_UFS 153 +#define CLK_UART0 154 +#define CLK_UART1 155 +#define CLK_UART2 156 +#define CLK_UART3 157 +#define CLK_UART4 158 +#define CLK_UART5 159 +#define CLK_UART6 160 +#define CLK_TWI0 161 +#define CLK_TWI1 162 +#define CLK_TWI2 163 +#define CLK_TWI3 164 +#define CLK_TWI4 165 +#define CLK_TWI5 166 +#define CLK_TWI6 167 +#define CLK_TWI7 168 +#define CLK_TWI8 169 +#define CLK_TWI9 170 +#define CLK_TWI10 171 +#define CLK_TWI11 172 +#define CLK_TWI12 173 +#define CLK_SPI0 174 +#define CLK_BUS_SPI0 175 +#define CLK_SPI1 176 +#define CLK_BUS_SPI1 177 +#define CLK_SPI2 178 +#define CLK_BUS_SPI2 179 +#define CLK_SPIF 180 +#define CLK_BUS_SPIF 181 +#define CLK_SPI3 182 +#define CLK_BUS_SPI3 183 +#define CLK_SPI4 184 +#define CLK_BUS_SPI4 185 +#define CLK_GPADC0_24M 186 +#define CLK_GPADC0 187 +#define CLK_THS0 188 +#define CLK_IRRX 189 +#define CLK_IRRX_GATE 190 +#define CLK_IRTX 191 +#define CLK_IRTX_GATE 192 +#define CLK_LRADC 193 +#define CLK_SGPIO 194 +#define CLK_BUS_SGPIO 195 +#define CLK_LPC 196 +#define CLK_BUS_LPC 197 +#define CLK_I2SPCM0 198 +#define CLK_BUS_I2SPCM0 199 +#define CLK_I2SPCM1 200 +#define CLK_BUS_I2SPCM1 201 +#define CLK_I2SPCM2 202 +#define CLK_I2SPCM2_ASRC 203 +#define CLK_BUS_I2SPCM2 204 +#define CLK_I2SPCM3 205 +#define CLK_BUS_I2SPCM3 206 +#define CLK_I2SPCM4 207 +#define CLK_BUS_I2SPCM4 208 +#define CLK_OWA_TX 209 +#define CLK_OWA_RX 210 +#define CLK_BUS_OWA 211 +#define CLK_DMIC 212 +#define CLK_BUS_DMIC 213 +#define CLK_USB 214 +#define CLK_USB0_DEVICE 215 +#define CLK_USB0_EHCI 216 +#define CLK_USB0_OHCI 217 +#define CLK_USB1 218 +#define CLK_USB1_EHCI 219 +#define CLK_USB1_OHCI 220 +#define CLK_USB_REF 221 +#define CLK_USB2_U2_REF 222 +#define CLK_USB2_SUSPEND 223 +#define CLK_USB2_MF 224 +#define CLK_USB2_U3_UTMI 225 +#define CLK_USB2_U2_PIPE 226 +#define CLK_PCIE0_AUX 227 +#define CLK_PCIE0_AXI_SLV 228 +#define CLK_SERDES_PHY_CFG 229 +#define CLK_GMAC_PTP 230 +#define CLK_GMAC0_PHY 231 +#define CLK_GMAC0 232 +#define CLK_GMAC1_PHY 233 +#define CLK_GMAC1 234 +#define CLK_VO0_TCONLCD0 235 +#define CLK_BUS_VO0_TCONLCD0 236 +#define CLK_VO0_TCONLCD1 237 +#define CLK_BUS_VO0_TCONLCD1 238 +#define CLK_VO0_TCONLCD2 239 +#define CLK_BUS_VO0_TCONLCD2 240 +#define CLK_DSI0 241 +#define CLK_BUS_DSI0 242 +#define CLK_DSI1 243 +#define CLK_BUS_DSI1 244 +#define CLK_COMBPHY0 245 +#define CLK_COMBPHY1 246 +#define CLK_TCONTV0 247 +#define CLK_TCONTV1 248 +#define CLK_EDP_TV 249 +#define CLK_EDP 250 +#define CLK_HDMI_REF 251 +#define CLK_HDMI_TV 252 +#define CLK_HDMI 253 +#define CLK_HDMI_SFR 254 +#define CLK_HDCP_ESM 255 +#define CLK_DPSS_TOP0 256 +#define CLK_DPSS_TOP1 257 +#define CLK_LEDC 258 +#define CLK_BUS_LEDC 259 +#define CLK_DSC 260 +#define CLK_CSI_MASTER0 261 +#define CLK_CSI_MASTER1 262 +#define CLK_CSI_MASTER2 263 +#define CLK_CSI 264 +#define CLK_BUS_CSI 265 +#define CLK_ISP 266 +#define CLK_RES_DCAP_24M 267 +#define CLK_APB2JTAG 268 +#define CLK_FANOUT_25M 269 +#define CLK_FANOUT_16M 270 +#define CLK_FANOUT_12M 271 +#define CLK_FANOUT_24M 272 +#define CLK_CLK27M_FANOUT 273 +#define CLK_CLK_FANOUT 274 +#define CLK_SYS_12M 275 +#define CLK_PLL_PERI0_16M 276 +#define CLK_PLL_PERI0_25M 277 +#define CLK_FANOUT3 278 +#define CLK_FANOUT2 279 +#define CLK_FANOUT1 280 +#define CLK_FANOUT0 281 +#define CLK_BUS_DEBUG 282 +#define CLK_PLL_DDR_AUTO 283 +#define CLK_PLL_PERI0_2X_AUTO 284 +#define CLK_PLL_PERI0_800M_AUTO 285 +#define CLK_PLL_PERI0_600M_AUTO 286 +#define CLK_PLL_PERI0_480M_ALL_AUTO 287 +#define CLK_PLL_PERI0_480M_AUTO 288 +#define CLK_PLL_PERI0_160M_AUTO 289 +#define CLK_PLL_PERI0_300M_ALL_AUTO 290 +#define CLK_PLL_PERI0_300M_AUTO 291 +#define CLK_PLL_PERI0_150M_AUTO 292 +#define CLK_PLL_PERI0_400M_ALL_AUTO 293 +#define CLK_PLL_PERI0_400M_AUTO 294 +#define CLK_PLL_PERI0_200M_AUTO 295 +#define CLK_PLL_PERI1_800M_AUTO 296 +#define CLK_PLL_PERI1_600M_ALL_AUTO 297 +#define CLK_PLL_PERI1_600M_AUTO 298 +#define CLK_PLL_PERI1_480M_ALL_AUTO 299 +#define CLK_PLL_PERI1_480M_AUTO 300 +#define CLK_PLL_PERI1_160M_AUTO 301 +#define CLK_PLL_PERI1_300M_ALL_AUTO 302 +#define CLK_PLL_PERI1_300M_AUTO 303 +#define CLK_PLL_PERI1_150M_AUTO 304 +#define CLK_PLL_PERI1_400M_ALL_AUTO 305 +#define CLK_PLL_PERI1_400M_AUTO 306 +#define CLK_PLL_PERI1_200M_AUTO 307 +#define CLK_PLL_VIDEO2_3X_AUTO 308 +#define CLK_PLL_VIDEO1_3X_AUTO 309 +#define CLK_PLL_VIDEO0_3X_AUTO 310 +#define CLK_PLL_VIDEO2_4X_AUTO 311 +#define CLK_PLL_VIDEO1_4X_AUTO 312 +#define CLK_PLL_VIDEO0_4X_AUTO 313 +#define CLK_PLL_GPU0_AUTO 314 +#define CLK_PLL_VE1_AUTO 315 +#define CLK_PLL_VE0_AUTO 316 +#define CLK_PLL_AUDIO1_DIV5_AUTO 317 +#define CLK_PLL_AUDIO1_DIV2_AUTO 318 +#define CLK_PLL_AUDIO0_4X_AUTO 319 +#define CLK_PLL_NPU_AUTO 320 +#define CLK_PLL_DE_3X_AUTO 321 +#define CLK_PLL_DE_4X_AUTO 322 + +#define CLK_MAX_NO (CLK_PLL_DE_4X_AUTO + 1) + +#endif /* _DT_BINDINGS_CLK_SUN60IW2_H_ */ diff --git a/include/dt-bindings/clock/sun60iw2-cpupll-ccu.h b/include/dt-bindings/clock/sun60iw2-cpupll-ccu.h new file mode 100644 index 000000000..cd791eba2 --- /dev/null +++ b/include/dt-bindings/clock/sun60iw2-cpupll-ccu.h @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */ + +#ifndef _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_ +#define _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_ + + +#define CLK_PLL_CPU_BACK 0 +#define CLK_PLL_CPU_L 1 +#define CLK_PLL_CPU_B 2 +#define CLK_PLL_CPU_DSU 3 +#define CLK_CPU_L 4 +#define CLK_CPU_B 5 +#define CLK_CPU_DSU 6 + +#define CLK_CPUPLL_MAX_NO (CLK_CPU_DSU + 1) + +#endif /* _DT_BINDINGS_CLK_SUN60IW2_CPUPLL_H_ */ diff --git a/include/dt-bindings/clock/sun60iw2-r-ccu.h b/include/dt-bindings/clock/sun60iw2-r-ccu.h new file mode 100644 index 000000000..7bd8983a3 --- /dev/null +++ b/include/dt-bindings/clock/sun60iw2-r-ccu.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */ +/* + * Copyright (c) 2023 rengaomin@allwinnertech.com + */ + +#ifndef _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN60IW1_R_CCU_H_ + +#define CLK_R_AHB 0 +#define CLK_R_APBS0 1 +#define CLK_R_APBS1 2 +#define CLK_R_TIMER0 3 +#define CLK_R_TIMER1 4 +#define CLK_R_TIMER2 5 +#define CLK_R_TIMER3 6 +#define CLK_R_TIMER 7 +#define CLK_R_TWD 8 +#define CLK_R_BUS_PWM 9 +#define CLK_R_PWM 10 +#define CLK_R_SPI 11 +#define CLK_R_BUS_SPI 12 +#define CLK_R_MBOX 13 +#define CLK_R_UART1 14 +#define CLK_R_UART0 15 +#define CLK_R_TWI2 16 +#define CLK_R_TWI1 17 +#define CLK_R_TWI0 18 +#define CLK_R_PPU 19 +#define CLK_R_TZMA 20 +#define CLK_R_CPUS_BIST 21 +#define CLK_R_IRRX 22 +#define CLK_R_BUS_IRRX 23 +#define CLK_RTC 24 +#define CLK_RISCV_24M 25 +#define CLK_RISCV_CFG 26 +#define CLK_RISCV 27 +#define CLK_R_CPUCFG 28 +#define CLK_VDD_USB2CPUS 29 +#define CLK_VDD_SYS2USB 30 +#define CLK_VDD_SYS2CPUS 31 +#define CLK_VDD_DDR 32 +#define CLK_TT_AUTO 33 +#define CLK_CPU_ICACHE_AUTO 34 +#define CLK_AHBS_AUTO_CLK 35 + +#define CLK_R_NUMBER (CLK_AHBS_AUTO_CLK + 1) + +#endif /* _DT_BINDINGS_CLK_SUN60IW2_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun60iw2-rtc.h b/include/dt-bindings/clock/sun60iw2-rtc.h new file mode 100644 index 000000000..83fc97d75 --- /dev/null +++ b/include/dt-bindings/clock/sun60iw2-rtc.h @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */ +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + */ + +#ifndef _DT_BINDINGS_CLK_SUN60IW2_RTC_H_ +#define _DT_BINDINGS_CLK_SUN60IW2_RTC_H_ + +#define CLK_IOSC 0 +#define CLK_EXT32K_GATE 1 +#define CLK_IOSC_DIV32K 2 +#define CLK_OSC32K 3 +#define CLK_DCXO24M_DIV32K 4 +#define CLK_RTC32K 5 +#define CLK_RTC_1K 6 +#define CLK_RTC_32K_FANOUT 7 +#define CLK_RTC_DCXO_WAKEUP 8 +#define CLK_RTC_DCXO_SERDES1 9 +#define CLK_RTC_DCXO_SERDES0 10 +#define CLK_RTC_SPI 11 +#define CLK_DCXO 12 + +#define CLK_RTC_MAX_NO (CLK_DCXO + 1) + +#endif /* _DT_BINDINGS_CLK_SUN60IW2_RTC_H_ */ diff --git a/include/dt-bindings/clock/sunxi-clk.h b/include/dt-bindings/clock/sunxi-clk.h new file mode 100644 index 000000000..7727a50f4 --- /dev/null +++ b/include/dt-bindings/clock/sunxi-clk.h @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */ +/* + * Copyright (C) 2022 liujuan1@allwinnertech.com + */ + +#ifndef __DT_SUNXI_CLK_H +#define __DT_SUNXI_CLK_H + +#define TR_1 0 +#define TR_N 1 + +#define FREQ_31_5 0 +#define FREQ_32 1 +#define FREQ_32_5 2 +#define FREQ_33 3 + +#endif diff --git a/include/dt-bindings/display/sunxi-lcd.h b/include/dt-bindings/display/sunxi-lcd.h new file mode 100644 index 000000000..7b1100f9d --- /dev/null +++ b/include/dt-bindings/display/sunxi-lcd.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */ +#ifndef __SUNXI_LCD_H__ +#define __SUNXI_LCD_H__ + +/* displl */ +#define CLK_PLL_DISPLL 0 +#define CLK_DSI_LS 1 +#define CLK_DSI_HS 2 +#define CLK_LVDS_OR_RGB 3 + +/* dsi */ +#define MIPI_DSI_MODE_VIDEO 1 +#define MIPI_DSI_MODE_VIDEO_BURST (1<<1) +#define MIPI_DSI_MODE_NO_EOT_PACKET (1<<9) +#define MIPI_DSI_CLOCK_NON_CONTINUOUS (1<<10) +#define MIPI_DSI_EN_3DFIFO (1<<21) +#define MIPI_DSI_SLAVE_MODE (1<<22) +#define MIPI_DSI_MODE_VRR (1<<24) +#define MIPI_DSI_SYNC_INCELL (1<<25) +#define MIPI_DSI_ASYNC_INCELL (1<<26) + +/* lvds */ +#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010 +#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 +#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 + +/* rgb */ +#define MEDIA_BUS_FMT_RGB565_1X16 0x1017 +#define MEDIA_BUS_FMT_RGB666_1X18 0x1009 +#define MEDIA_BUS_FMT_RGB888_1X24 0x100a + +#endif diff --git a/include/dt-bindings/power/sun60iw2-power.h b/include/dt-bindings/power/sun60iw2-power.h new file mode 100644 index 000000000..6f05062ca --- /dev/null +++ b/include/dt-bindings/power/sun60iw2-power.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_SUN60IW2_H__ +#define __DT_BINDINGS_POWER_SUN60IW2_H__ + +#define SUN60IW2_PCK_VI 0 +#define SUN60IW2_PCK_DE_SYS 1 +#define SUN60IW2_PCK_VE_DEC 2 +#define SUN60IW2_PCK_VE_ENC 3 +#define SUN60IW2_PCK_NPU 4 +#define SUN60IW2_PCK_GPU_TOP 5 +#define SUN60IW2_PCK_GPU_CORE 6 +#define SUN60IW2_PCK_PCIE 7 +#define SUN60IW2_PCK_USB2 8 +#define SUN60IW2_PCK_VO 9 +#define SUN60IW2_PCK_VO1 10 + +#endif diff --git a/include/dt-bindings/reset/sun60iw2-ccu.h b/include/dt-bindings/reset/sun60iw2-ccu.h new file mode 100644 index 000000000..c442591a5 --- /dev/null +++ b/include/dt-bindings/reset/sun60iw2-ccu.h @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */ +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + */ + +#ifndef _DT_BINDINGS_RESET_SUN60IW2_H_ +#define _DT_BINDINGS_RESET_SUN60IW2_H_ + +#define RST_BUS_ITS_PCIE0 0 +#define RST_BUS_NSI 1 +#define RST_BUS_NSI_CFG 2 +#define RST_BUS_IOMMU0_SY 3 +#define RST_BUS_MSI_LITE0_MBU 4 +#define RST_BUS_MSI_LITE0_AHB 5 +#define RST_BUS_MSI_LITE1_MBU 6 +#define RST_BUS_MSI_LITE1_AHB 7 +#define RST_BUS_MSI_LITE2_MBU 8 +#define RST_BUS_MSI_LITE2_AHB 9 +#define RST_BUS_IOMMU1_SY 10 +#define RST_BUS_DMA0 11 +#define RST_BUS_DMA1 12 +#define RST_BUS_SPINLOCK 13 +#define RST_BUS_MSGBOX0 14 +#define RST_BUS_PWM0 15 +#define RST_BUS_PWM1 16 +#define RST_BUS_DBGSY 17 +#define RST_BUS_SYSDAP 18 +#define RST_BUS_TIMER0 19 +#define RST_BUS_DE0 20 +#define RST_BUS_DI 21 +#define RST_BUS_G2D 22 +#define RST_BUS_EINK 23 +#define RST_BUS_DE_SY 24 +#define RST_BUS_VE_DEC 25 +#define RST_BUS_VE_ENC0 26 +#define RST_BUS_CE_SY 27 +#define RST_BUS_CE 28 +#define RST_BUS_NPU_AHB 29 +#define RST_BUS_NPU_AXI 30 +#define RST_BUS_NPU_CORE 31 +#define RST_BUS_GPU0 32 +#define RST_BUS_DRAM0 33 +#define RST_BUS_NAND0 34 +#define RST_BUS_SMHC0 35 +#define RST_BUS_SMHC1 36 +#define RST_BUS_SMHC2 37 +#define RST_BUS_SMHC3 38 +#define RST_BUS_UFS_AXI 39 +#define RST_BUS_UFS_AHB 40 +#define RST_BUS_UART0 41 +#define RST_BUS_UART1 42 +#define RST_BUS_UART2 43 +#define RST_BUS_UART3 44 +#define RST_BUS_UART4 45 +#define RST_BUS_UART5 46 +#define RST_BUS_UART6 47 +#define RST_BUS_TWI0 48 +#define RST_BUS_TWI1 49 +#define RST_BUS_TWI2 50 +#define RST_BUS_TWI3 51 +#define RST_BUS_TWI4 52 +#define RST_BUS_TWI5 53 +#define RST_BUS_TWI6 54 +#define RST_BUS_TWI7 55 +#define RST_BUS_TWI8 56 +#define RST_BUS_TWI9 57 +#define RST_BUS_TWI10 58 +#define RST_BUS_TWI11 59 +#define RST_BUS_TWI12 60 +#define RST_BUS_SPI0 61 +#define RST_BUS_SPI1 62 +#define RST_BUS_SPI2 63 +#define RST_BUS_SPIF 64 +#define RST_BUS_SPI3 65 +#define RST_BUS_SPI4 66 +#define RST_BUS_GPADC0 67 +#define RST_BUS_THS0 68 +#define RST_BUS_IRRX 69 +#define RST_BUS_IRTX 70 +#define RST_BUS_LRADC 71 +#define RST_BUS_SGPIO 72 +#define RST_BUS_LPC 73 +#define RST_BUS_I2SPCM0 74 +#define RST_BUS_I2SPCM1 75 +#define RST_BUS_I2SPCM2 76 +#define RST_BUS_I2SPCM3 77 +#define RST_BUS_I2SPCM4 78 +#define RST_BUS_OWA 79 +#define RST_BUS_DMIC 80 +#define RST_USB_0_PHY_RSTN 81 +#define RST_USB_0_DEVICE 82 +#define RST_USB_0_EHCI 83 +#define RST_USB_0_OHCI 84 +#define RST_USB_1_PHY_RSTN 85 +#define RST_USB_1_EHCI 86 +#define RST_USB_1_OHCI 87 +#define RST_USB_2 88 +#define RST_BUS_PCIE0 89 +#define RST_BUS_PCIE0_PWRUP 90 +#define RST_BUS_SERDES 91 +#define RST_BUS_GMAC0_AXI 92 +#define RST_BUS_GMAC0 93 +#define RST_BUS_GMAC1_AXI 94 +#define RST_BUS_GMAC1 95 +#define RST_BUS_VO0_TCONLCD0 96 +#define RST_BUS_VO0_TCONLCD1 97 +#define RST_BUS_VO0_TCONLCD2 98 +#define RST_BUS_LVDS0 99 +#define RST_BUS_LVDS1 100 +#define RST_BUS_DSI0 101 +#define RST_BUS_DSI1 102 +#define RST_BUS_TCONTV0 103 +#define RST_BUS_TCONTV1 104 +#define RST_BUS_EDP 105 +#define RST_BUS_HDMI_HDCP 106 +#define RST_BUS_HDMI_SUB 107 +#define RST_BUS_HDMI_MAIN 108 +#define RST_BUS_DPSS_TOP0 109 +#define RST_BUS_DPSS_TOP1 110 +#define RST_BUS_VIDEO_OUT0 111 +#define RST_BUS_VIDEO_OUT1 112 +#define RST_BUS_LEDC 113 +#define RST_BUS_DSC 114 +#define RST_BUS_CSI 115 +#define RST_BUS_VIDEO_IN 116 +#define RST_BUS_APB2JTAG 117 +#define RST_BUS_UFS_PHY 119 +#define RST_BUS_UFS_CORE 120 + +#endif /* _DT_BINDINGS_RESET_SUN60IW2_H_ */ diff --git a/include/dt-bindings/reset/sun60iw2-r-ccu.h b/include/dt-bindings/reset/sun60iw2-r-ccu.h new file mode 100644 index 000000000..0a181e323 --- /dev/null +++ b/include/dt-bindings/reset/sun60iw2-r-ccu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* Copyright(c) 2020 - 2023 Allwinner Technology Co.,Ltd. All rights reserved. */ +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + */ + +#ifndef _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_ + +#define RST_BUS_R_TIME 0 +#define RST_BUS_R_PWM 1 +#define RST_BUS_R_SPI 2 +#define RST_BUS_R_MBOX 3 +#define RST_BUS_R_UART1 4 +#define RST_BUS_R_UART0 5 +#define RST_BUS_R_TWI2 6 +#define RST_BUS_R_TWI1 7 +#define RST_BUS_R_TWI0 8 +#define RST_BUS_R_IRRX 9 +#define RST_BUS_RTC 10 +#define RST_BUS_RISCV_CFG 11 +#define RST_BUS_R_CPUCFG 12 +#define RST_BUS_MODULE 13 + +#endif /* _DT_BINDINGS_RST_SUN60IW2_R_CCU_H_ */