* changes:
feat(tc): enable workaround for CVE-2026-0995
fix(security): workaround for C1-Pro/CME CVE-2026-0995
feat(psci): add psci_cpu_off_start event
feat(smccc): add support for CPU Service calls
This SME erratum in C1-Pro means memory accesses from the CME unit can
remain outstanding after another CPU issues TLBI+DSB. This means SME
can access memory after it has been re-allocated, potentially
overwriting the new owner's data. With pKVM, this could allow the host
access to guest memory if the SME accesses survived the page being
donated to HYP and allocated to the guest.
The workaround is for all affected CPUs to issue DSB locally whenever
another CPU does TLB maintenance. The local DSB completes all
outstanding accesses.
Linux and pKVM share a security state in the GIC, meaning pKVM would
be exposed to interrupt blackouts caused by linux. It is difficult
for the non secure world to avoid races when an SGI is sent to a CPU
that is about go offline and can no longer take the interrupt.
(this would violate the PSCI rules for CPU_OFF calls).
Implement the workaround in EL3 using an SMC in the 'CPU vendor' space.
The workaround uses atomic_inc_return on a global counter to order
parallel callers. This gives each caller a deadline.
Secure SGI are sent to the affected C1 Pro CPUs causing them to run
the workaround, and update their local counter from the global counter.
The CPU that issued the SMC then waits for each SGI'd CPU to update
to at least the deadline from its call.
An SGI being sent can race with an SMC to PSCI CPU_OFF. To avoid
this SGI preventing the CPU from enterring WFI to power off, the
workaround is run pre-emptively and the SGI is masked at the GIC
redistributor.
This mitigation is coordinated with corresponding Operating System
updates for CVE-2026-0995. Both EL3 (TF-A) and the OS must include
their respective fixes to ensure complete mitigation. For example,
the Linux kernel implements a complementary workaround that must
be deployed alongside this TF-A update.
Linux commit:
https://lore.kernel.org/all/20260302165801.3014607-1-catalin.marinas@arm.com/
Ref: https://developer.arm.com/documentation/111823/latest/
Change-Id: Ie969354ad0693fe172d921953b87cfbf4a39ea8e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Together with the psci_cpu_on_finish event this is useful to track the
online state of cores.
We cannot trigger the event much later, as then the CPU will be partly
off already (left coherency, for instance).
Change-Id: I072647ece6847b11af1d0e3a0686f5dfd1f2ea58
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Add support for CPU Service Calls SMC.
SMCCC Documentation reference:
https://developer.arm.com/docs/den0028/latest
Change-Id: Ie415af366de84350bd5f20dec869c2f57a37c0d1
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Newer compilers accept C style integer literal suffixes (like `1ULL`) in
assembly code. Unfortunately, this seems to be a recent development and
older compilers do not. Convert uses of these suffixes to use the
helpers from utils_def_exp.h that will expand correctly.
Change-Id: I5a6e4a52e3c9c85b964fd9fc88548af68cc9998e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
* changes:
refactor(cpufeat): clump FEAT_PACQARMA3 with FEAT_PAuth
refactor(cpufeat): simplify FEAT_MTPMU helpers
refactor(cpufeat): bring MPAM and DIT to the feat_detect pattern
refactor(cpufeat): drop redundant comments from arch_features.h
FEAT_RAS does not provide an architectural way to disable its system
registers from lower ELs. It does provide a way to trap their accesses
to EL3 but no way to communicate this to lower ELs (eg. with ID
registers). As such, from a lower ELs perspective if FEAT_RAS is
implemented, then it is perfectly valid to issue accesses to any
FEAT_RAS registers.
Today that is not the case. When lower EL software issues such an access
it will instead get an UNDEF exception (injected by EL3) which is not
architecturally correct. It's not illogical to do this - the RAS System
Architecture mandates very little and it leaves access control to be an
IMPDEF choice of being handled in hardware of firmware without a
discovery mechanism and so we must assume no hardware access control.
So to comply with both requirements, implement a rudimentary software
based access control. This reuses the old flags (FAULT_INJECTION_SUPPORT
and RAS_TRAP_NS_ERR_REC_ACCESS). If they do not permit access, emulate
them as RAZ/WI. If access is permitted, do not trap in the first place.
Change-Id: Ie202291b096f0394230387a8d58ff56ebb7f68a3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
They two are inherently related and the ID register update helper
already treats them as one. Combine them to save on some code.
Change-Id: I4bdc021d98e053cece6619889334828a5b679d28
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The ID register field follows the general convention: 0 means missing,
anything over 1 means implemented. The special value of 0b1111 has the
semantics of "feature unconditionally enabled" which follows this rule.
There is no need to special case the feature and code can be simpler.
Change-Id: Iaf90eb1f8abb22a48054b4e564dad669e1703dcb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The enablement for FEAT_MPAM and FEAT_DIT happened when the feat_state
framework was fairly fresh so they don't follow the patterns that have
emerged since. Convert them to follow these patterns.
Change-Id: Id04915a3d1d5c3e4f8702f03e53494703e6de6dc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The definitions of each feature include all necessary information to
fully understand what it is about. The expansion of the name is also
duplicate to the explanations in defaults.mk and the docs and adds to
cognitive load during review. Further, the comments aren't particularly
consistent.
Drop the comments to reduce duplication. These are always documented in
the Arm ARM.
Change-Id: I749629f924dd818285b7970e52ef8c413787d291
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
* changes:
refactor(build): remove FEAT_CSV2_2 enable from ENABLE_RMM
fix(arm): clean up FEAT_RME #ifdefs
fix(cpufeat): add arch_extension directives to bit_lock() too
Update the mbed TLS submodule to the 3.6.6 release and bump
MBEDTLS_CONFIG_VERSION in default_mbedtls_config.h so the
Trusted Firmware-A configuration matches the imported version.
Change-Id: I9f90eecfbce203a89c61e864ef3f85677efad1c4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
When AES-GCM is enabled, use the AESCE backend and set
MBEDTLS_AES_USE_HARDWARE_ONLY to avoid falling back to the
plain-C AES implementation when FEAT_CRYPTO is available.
Change-Id: I17750618646aea962a91c4fae551bff65acf30f3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Remove flags used for configuring watchdog during low power phases.
The configuration to stop watchdog during standby and s2idle is done in
OP-TEE.
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Change-Id: Ib68d5bf31d7f97791af6b25327b374771b75fd4e
Demonstrate the migration of Arm platform SiP handlers to the new SMC
validation framework with type-safe smc_get_mem_range() usage.
Change-Id: Ifcc85becd146f2e638b1e08be6a1cdba43b91d3b
Signed-off-by: Kenneth Kabogo <kennethkabogo2@gmail.com>
This patch introduces a standardized framework for validating SiP SMC
arguments in EL3 runtime services to mitigate Privilege-Blind Forwarding
(PBF) and TOCTOU race conditions.
The framework provides:
- Atomic Shadow-Copy with smc_get_mem_range() inline function
- Type-safe validation using uintptr_t and size_t
- Integer overflow protection for memory range tuples
- Architecture-aware register mapping in common/smc_validation.c
Change-Id: Icf8f658c16fb25989eb757b71f70668c787c3153
Signed-off-by: Kenneth Kabogo <kennethkabogo2@gmail.com>
The Arm ARM says that a successful read of RNDR(RS) should return with
PSTATE.NZCV == 0 and a failed one should read 0 and PSTATE.NZCV ==
0b0100. No platform hooks emulate this PSTATE behaviours and neither
does generic code.
This patch adds the emulation in generic code so that platform hooks
don't have to. To do this, simplify the platform hook even further - it
now has one job: to return the value and if it was successful. All the
architectural parsing is now fully generic.
Change-Id: Ica35aa6f10cc3dd6fa6ba91e6de1bec68260953d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The pattern for is_feat_xyz_supported() is to not use any #if directives
around it and instead to rely on the compiler to do the right thing an
compile the redundant branches away. This does require a bit of dancing
to appease the compiler - there needs to be an empty function when
FEAT_XYZ is 0 to prevent linker errors.
Change-Id: I4e5eeec7c47d0d1a3dba45757d3d820d380d8e36
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Cortex-A57 erratum 817171 is a Cat B erratum that applies to revisions
r0p0, r0p1. It is fixed in r1p0.
Set L2ACTLR_EL1[26] to 1'b1 to disable L2 regional clock gating.
SDEN documentation:
https://developer.arm.com/documentation/epm049219/latest
Change-Id: I3cf8e70a6abcab8f51098fb22a1d383e123a53d6
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-X1 erratum 2779479 is a Cat B erratum that applies to revisions
r0p0, r1p0, r1p1, r1p2. It is still open.
The erratum can be avoided by setting CPUACTLR3_EL1[47]. Setting this
chicken bit might have a small impact on power and negligible impact
on performance.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401782/latest
Change-Id: I4926f7054be48b08f02f0a4de66114b4d51a5738
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-X1 erratum 1515634 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.
Set CPUACTLR_EL1[11] to one, which flushes the L0 Macro-op cache for
all context synchronization events.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401782/latest
Change-Id: I39bfe27c8dfe575994323aeedf0ed73d1e83745d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-X1 erratum 1492189 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.
The workaround is to set CPUACTLR5_EL1[8] to 1'b1. The workaround
might result in a small increase in core power consumption.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401782/latest
Change-Id: I288f88f092ee05c15cefb2e764663f4d17fc10a5
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-X4 erratum 2646977 is a Cat B erratum that applies to revision
r0p0. It is fixed in r0p1.
This erratum can be avoided by setting CPUACTLR5_EL1[56:55] to 0b01.
SDEN documentation:
https://developer.arm.com/documentation/109148/latest
Change-Id: Ica7e339280aa97c7d9f6fd8100bd463e4dd978ac
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-A510 erratum 1975068 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.
In some systems, software can avoid using Non-shareable mappings.
Where that is not possible, software can set IMP_CMPXECTLR_EL1[9:8] =
0b11. This disables early forwarding of L2 hardware prefetches to
subsequent requests, and may incur a small but not negligible
performance impact.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest
Change-Id: I3ac6cbf43a0bbb798b5e39ee1030376afc1b125a
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
QTI SMMU driver is only enabled on Kodiak without QTISECLIB being
enabled. So clean up the driver inclusion and remove any #ifdefry
from common code to make it more readable.
Change-Id: I6d7d4b2f12e1e8fc1b4126895a6ddf6c9a516f7e
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Cortex-A510 erratum 1910738 is a Cat B erratum that applies to
revision r0p0. It is fixed in r0p1.
This erratum can be avoided by setting IMP_CPUECTLR_EL1[19] = 1,
IMP_CPUACTLR_EL1[4] = 1 and IMP_CPUACTLR_EL1[26] = 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest
Change-Id: I93ebe8dc7908c52239cfe10d063016a58855f17f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
* changes:
feat(cpufeat): constrain RAS_TRAP_NS_ERR_REC_ACCESS on ENABLE_FEAT_RAS
fix(build): set defaults to feature flags before platform.mk
refactor(cpufeat): unify FEAT_IDTE3's definitions with arch.h
refactor(el3-runtime): generalise sysreg trapping
refactor(el3-runtime): use contexted SCR_EL3 instead of the register
build: rename default_ones to set_ones
QTI xPU bypass driver is only needed on Kodiak when QTISECLIB is
enabled to workaround an issue observed during Linux boot. So clean
up the driver inclusion and remove any #ifdefry from common code to
make it more readable.
Change-Id: Ieca67a8298443a672b718dff34c79c1b49918251
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
This patch introduces five assembly macros that collapse multiple
bit-manipulation operations on the same system register into a
single mrs/msr pair:
sysreg_lazy_start _reg -- read register into x1
sysreg_lazy_set _bit -- ORR bit into x1 (any 64-bit mask)
sysreg_lazy_clear _bit -- BIC bit from x1 (any 64-bit mask)
sysreg_lazy_insert _src, _lsb, _width -- BFI into x1
sysreg_lazy_commit _reg -- write x1 back to register
Each sysreg_bit_set / sysreg_bit_clear / sysreg_bitfield_insert call
issues its own mrs+msr pair. When several of those target the same
register the reads and writes are redundant. The lazy helpers
replace N reads and N writes with one read and one write.
x1 holds the accumulated register value between start and commit.
x0 is used as a scratch register by sysreg_lazy_set,
sysreg_lazy_clear, and sysreg_lazy_insert. mov_imm is used for bit
values to support arbitrary 64-bit masks, consistent with the
existing hand-written mrs/mov_imm/orr/msr patterns in CPU files.
Change-Id: Iaaf0e4bd7ba85c69d9063b012a9066b3ba40b58e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Cortex-A77 erratum 1515815 is a Cat B erratum that applies to
revisions r0p0, r1p0. It is fixed in r1p1.
Set CPUACTLR_EL1[11] to 1 so that the L0 Macro-op cache is flushed for
all context synchronization events, ensuring that only a single
instruction is executed before a software step or halt step exception
is taken.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest
Change-Id: I1e6faf5a699734f9a5be848807e9c3fa5110d569
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-A77 erratum 1253791 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.
This erratum can be avoided by setting CPUACTLR3_EL1[10] to 1, which
prevents parallel execution of divide and square root instructions.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest
Change-Id: I76895d167a477246ff5bc6c87237fb4f9724c547
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-A77 erratum 1220737 is a Cat B erratum that applies to revision
r0p0. It is fixed in r1p0.
This erratum can be avoided by setting CPUECTLR_EL1[25:24] to 0b11,
which disables write streaming to the L2. This will have an impact on
performance for streaming workloads.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1152370/latest
Change-Id: Iad21fad2b774234b1df808a4074eb3aabc01f2f3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-A78AE erratum 2779481 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is fixed in r0p3.
The erratum can be avoided by setting CPUACTLR3_EL1[47].
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest
Change-Id: If45cd8efe24768aaa0d31f56b3b297ba1c10980f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-A78AE erratum 2743229 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2. It is fixed in r0p3.
This erratum can be avoided by setting CPUACTLR5_EL1[56:55] to 0b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1707912/latest
Change-Id: Ic9a60a695eb00574c25490376337a4ad09b9b2c7
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
libeventlog provides its own tcg.h, and this should be used.
Remove old tcg.h from TF-A source tree.
Change-Id: I58c6af9480d4bee11751aeebd53829da0bde52c4
Signed-off-by: Matthew Ellis <Matthew.Ellis@arm.com>
Cortex-A715 erratum 2292761 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
This erratum can be avoided by setting CPUACTLR4_EL1[13] to 1. Using
this workaround has no performance impact.
SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest
Change-Id: Ie2bddb8535a0070da1a58a7753ad3a95c5005646
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Cortex-A78 erratum 1479939 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
This erratum can be avoided by setting CPUACTLR_EL1[13] to 1 to
disable a performance feature. This should be done before enabling the
MMU.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1401784/latest
Change-Id: I553697b5d34da00298526ee0988f52dea8e9e93f
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
