FEAT_RAS does not provide an architectural way to disable its system
registers from lower ELs. It does provide a way to trap their accesses
to EL3 but no way to communicate this to lower ELs (eg. with ID
registers). As such, from a lower ELs perspective if FEAT_RAS is
implemented, then it is perfectly valid to issue accesses to any
FEAT_RAS registers.
Today that is not the case. When lower EL software issues such an access
it will instead get an UNDEF exception (injected by EL3) which is not
architecturally correct. It's not illogical to do this - the RAS System
Architecture mandates very little and it leaves access control to be an
IMPDEF choice of being handled in hardware of firmware without a
discovery mechanism and so we must assume no hardware access control.
So to comply with both requirements, implement a rudimentary software
based access control. This reuses the old flags (FAULT_INJECTION_SUPPORT
and RAS_TRAP_NS_ERR_REC_ACCESS). If they do not permit access, emulate
them as RAZ/WI. If access is permitted, do not trap in the first place.
Change-Id: Ie202291b096f0394230387a8d58ff56ebb7f68a3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Update the EL3 Runtime Service Writer's Guide with security best
practices for SMC argument validation, including PBF mitigation
strategies and the Atomic Shadow-Copy principle.
Change-Id: I8d38addccb793bc4d7ed84be76921a2126fe5c41
Signed-off-by: Kenneth Kabogo <kennethkabogo2@gmail.com>
FEATURE_DETECTION has received a lot of attention since its introduction
and at this point is quite reliable. Its experimental designation is no
longer appropriate and it would be quite reasonable to use this feature
by default.
Always enable the feature for FVP so that we can have confidence that
the SW view of HW is up to date.
This patch also drops the mention of errata reporting around
FEATURE_DETECTION as this hasn't been true for some time.
Change-Id: I4a94dce243e430d5d3528c66154075b4352cd520
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Update documentation to reflect the use of GCC version 15.2.Rel1,
the latest production release available at:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I841d494f2226cbbf0bd388c4eb89548f62e069d3
Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME related support is now enabled using feature detection option
ENABLE_FEAT_RME, this patch moves GPT support under ENABLE_FEAT_RME.
This change brings in below benefits:
- single TF-A build that works for RME and non-RME systems, when
build with ENABLE_FEAT_RME=2 (FEAT_STATE_CHECK)
- RMM loading is optional on RME systems
- SiP calls that leverages RME features to change the PAS of a memory
range from non-secure to secure is supported without need to enable
Realm PAS or RMM.
- FIRME Granule Management Interface (GMI) ABIs that handles
FEAT_RME_GPC2/FEAT_RME_GDI can be enabled without need to enable RMM
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I88d9d4e0491af2b4ae0307c018f2d4a71ee6693f
RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.
Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.
For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192
ENABLE_RME currently controls multiple, distinct aspects of RME support,
including forcing BL2 to EL3, ROOT world page table setup, GPT
initialization, and full RMM loading and handling.
While full CCA support requires all of these steps, some systems running
on FEAT_RME-capable cores do not need or want an RMM. However, such
systems still require TF-A page table entries to set the .NSE bit so
that TF-A accesses are correctly attributed to the ROOT world,
otherwise, enabling the MMU may cause the system to hang.
To address this, a new build option, ENABLE_FEAT_RME, is introduced. It
handles only the .NSE PTE setup and ignores the rest of the RME/RMM
initialization. ENABLE_FEAT_RME follows the ENABLE_FEAT_* convention and
supports values 0–2, with 2 enabling runtime detection.
Full RME functionality remains gated by ENABLE_RME, which now implicitly
enables ENABLE_FEAT_RME, allowing TF-A to run safely on FEAT_RME systems
without requiring an RMM.
Change-Id: I8391652842ff2e62a73b61829c6250c3805d4a4e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Set the default value of RMM_V1_COMPAT to 0. This means by default, TF-A
will only work with an RMM which is aligned to RMMv2.0 specification.
BREAKING-CHANGE: RMM v1.x compatibility is now disabled by default.
Platforms which continue to rely on the RMM v1 ABI must explicitly
build TF-A with `RMM_V1_COMPAT=1`.
Change-Id: Icf0e2dc9ebd8991cc989930807997625282191c3
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
This is the first FIRME service patch that adds support for basic ABIs
for retrieving the FIRME version, features, and GPI_SET.
This adds a new generic granule transition function that replaces
the existing delegate/undelegate APIs that GPI_SET uses. It also
updates TRP to use GPI_SET when FIRME is supported.
FIRME spec is here, note that it is ALPHA2 quality so further changes
are to be expected:
https://developer.arm.com/documentation/den0149
Change-Id: I57b8ad7e87a0679e15c8247f8457f91f3254dedb
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.
The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.
This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.
Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Add an opt-in negative test mode that simulates a short read
for a selected image_id during image loading. This exercises
the partial-read error handling path and is intended for CI
validation only.
Disabled by default via build options.
Change-Id: I219b75898e1778c0b263f99a9370425098d52f8f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The GICv3 is architectured to solely manage interrupts targeted to
Normal and Secure world. It doesn't manage interrupts targeting the
more recently introduced Realm world. Hence the new RMMv2.0
specification mandates that EL3 should not save and restore
the GIC registers on a world switch. This change is not backward
compatible with RMMv1.x ABI.
Note the change in implementation of cm_el2_sysregs_context_save()
and cm_el2_sysregs_context_restore() API as GIC state is not
managed by these APIs anymore.
Add new build flag RMM_V1_COMPAT to support backward compatibility
with RMMv1.x. This flag is currently enabled by default.
This patch is a reworked version of the original patch at:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/45658
NOTE: If RMM_V1_COMPAT is not enabled, then RMM_EL3_IFC_VERSION
is bumped to 1.0 which makes it incompatible with an RMM supporting
0.x.
Change-Id: If4c53b85ef31091c254b383ed7b32c39124f0dbb
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Rely on build options BL2_RUNS_AT_EL3 and BL2_INV_DCACHE to invalidate
the data cache upon BL2 entry and this shouldn't be tied with ENABLE_RME
build flag. This also ensures that if a platform sets
BL2_INV_DCACHE, it takes precedence over feature flags.
This change also restores documentation for BL2_INV_DCACHE, which was
accidentally removed by commit 43f35ef51.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I52bdfe351c730f62d79a518327f57b398c7b29c5
This change adds Mbed TLS 3.6.5 as a submodule to the TF-A repository.
It is no longer a requirement to pass `MBEDTLS_DIR` to the build system
when building configurations which require it, as the build system will
now look inside the `contrib` directory if the parameter is missing.
If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:
git submodule update --init --recursive
BREAKING-CHANGE: Mbed TLS is now included in the TF-A repository, and it
is no longer a requirement to pass `MBEDTLS_DIR` to the build system.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.
Change-Id: Iad777e77936d1c373065f17fe5c4aadc45e56b64
Signed-off-by: Chris Kay <chris.kay@arm.com>
This patch documents the support for SP live activation by a reference
SPM implementation as well as provides the guidance for platform
integrators to build Logical Secure Partition, which is needed to
orchestrate live activation of an SP in coordination with SPMC.
The corresponding build flags have been documented as well.
Change-Id: I88920344267f86f5e9916ea3632de78af32469ef
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS world only and are not context switched as a result. There is
no use for this feature at EL3.
Change-Id: Ica7a312d891a1671df8e9f2adbfe464d96bbcd4d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for NS only and do not context switch the registers. There is
no use of the feature at EL3.
Change-Id: I174a256d70a99abfafc65eed3a2fbdaea5ea946d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.
Change-Id: I70e2a488f4e50da4b181a00648c4f608e1da451c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
* changes:
feat(qemu): disable fpregs traps for QEMU in BL31
feat(crypto): enable the runtime instrumentation for crypto extension
feat(crypto): enable access to SIMD crypto in BL1 and BL2
feat(crypto): enable floating point register traps in EL3
feat(crypto): build flag for SIMD crypto extensions for v8+ platform
refactor(build): add a default filter list for lib cflags
Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest
Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
Add new build flags ENABLE_FEAT_CRYPTO to enable SIMD crypto extension
for hash256 in bootflow authentication process and ENABLE_FEAT_CRYPTO_SHA3
to enable SIMD crypto extension for sha384 and sha512 in bootflow authentication
process for Arm platform greater than v8.0.
Change-Id: I6e52feb318136910d34cafd89319bf94f90e16fc
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
FEAT_SB is mostly FEAT_STATE_CHECKED enabled but that is not apparent
from docs and code's check is sub-optimal. Update docs to make this
apparent and update code to have a proper FEAT_STATE_CHECKED fallback.
Also enable it for FVP so it's tested a bit more.
Change-Id: I1374c4828b235ad16904f6c4ac9e39b9c2596a37
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply
saying it impacts execution at EL3. That's true, but FEAT_STATE_CHECKED
can still be allowed by being a bit clever about it.
First, the remainder of common code can be converted to use the
is_feat_ras_supported() helper instead of the `#if FEATURE` pattern.
There are no corner cases to consider there. The feature is either
present (and appropriate action must be taken) or the feature is not (so
we can skip RAS code).
A conscious choice is taken to check the RAS code in synchronize_errors
despite it being in a hot path. Any fixed platform that seeks to be
performant should be setting features to 0 or 1. Then, the
SCTLR_EL3.IESB bit is always set if ENABLE_FEAT_RAS != 0 since we expect
FEAT_IESB to be present if FEAT_RAS is (despite the architecture not
guaranteeing it). If FEAT_RAS isn't present then we don't particularly
care about the status of FEAT_IESB.
Second, platforms that don't set ENABLE_FEAT_RAS must continue to work.
This is true out of the box with the is_feat_xyz_supported() helpers, as
they make sure to fully disable code within them.
Third, platforms that do set ENABLE_FEAT_RAS=1 must continue to work.
This is also true out of the box and no logical change is undertaken in
common code.
Finally, ENABLE_FEAT_RAS is set to 2 on FVP. Having RAS implies that the
whole handling machinery will be built-in and registered as appropriate.
However, when RAS is built-in but not present in hardware, these
registrations can still happen, they will only never be invoked at
runtime.
Change-Id: I949e648601dc0951ef9c2b217f34136b6ea4b3dc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
When log level set to verbose, xlat prints
alot of translation table debug logs.These
detail logs keeps on printing for minutes
and increase boot time. Also, not all users
might be interested in the xlat detail
logs when verbose is on.
LOG_DEBUG is added to print xlat detail
logs only when someone intentionally
enables logging.
Change-Id: I3308b49779a692bdce87fb6929c88fdcb713e628
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>
This patch adds a build macro ENABLE_FEAT_MORELLO which when set will
compile BL31 firmware with changes required to boot capability
aware software.
It also adds helper function in c and assmbly to check if morello
hardware is present and if morello capability is enabled or not.
CE field, bits [23:20] in ID_AA64PFR1_EL1 defines whether morello
architecture is present or not, 0b0000 indicates that it is absent
and 0b0001 indicates that it is present. While whether capabilities
are enabled or not is decided at runtime with ENABLE_FEAT_MORELLO build
option.
Reference: https://developer.arm.com/documentation/ddi0606/latest/
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: Ib16877acbfcb72c4bd8c08e97e44edc0a3e46089
With `ERRATA_SME_POWER_DOWN` enabled we disconnect SME from
core to power down the core correctly, we actually don't disable sme.
Change-Id: I42b99bd5ef125868f55a2a3ef96c0ac1b054f509
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've gained
lots of quality of life features that allow for better feature
enablement. This patch converts USE_SPINLOCK_CAS to tri-state and adds
it to FEATURE_DETECTION to align with all other features.
Instead of introducing the assembly checking for tri-state, this patch
translates all locking routines to C inline assembly and uses the
standard C helpers. The main benefit is that this gives greater
visibility to the compiler about what the functions are doing and lets
it optimise better. Namely, it is able to allocate registers itself and
inline the functions when LTO is enabled.
An unsuccessful attempt was made to use the instructions directly and
have even flow control in C. This, however, made code very complicated
and less efficient in the tight loops of the spinlock.
The last use of ARM_ARCH_AT_LEAST goes away with this change and so this
macro is removed. It has now been fully superseded by the FEAT_STATE
framework.
This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requires
USE_SPINLOCK_CAS. This patch does not address this in any way but makes
the relationship explicit.
Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algorithm metadata at runtime. Add mboot_find_event_log_metadata() as a
common helper for resolving image metadata. Update the Event Log build
logic to use MAX_DIGEST_SIZE and MAX_HASH_COUNT, deprecate legacy
MBOOT_EL_HASH_ALG, and warn when it is used. Adjust MbedTLS
configuration to enable hash algorithms automatically when Measured Boot
is enabled.
Change-Id: I704e1a5005f6caad3d51d868bacc53699b6dd64f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): update feature names and comments
fix(cpufeat): simplify AArch32 feature disablement
Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/
Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).
This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b
Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimisations to be made across compilation unit boundaries (i.e. C
files). This is especially useful in areas with lots of closely related
compilation units that operate on the same data structures (eg PSCI and
context management).
The only drawback is that LTO makes conditions ripe for the build to
heavily mangle all functions, making debugging a nightmare. So only
enable for release builds.
Note this will make object files unintepretable by objdump. Use lto-dump
instead.
BREAKING-CHANGE: LTO has been enabled by default, which may cause
unpredictable issues for platforms where the linker scripts have not
been designed with LTO in mind. Please report any issues to the
[mailing list](mailto:tf-a@lists.trustedfirmware.org).
Change-Id: Ia472aff1a23366d918abded7a1c5da695f2c4787
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The minimum Node version was updated to the latest LTS release. Update
the docs to reflect this change. While we're at it, clean up remaining
references from the Arm GNU toolchain version update and set the minimum
for GNU Make to whatever is provided by Ubuntu 22.04.
Change-Id: I16923c9cf69b34f78f19bc10e3bed72b70ae8132
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
* changes:
feat(cpufeat): add support for FEAT_IDTE3
feat(cpufeat): include enabled security state scope
feat(cpufeat): add ID register defines and read helpers
This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.
The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.
The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.
FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.
This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.
This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5
Adding features is an arcane job with a long list of things to consider.
There is no single place to list these things so someone new to this
must be guided along, usually at code review. Further, the process
changes occasionally so it can be difficult even for an experienced
contributor to get right.
So add a checklist along with brief explanations on what to look for so
we can make our job nicer.
Change-Id: I09dd0062b742c9fce5a8f86a2067adc941db6899
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/
On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.
Ref- https://developer.arm.com/documentation/102898/0108/
Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
It is already described in the porting guide and context management
sections so it's largely redundant. It also hasn't been updated for a
while despite lots going on around PSCI so it's clearly not read often.
The only part that isn't is that for describing a new secure dispatcher,
which belongs in the porting guide.
Change-Id: Icdc53e19565f0785bc8a112e5eb49df1b365c66c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Update documentation to reflect the use of GCC version 14.3.Rel1,
the latest production release available at:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I4387ccf519593b804d3e8541e8aaf9723a2aedeb
