56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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#ifndef __ADI_H__
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#define __ADI_H__
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#define DCDC_CORE_VAL_ADDR 0x1864
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#define DCDC_CORE_VAL_ADI_CHN 21
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int adi_hwchannel_set(unsigned int chn, unsigned int config);
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void sci_adi_init(void);
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/*
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* sci_get_adie_chip_id - read a-die chip id
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*/
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u32 sci_get_adie_chip_id(void);
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int sci_adi_read(u32 reg);
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/*
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* WARN: the arguments (reg, value) is different from
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* the general __raw_writel(value, reg)
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* For sci_adi_write_fast: if set sync 1, then this function will
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* return until the val have reached hardware.otherwise, just
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* async write(is maybe in software buffer)
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*/
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int sci_adi_write_fast(u32 reg, u16 val, u32 sync);
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int sci_adi_write(u32 reg, u16 or_val, u16 clear_msk);
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static inline int sci_adi_raw_write(u32 reg, u16 val)
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{
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#if defined(CONFIG_FPGA)
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return 0;
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#else
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return sci_adi_write_fast(reg, val, 1);
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#endif /* CONFIG_FPGA */
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}
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static inline int sci_adi_set(u32 reg, u16 bits)
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{
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#if defined(CONFIG_FPGA)
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return 0;
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#else
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return sci_adi_write(reg, bits, 0);
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#endif /* CONFIG_FPGA */
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}
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static inline int sci_adi_clr(u32 reg, u16 bits)
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{
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#if defined(CONFIG_FPGA)
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return 0;
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#else
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return sci_adi_write(reg, 0, bits);
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#endif /* CONFIG_FPGA */
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}
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#endif
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