184 lines
5.2 KiB
Diff
184 lines
5.2 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Codex <[email protected]>
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Date: Wed, 8 Jul 2026 09:25:00 +0800
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Subject: [PATCH] uis7885-2h10: enable 40pin debug functions
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This is a board bring-up patch for the 40-pin header. The existing DTS
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contains device assignments for other boards; release those old consumers
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where they overlap with the new 40-pin mapping.
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Header mapping notes:
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- 40pin TWI3 is AP I2C5 on GPIO175/176.
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- 40pin TWI4 is AP I2C7 on GPIO193/194.
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- 40pin SPI1 is AP SPI0 on GPIO105-108.
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- 40pin SPI1_CS1 has no native SPI0 CS1; use GPIO192 as a software CS.
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- 40pin UART1 uses UART7 pads routed to AP UART0.
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- 40pin UART5 uses UART6 pads routed to AP UART3.
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- 40pin PWM uses the PWMC pad, not PWMA.
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- 40pin pins 16/18 are plain GPIO148/GPIO150, not UART RTS/CTS.
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- 40pin PCM/I2S pads are IIS1 pins routed to AP IIS1 by pinmap; this
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patch does not add an audio sound-card route for them yet.
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Keep the currently validated buses untouched:
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- I2C2 is still used by HDMI.
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- I2C4 is still used by the camera.
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---
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.../linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig | 2 +-
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.../linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts | 66 ++++++++++++++++-
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2 files changed, 60 insertions(+), 6 deletions(-)
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diff --git a/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig b/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig
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index 000000000000..000000000000 100755
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--- a/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig
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+++ b/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig
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@@ -2539,7 +2539,7 @@
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#
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# SPI Protocol Masters
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#
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-# CONFIG_SPI_SPIDEV is not set
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+CONFIG_SPI_SPIDEV=y
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# CONFIG_SPI_LOOPBACK_TEST is not set
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# CONFIG_SPI_TLE62X0 is not set
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# CONFIG_SPI_SLAVE is not set
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diff --git a/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts b/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts
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index 000000000000..000000000000 100755
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--- a/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts
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+++ b/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts
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@@ -426,7 +426,11 @@
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bq2597x_chg: charger@65 {
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compatible = "ti,bq2597x-standalone";
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reg = <0x65>;
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- irq-gpio = <&ap_gpio 193 GPIO_ACTIVE_LOW>;
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+ /*
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+ * GPIO193 is 40pin TWI4_SDA / AP I2C7_SDA.
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+ * Leave it to the 40pin header in debug mode.
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+ */
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+ /* irq-gpio = <&ap_gpio 193 GPIO_ACTIVE_LOW>; */
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ti,bq2597x,bus-therm-disable = <1>;
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ti,bq2597x,regulation-disable = <1>;
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@@ -581,7 +585,11 @@
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&panel {
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sprd,backlight = <&pwm_backlight>;
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- avdd-gpio = <&ap_gpio 192 GPIO_ACTIVE_HIGH>;
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+ /*
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+ * GPIO192 is 40pin SPI1_CS1. SPI0 has no native CS1, so use this
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+ * pad as a software-controlled SPI chip select in debug mode.
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+ */
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+ /* avdd-gpio = <&ap_gpio 192 GPIO_ACTIVE_HIGH>; */
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avee-gpio = <&ap_gpio 191 GPIO_ACTIVE_HIGH>;
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reset-gpio = <&ap_gpio 11 GPIO_ACTIVE_HIGH>;
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};
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@@ -521,7 +529,7 @@
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&pwms {
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pinctrl-names = "default";
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- pinctrl-0 = <&pwm0_pwma>;
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+ pinctrl-0 = <&pwm2_pwmc>;
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status = "okay";
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};
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@@ -799,11 +807,11 @@
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};
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&i2c5 {
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- status = "disabled";
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+ status = "okay";
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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-
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+/*
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sensor_sub2: sensor-sensor_sub2a {
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status = "disabled";
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compatible = "sprd,sensor-sub2";
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@@ -841,6 +849,7 @@
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sprd,phyid = <7>;
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power-domains = <&mm_domain>;
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};
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+*/
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};
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&i2c6 {
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@@ -853,6 +862,7 @@
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compatible = "sprd,flash-ocp8137";
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reg = <0x63>;
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sprd,flash-ic = <8137>;
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+ status = "disabled";
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sprd,torch = <1>;
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sprd,preflash = <1>;
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sprd,highlight = <1>;
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@@ -867,15 +877,55 @@
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};
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};
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+&i2c7 {
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+ status = "okay";
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+ clock-frequency = <400000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&uart3 {
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+ status = "okay";
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+};
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+
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&pdm_dmic {
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status = "okay";
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};
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-&sprd_headset {
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+&spi0 {
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status = "okay";
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+ num-chipselect = <2>;
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+ cs-gpios = <&ap_gpio 105 GPIO_ACTIVE_LOW>,
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+ <&ap_gpio 192 GPIO_ACTIVE_LOW>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ spidev0: spidev@0 {
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+ compatible = "rohm,dh2228fv";
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+ reg = <0>;
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+ spi-max-frequency = <10000000>;
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+ };
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+
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+ spidev1: spidev@1 {
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+ compatible = "rohm,dh2228fv";
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+ reg = <1>;
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+ spi-max-frequency = <10000000>;
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+ };
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+};
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+
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+&sprd_headset {
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+ /*
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+ * GPIO61/GPIO62 are 40pin PG1/PG0 in debug mode. Disable the
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+ * headset GPIO consumers so those lines can be requested as GPIOs.
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+ */
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+ status = "disabled";
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extcon = <&pmic_typec>;
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- mic-gpios = <&ap_gpio 62 GPIO_ACTIVE_HIGH>;
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- lr-gpios = <&ap_gpio 61 GPIO_ACTIVE_HIGH>;
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+ /* mic-gpios = <&ap_gpio 62 GPIO_ACTIVE_HIGH>; */
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+ /* lr-gpios = <&ap_gpio 61 GPIO_ACTIVE_HIGH>; */
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sprd,3pole-adc-threshold = <112>;
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};
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@@ -934,9 +984,9 @@
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function = "func4";
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};
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- pwm0_pwma: pwma {
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- pins = "QOGIRN6PRO_PWMA";
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+ pwm2_pwmc: pwmc {
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+ pins = "QOGIRN6PRO_PWMC";
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function = "func1";
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};
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--
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2.34.1
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