diff --git a/40pin-debug-enable.patch b/40pin-debug-enable.patch deleted file mode 100644 index 06127f8d7..000000000 --- a/40pin-debug-enable.patch +++ /dev/null @@ -1,183 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Codex -Date: Wed, 8 Jul 2026 09:25:00 +0800 -Subject: [PATCH] uis7885-2h10: enable 40pin debug functions - -This is a board bring-up patch for the 40-pin header. The existing DTS -contains device assignments for other boards; release those old consumers -where they overlap with the new 40-pin mapping. - -Header mapping notes: -- 40pin TWI3 is AP I2C5 on GPIO175/176. -- 40pin TWI4 is AP I2C7 on GPIO193/194. -- 40pin SPI1 is AP SPI0 on GPIO105-108. -- 40pin SPI1_CS1 has no native SPI0 CS1; use GPIO192 as a software CS. -- 40pin UART1 uses UART7 pads routed to AP UART0. -- 40pin UART5 uses UART6 pads routed to AP UART3. -- 40pin PWM uses the PWMC pad, not PWMA. -- 40pin pins 16/18 are plain GPIO148/GPIO150, not UART RTS/CTS. -- 40pin PCM/I2S pads are IIS1 pins routed to AP IIS1 by pinmap; this - patch does not add an audio sound-card route for them yet. - -Keep the currently validated buses untouched: -- I2C2 is still used by HDMI. -- I2C4 is still used by the camera. ---- - .../linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig | 2 +- - .../linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts | 66 ++++++++++++++++- - 2 files changed, 60 insertions(+), 6 deletions(-) - -diff --git a/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig b/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig -index 000000000000..000000000000 100755 ---- a/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig -+++ b/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/sprd_uis7885_defconfig -@@ -2539,7 +2539,7 @@ - # - # SPI Protocol Masters - # --# CONFIG_SPI_SPIDEV is not set -+CONFIG_SPI_SPIDEV=y - # CONFIG_SPI_LOOPBACK_TEST is not set - # CONFIG_SPI_TLE62X0 is not set - # CONFIG_SPI_SLAVE is not set -diff --git a/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts b/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -index 000000000000..000000000000 100755 ---- a/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -+++ b/source_sync_rls_25c/layers/meta-unisoc/recipes-kernel/linux/linux-unisoc-5.4/uis7885/uis7885-2h10-overlay.dts -@@ -426,7 +426,11 @@ - bq2597x_chg: charger@65 { - compatible = "ti,bq2597x-standalone"; - reg = <0x65>; -- irq-gpio = <&ap_gpio 193 GPIO_ACTIVE_LOW>; -+ /* -+ * GPIO193 is 40pin TWI4_SDA / AP I2C7_SDA. -+ * Leave it to the 40pin header in debug mode. -+ */ -+ /* irq-gpio = <&ap_gpio 193 GPIO_ACTIVE_LOW>; */ - - ti,bq2597x,bus-therm-disable = <1>; - ti,bq2597x,regulation-disable = <1>; -@@ -581,7 +585,11 @@ - - &panel { - sprd,backlight = <&pwm_backlight>; -- avdd-gpio = <&ap_gpio 192 GPIO_ACTIVE_HIGH>; -+ /* -+ * GPIO192 is 40pin SPI1_CS1. SPI0 has no native CS1, so use this -+ * pad as a software-controlled SPI chip select in debug mode. -+ */ -+ /* avdd-gpio = <&ap_gpio 192 GPIO_ACTIVE_HIGH>; */ - avee-gpio = <&ap_gpio 191 GPIO_ACTIVE_HIGH>; - reset-gpio = <&ap_gpio 11 GPIO_ACTIVE_HIGH>; - }; -@@ -521,7 +529,7 @@ - - &pwms { - pinctrl-names = "default"; -- pinctrl-0 = <&pwm0_pwma>; -+ pinctrl-0 = <&pwm2_pwmc>; - status = "okay"; - }; - -@@ -799,11 +807,11 @@ - }; - - &i2c5 { -- status = "disabled"; -+ status = "okay"; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; -- -+/* - sensor_sub2: sensor-sensor_sub2a { - status = "disabled"; - compatible = "sprd,sensor-sub2"; -@@ -841,6 +849,7 @@ - sprd,phyid = <7>; - power-domains = <&mm_domain>; - }; -+*/ - }; - - &i2c6 { -@@ -853,6 +862,7 @@ - compatible = "sprd,flash-ocp8137"; - reg = <0x63>; - sprd,flash-ic = <8137>; -+ status = "disabled"; - sprd,torch = <1>; - sprd,preflash = <1>; - sprd,highlight = <1>; -@@ -867,15 +877,55 @@ - }; - }; - -+&i2c7 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart3 { -+ status = "okay"; -+}; -+ - &pdm_dmic { - status = "okay"; - }; - --&sprd_headset { -+&spi0 { - status = "okay"; -+ num-chipselect = <2>; -+ cs-gpios = <&ap_gpio 105 GPIO_ACTIVE_LOW>, -+ <&ap_gpio 192 GPIO_ACTIVE_LOW>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ spidev0: spidev@0 { -+ compatible = "rohm,dh2228fv"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ spidev1: spidev@1 { -+ compatible = "rohm,dh2228fv"; -+ reg = <1>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&sprd_headset { -+ /* -+ * GPIO61/GPIO62 are 40pin PG1/PG0 in debug mode. Disable the -+ * headset GPIO consumers so those lines can be requested as GPIOs. -+ */ -+ status = "disabled"; - extcon = <&pmic_typec>; -- mic-gpios = <&ap_gpio 62 GPIO_ACTIVE_HIGH>; -- lr-gpios = <&ap_gpio 61 GPIO_ACTIVE_HIGH>; -+ /* mic-gpios = <&ap_gpio 62 GPIO_ACTIVE_HIGH>; */ -+ /* lr-gpios = <&ap_gpio 61 GPIO_ACTIVE_HIGH>; */ - sprd,3pole-adc-threshold = <112>; - }; - -@@ -934,9 +984,9 @@ - function = "func4"; - }; - -- pwm0_pwma: pwma { -- pins = "QOGIRN6PRO_PWMA"; -+ pwm2_pwmc: pwmc { -+ pins = "QOGIRN6PRO_PWMC"; - function = "func1"; - }; - --- -2.34.1