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= BPI-H618 预编
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:outlinelevels: 3
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用于嵌入式应用的 Banana Pi SBC
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:example-caption!:
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ifndef::imagesdir[:imagesdir: images]
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<<<
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toc::[]
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== 第一章 介绍
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=== 1.1 介绍
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=== 1.2 关键特性
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= Banana Pi Compute Module 4
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:outlinelevels: 3
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A Banana Pi for deeply embedded applica
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:example-caption!:
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ifndef::imagesdir[:imagesdir: images]
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== Colophon
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法律信息及版权信息
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<<<
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toc::[]
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== Chapter 1. Introduction
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=== 1.1 Introduction
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image::BPI-CM4.jpg[scaledwidth=75%, title="The BPI-CM4"]
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The Banana Pi Compute Module 4(CM4)is a System on Module(SoM) containing processor,DRAM, eMMC Flash and supporting power circuitry. These modules allow a designer touse the Banana Pi hardware and software stack in their own custom systems and formfactors. And, These modules offer additional IO interfaces beyond what is provided on Banana Pi boards, providing designers with more options.
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The design of the CM4 is loosely based on the Amlogic A311D, Quad core ARM Cortex-A73 and dual core ARM Cortex-A53 CPU , ARM G52MP4(6EE) GPU,NPU for AI at 5.0 TOPS, support Camera and MIPI-CSI interface ,HDMI output,2 Gigabit port . 4G RAM and 16 GB eMMC flash.
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for A311D chip PIN limited . just support 1 HDMI ,1 CSI and 1 DSI , Raspberry Pi support 2 HDMI ,2 CSI and 2 DSI , Other is Pin2Pin . you can use Raspberry Pi CM4 baseboard.
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NOTE: for A311D chip PIN limited . just support 1 HDMI ,1 CSI and 1 DSI , Raspberry Pi support 2 HDMI ,2 CSI and 2 DSI , Other is Pin2Pin . you can use Raspberry Pi CM4 baseboard.
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<<<
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=== 1.2 Key Feature
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Key feature of the BPI-CM4 are as follows:
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* Amlogic A311D Quad core ARM Cortex-A73 and dual core ARM Cortex-A53,ARM G52 MP4(6EE) GPU
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* NPU for AI Next generation, deep-neural-network applications, at 5.0 TOPS
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* OpenGL ES 3.2, Vulkan 1.1 and OpenCL 2.0 support
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* 4GB LPDDR4 RAM
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* 16GB eMMC flash (Max 128G)
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* MIPI DSI :
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** 1x4-Lane MIPI DSI Display Interface
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* MIPI CSI :
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** 1x4-Lane MIPI CSI Camera Interface
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* PCIe Interface:
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** 1xPCIe 1-Lane Host,Gen 2(5Gbps)
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* HDMI Interface:
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** 1xHDMI 2.1 Output Interface(up tp 4Kx2K@60)
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* Gigabit Ethernet PHY supporting
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* 26 PIN GPIO:
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** 1x PCM
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** 1x IIC
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** 1x UART
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** 1x PWM
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* Single +5V PSU Input
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* Support Android and Linux system
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* Size: 55x40mm
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== Chapter 2. Interfaces
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=== 2.1 Wireless
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The BPI-CM4 supports an onboard wireless module based on Realtek RTL8822CS,supports both
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* 2.4GHz & 5GHz IEEE 802.11 a/b/g/n/ac 2x2 MIMO wireless
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* Bluetooth 5.0 BR/EDR/LE
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These wireless interfaces can be individually enabled or disabled as required via CPU GPIO. In the case of many application environments, a service engineer can enable wireless operation and then disable it when done.
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The CPU can also turn on the wireless by itself for data communication, and turn ff the wireless after completion to reduce power consumption.
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The BPI-CM4 has two standard IPEX-1G connector on the module, If you want to use 2x2 MIMO, need to connect 2x 2.4G&5G antenna.
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Banana Pi Ltd has an antenna kit which is certified to be used with the BPI-CM4. If a different antenna is used then separate certification will be required.
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=== 2.2 Ethernet
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The BPI-CM4 has an onboard Gigabit Ethernet PHY - the https://www.realtek.com/en/products/connected-media-ics/item/rtl8211f-i-cg[REALTEK RTL8211F] - some of the major features of this PHY include;
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* IEEE 802.3az-2010
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* Built-in Wake-on-LAN
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* Crossover Detection & Auto-Correction
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A standard RJ45 connector is necessary to provid an Ethernet connection to the BPI-CM4.Can be see in link:#EthSch[Figure 2]
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[#EthSch]
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image::EthernetSch.jpg[title="Ethernet Schematic", alt=EthSch]
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The differential Ethernet signals should be routed as 100Ω differential pairs, with suitable clearances. Length matching between pairs should be better than 50mm, so in the typical case no length matching is required. However the signals within a pair need to be length matched, ideally to better than 0.15mm.
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The PHY also supports up to 2 LEDs to give user status feedback, these are low active. These LEDs can have a range of functions, and you should consult your OS driver to see which functions are supported by your driver.
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=== 2.3 PCIe(Gen2 x1)
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The BPI-CM4 has an internal PCIe2.0 x1 host controller. Connecting a PCIe device follows the standard PCIe convention.The CM4 has onboard AC coupling capacitors for *PCIe_CLK* and *PCIe_TX* signals.However the *PCIe_RX* signals need external coupling capacitors close to the driving source (the device *TX*), if you are using an external PCIe/NVMe cards these capacitors will be onboard. The PCIe conversion is that if you are wiring directly to an IC then the TX and RX pairs need to be swapped ( ie. TX->RX, RX->TX ). If you are wiring to a connector then this is typically labelled from the host post of view and so TX RX swaps aren’t required. Additionally the *PCIECK_REQN* must be connected to ensure the CM4 produces a clock signal, and the *PERST0_N* should also be connected to ensure the device is correctly reset when required. The differential PCIe signals should be routed as 100Ω differential pairs, with suitable clearances. There is no need to match the lengths between pairs, only the signals within a Pair need to be length matched ideally to better than 0.1mm
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TIP: 5.10 kernel and .......
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=== 2.4 USB 2.0(Highspeed)
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The USB 2.0 interface supports up to 480MBps signalling. The differential pair should be routed as a 90Ω differential pair. The P N signals should ideally be matched to better than 0.15mm.
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<<<
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== Build
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This page was built by the following command:
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$ mvn
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=== Attributes
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.Built-in
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asciidoctor-version:: {asciidoctor-version}
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safe-mode-name:: {safe-mode-name}
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docdir:: {docdir}
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docfile:: {docfile}
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imagesdir:: {imagesdir}
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.Custom
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sourcedir:: {sourcedir}
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== Includes
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WARNING: Includes can be tricky!
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/ModDate (D:20230807153832+08'00')
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/CreationDate (D:20230807154639+08'00')
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>>
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endobj
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2 0 obj
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<< /Type /Catalog
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