542 lines
14 KiB
C
542 lines
14 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
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*/
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#include <linux/bitops.h>
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#include <linux/phy.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/mdio.h>
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#include <linux/timer.h>
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#include <linux/netdevice.h>
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#if IS_ENABLED(CONFIG_AMLOGIC_ETH_PRIVE)
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#include <linux/amlogic/aml_phy_debug.h>
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#endif
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#define MAXIO_PHY_VER "v1.8.1.2"
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#define MAXIO_PAGE_SELECT 0x1f
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#define MAXIO_MAE0621A_WORK_STATUS_REG 0x1d
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#define MAXIO_MAE0621A_CLK_MODE_REG 0x02
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#define MAXIO_PHYSR_P_A43 (0x1a)
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#define MAXIO_PHY_LINK BIT(2)
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#define MAXIO_PHY_DUPLEX BIT(3)
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#define MAXIO_PHY_SPEED (3 << 4)
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#define MAXIO_PHY_1000M (0x20)
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#define MAXIO_PHY_100M (0x10)
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#define MAXIO_PHY_10M (0x00)
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#define AUTONEG_COMPLETED_INT_EN (0x8)
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#define LINKOK (0x4)
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#define AUTONEG_COMPLETED (0x8)
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#define PHY_READ(a, b) phy_read((a), (b))
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#define PHY_WRITE(a, b, c) phy_write((a), (b), (c))
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static int maxio_read_paged(struct phy_device *phydev, int page, u32 regnum)
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{
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int ret = 0, oldpage;
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oldpage = PHY_READ(phydev, MAXIO_PAGE_SELECT);
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if (oldpage >= 0) {
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, page);
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ret = PHY_READ(phydev, regnum);
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}
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, oldpage);
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return ret;
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}
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static int maxio_write_paged(struct phy_device *phydev, int page, u32 regnum, u16 val)
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{
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int ret = 0, oldpage;
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oldpage = PHY_READ(phydev, MAXIO_PAGE_SELECT);
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if (oldpage >= 0) {
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, page);
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ret = PHY_WRITE(phydev, regnum, val);
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}
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, oldpage);
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return ret;
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}
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static int maxio_adcc_check(struct phy_device *phydev)
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{
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int ret = 0;
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int adcvalue;
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u32 regval;
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int i;
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maxio_write_paged(phydev, 0xd96, 0x2, 0x1fff);
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maxio_write_paged(phydev, 0xd96, 0x2, 0x1000);
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for (i = 0; i < 4; i++) {
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regval = 0xf908 + i * 0x100;
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maxio_write_paged(phydev, 0xd8f, 0xb, regval);
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adcvalue = maxio_read_paged(phydev, 0xd92, 0xb);
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if (adcvalue & 0x1ff) {
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continue;
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} else {
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ret = -1;
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break;
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}
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}
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return ret;
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}
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static int maxio_self_check(struct phy_device *phydev, int checknum)
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{
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int ret = 0;
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int i;
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for (i = 0; i < checknum; i++) {
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ret = maxio_adcc_check(phydev);
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if (ret == 0) {
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pr_debug("MAE0621A READY\n");
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break;
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}
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if (ret != 0) {
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maxio_write_paged(phydev, 0x0, 0x0, 0x1940);
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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msleep(20);
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maxio_write_paged(phydev, 0x0, 0x0, 0x1140);
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maxio_write_paged(phydev, 0x0, 0x0, 0x9140);
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}
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}
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maxio_write_paged(phydev, 0xd96, 0x2, 0xfff);
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maxio_write_paged(phydev, 0x0, 0x0, 0x9140);
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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return ret;
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}
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static int maxio_mae0621a_resume(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_resume(phydev);
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ret |= PHY_WRITE(phydev, MII_BMCR, BMCR_RESET | PHY_READ(phydev, MII_BMCR));
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msleep(20);
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return ret;
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}
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static int maxio_mae0621a_suspend(struct phy_device *phydev)
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{
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int ret = 0;
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ret = genphy_suspend(phydev);
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0);
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return ret;
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}
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static int maxio_restart_aneg(struct phy_device *phydev)
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{
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int ctl = PHY_READ(phydev, MII_BMCR);
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if (ctl < 0)
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return ctl;
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ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
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ctl &= ~BMCR_ISOLATE;
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return PHY_WRITE(phydev, MII_BMCR, ctl);
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}
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static void phy_resolve_aneg_linkmode_maxio(struct phy_device *phydev)
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{
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int physr_p_a43 = maxio_read_paged(phydev, 0xa43, MAXIO_PHYSR_P_A43);
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switch (physr_p_a43 & MAXIO_PHY_SPEED) {
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case MAXIO_PHY_1000M:
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phydev->speed = SPEED_1000;
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break;
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case MAXIO_PHY_100M:
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phydev->speed = SPEED_100;
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break;
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case MAXIO_PHY_10M:
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phydev->speed = SPEED_10;
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break;
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}
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if (physr_p_a43 & MAXIO_PHY_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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if (phydev->duplex == DUPLEX_FULL) {
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int lpa = PHY_READ(phydev, MII_LPA);
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phydev->pause = (lpa & LPA_PAUSE_CAP) ? 1 : 0;
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phydev->asym_pause = (lpa & LPA_PAUSE_ASYM) ? 1 : 0;
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}
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}
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static void phy_resolve_link_compatibility_maxio(struct phy_device *phydev)
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{
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int *paras = (int *)phydev->priv;
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int maxio_an_times = paras[0];
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int link_stable = paras[1];
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int iner, physr, insr;
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iner = maxio_read_paged(phydev, 0xa42, 0x12);
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if (iner & AUTONEG_COMPLETED_INT_EN) {
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physr = maxio_read_paged(phydev, 0xa43, 0x1a);
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if (physr & LINKOK) {
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insr = maxio_read_paged(phydev, 0xa43, 0x1d);
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if ((insr & AUTONEG_COMPLETED) == 0 && link_stable == 0) {
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if (maxio_an_times < 4) {
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maxio_restart_aneg(phydev);
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phydev->link = 0;
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maxio_an_times++;
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} else if (maxio_an_times == 4) {
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link_stable = 1;
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}
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} else if (insr & AUTONEG_COMPLETED) {
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maxio_an_times = 0;
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link_stable = 1;
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}
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if (link_stable == 1)
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maxio_an_times = 0;
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} else {
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link_stable = 0;
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}
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}
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paras[0] = maxio_an_times;
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paras[1] = link_stable;
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}
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static int maxio_mae0621a_status(struct phy_device *phydev)
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{
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int err, old_link = phydev->link;
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err = genphy_update_link(phydev);
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if (err)
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return err;
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if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
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return 0;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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phydev->pause = 0;
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phydev->asym_pause = 0;
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phy_resolve_aneg_linkmode_maxio(phydev);
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if (phydev->autoneg == AUTONEG_ENABLE)
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phy_resolve_link_compatibility_maxio(phydev);
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return 0;
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}
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static void maxio_mae0621a_remove(struct phy_device *phydev)
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{
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pr_debug("maxio driver remove\r\n");
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kfree(phydev->priv);
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phydev->priv = NULL;
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}
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static int maxio_mae0621a_config_init(struct phy_device *phydev)
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{
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int ret = 0;
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pr_debug("MAXIO_PHY_VER: %s\n", MAXIO_PHY_VER);
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ret |= maxio_write_paged(phydev, 0xda0, 0x10, 0xc13);
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ret |= maxio_write_paged(phydev, 0x0, 0xd, 0x7);
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ret |= maxio_write_paged(phydev, 0x0, 0xe, 0x3c);
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ret |= maxio_write_paged(phydev, 0x0, 0xd, 0x4007);
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ret |= maxio_write_paged(phydev, 0x0, 0xe, 0x0);
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ret |= maxio_write_paged(phydev, 0xd96, 0x13, 0x7bc);
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ret |= maxio_write_paged(phydev, 0xd8f, 0x8, 0x2500);
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ret |= maxio_write_paged(phydev, 0xd90, 0x2, 0x1555);
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ret |= maxio_write_paged(phydev, 0xd90, 0x5, 0x2b15);
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ret |= maxio_write_paged(phydev, 0xd92, 0x14, 0xa);
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ret |= maxio_write_paged(phydev, 0xd91, 0x7, 0x5b00);
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ret |= maxio_write_paged(phydev, 0xd8f, 0x0, 0x300);
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ret |= maxio_write_paged(phydev, 0xd92, 0xa, 0x8506);
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ret |= maxio_write_paged(phydev, 0xd91, 0x6, 0x6870);
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ret |= maxio_write_paged(phydev, 0xd91, 0x1, 0x940);
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ret |= maxio_write_paged(phydev, 0xda0, 0x13, 0x1303);
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ret |= maxio_write_paged(phydev, 0xd97, 0xc, 0x177);
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ret |= maxio_write_paged(phydev, 0xd97, 0xb, 0x9a9);
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ret |= maxio_write_paged(phydev, 0xa42, 0x12, 0x28);
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ret |= maxio_write_paged(phydev, 0x0, 0x4, 0xde1);
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ret |= maxio_write_paged(phydev, 0x0, 0x0, 0x9140);
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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ret |= maxio_self_check(phydev, 50);
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msleep(100);
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return 0;
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}
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static int maxio_mae0621a_probe(struct phy_device *phydev)
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{
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int *paras;
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paras = kzalloc(2 * sizeof(int), GFP_KERNEL);
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if (!paras)
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return -ENOMEM;
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phydev->priv = paras;
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pr_debug("%s: clkmode(oscillator) PHY_ID: 0x%x\n", __func__, phydev->phy_id);
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PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0x0);
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mdelay(100);
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return 0;
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}
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static int maxio_mae0621aq3ci_probe(struct phy_device *phydev)
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{
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int *paras;
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paras = kzalloc(2 * sizeof(int), GFP_KERNEL);
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if (!paras)
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return -ENOMEM;
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phydev->priv = paras;
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pr_debug("maxio_mae0621aQ3C probe PHY_ID: 0x%x\n", phydev->phy_id);
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return 0;
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}
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static int maxio_mae0621aq3ci_config_init(struct phy_device *phydev)
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{
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int ret = 0;
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pr_debug("MAXIO_PHY_VER: %s\n", MAXIO_PHY_VER);
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ret |= maxio_write_paged(phydev, 0xa43, 0x19, 0x823);
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ret |= maxio_write_paged(phydev, 0xdab, 0x17, 0xC13);
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ret |= maxio_write_paged(phydev, 0xd96, 0x15, 0xc08a);
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ret |= maxio_write_paged(phydev, 0xda4, 0x12, 0x7bc);
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ret |= maxio_write_paged(phydev, 0xd8f, 0x16, 0x2500);
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ret |= maxio_write_paged(phydev, 0xd90, 0x16, 0x1555);
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ret |= maxio_write_paged(phydev, 0xd92, 0x11, 0x2b15);
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ret |= maxio_write_paged(phydev, 0xd96, 0x16, 0x4010);
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ret |= maxio_write_paged(phydev, 0xda5, 0x11, 0x4a12);
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ret |= maxio_write_paged(phydev, 0xda5, 0x12, 0x4a12);
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ret |= maxio_write_paged(phydev, 0xd99, 0x16, 0xa);
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ret |= maxio_write_paged(phydev, 0xd95, 0x13, 0x5b00);
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ret |= maxio_write_paged(phydev, 0xd8f, 0x10, 0x300);
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ret |= maxio_write_paged(phydev, 0xd98, 0x17, 0x8506);
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ret |= maxio_write_paged(phydev, 0xd95, 0x12, 0x6870);
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ret |= maxio_write_paged(phydev, 0xd93, 0x15, 0x940);
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ret |= maxio_write_paged(phydev, 0xdad, 0x12, 0x1303);
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ret |= maxio_write_paged(phydev, 0xda8, 0x11, 0x177);
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ret |= maxio_write_paged(phydev, 0xda8, 0x10, 0x9a9);
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ret |= maxio_write_paged(phydev, 0xa42, 0x12, 0x28);
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ret |= maxio_write_paged(phydev, 0x0, 0x4, 0xde1);
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ret |= maxio_write_paged(phydev, 0x0, 0x0, 0x9140);
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0);
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return 0;
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}
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int maxio_mae0621aq3ci_resume(struct phy_device *phydev)
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{
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int ret = 0;
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ret = genphy_resume(phydev);
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ret |= maxio_write_paged(phydev, 0xdaa, 0x17, 0x1001);
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ret |= maxio_write_paged(phydev, 0xdab, 0x15, 0x0);
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0);
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return ret;
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}
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int maxio_mae0621aq3ci_suspend(struct phy_device *phydev)
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{
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int ret = 0;
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ret = maxio_write_paged(phydev, 0xdaa, 0x17, 0x1011);
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ret |= maxio_write_paged(phydev, 0xdab, 0x15, 0x5550);
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0);
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ret |= genphy_suspend(phydev);
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ret |= PHY_WRITE(phydev, MAXIO_PAGE_SELECT, 0);
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return ret;
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}
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#if IS_ENABLED(CONFIG_AMLOGIC_ETH_PRIVE)
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#define SUPPORT_PMEB_WOL
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int mae0621a_suspend(struct phy_device *phydev)
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{
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int value = 0;
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struct aml_eth_priv *eth_priv = aml_get_eth_priv_by_pdev(phydev);
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#if IS_ENABLED(CONFIG_AMLOGIC_WOL)
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/* When a wake source exists, the PHY must remain in working state. */
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if (eth_priv->wol_ready)
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return 0;
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#endif
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if (eth_priv->support_gpio_wol) {
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mutex_lock(&phydev->lock);
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/* config mac address for wol */
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if (phydev->attached_dev) {
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phy_write(phydev, MAXIO_PAGE_SELECT, 0xd8c);
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if (eth_priv->exphy_mdns_wkup) {
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/* multicast: 01:00:5e:00:00:fb */
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phy_write(phydev, 0x10, 0x0001);
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phy_write(phydev, 0x11, 0x005e);
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phy_write(phydev, 0x12, 0xfb00);
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} else {
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phy_write(phydev, 0x10, phydev->attached_dev->dev_addr[0] |
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(phydev->attached_dev->dev_addr[1] << 8));
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phy_write(phydev, 0x11, phydev->attached_dev->dev_addr[2] |
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(phydev->attached_dev->dev_addr[3] << 8));
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phy_write(phydev, 0x12, phydev->attached_dev->dev_addr[4] |
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(phydev->attached_dev->dev_addr[5] << 8));
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}
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}
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if (eth_priv->exphy_mdns_wkup) {
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phy_write(phydev, MAXIO_PAGE_SELECT, 0xd8a);
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/* set max packet length */
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phy_write(phydev, 0x11, 0x9fff);
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/* enable wakeup frame 0 event */
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phy_write(phydev, 0x10, 0x0001);
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phy_write(phydev, MAXIO_PAGE_SELECT, 0xd80);
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phy_write(phydev, 0x10, 0x0000);
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phy_write(phydev, 0x11, 0x0080);
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phy_write(phydev, 0x12, 0x103c);
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phy_write(phydev, 0x13, 0x0000);
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x15, 0x0000);
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phy_write(phydev, 0x16, 0x0000);
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phy_write(phydev, 0x17, 0x0000);
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/* set wakeup frame 0 crc */
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phy_write(phydev, MAXIO_PAGE_SELECT, 0xd88);
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phy_write(phydev, 0x10, 0xe442);
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/* pad isolation */
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phy_write(phydev, MAXIO_PAGE_SELECT, 0xd8a);
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} else {
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phy_write(phydev, MAXIO_PAGE_SELECT, 0xd8a);
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/* enable magic packet event */
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phy_write(phydev, 0x10, 0x1000);
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/* set max packet length */
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phy_write(phydev, 0x11, 0x9fff);
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}
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#ifdef SUPPORT_PMEB_WOL
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/* enable pulse low and set pulse width 84ms */
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phy_write(phydev, 0x13, 0x1);
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#endif
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/* select PMEB/INTB Pin */
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#ifdef SUPPORT_PMEB_WOL
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phy_write(phydev, MAXIO_PAGE_SELECT, 0xd40);
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value = phy_read(phydev, 0x16);
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phy_write(phydev, 0x16, value | (0x1 << 5)); // select PMEB mode
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#else
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phy_write(phydev, MAXIO_PAGE_SELECT, 0xa42);
|
|
value = phy_read(phydev, 0x12);
|
|
phy_write(phydev, 0x12, value | (0x1 << 7)); // enable PME interrupt
|
|
#endif
|
|
phy_write(phydev, MAXIO_PAGE_SELECT, 0);
|
|
|
|
mutex_unlock(&phydev->lock);
|
|
} else {
|
|
// genphy_suspend(phydev);
|
|
maxio_mae0621aq3ci_suspend(phydev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mae0621a_resume(struct phy_device *phydev)
|
|
{
|
|
struct aml_eth_priv *eth_priv = aml_get_eth_priv_by_pdev(phydev);
|
|
#if IS_ENABLED(CONFIG_AMLOGIC_WOL)
|
|
if (eth_priv->wol_ready)
|
|
return 0;
|
|
#endif
|
|
|
|
if (eth_priv->support_gpio_wol) {
|
|
phy_write(phydev, MAXIO_PAGE_SELECT, 0xd8a);
|
|
|
|
// mutex_lock(&phydev->lock);
|
|
/* disable wol */
|
|
phy_write(phydev, 0x10, 0x0);
|
|
/* reset wol */
|
|
phy_write(phydev, 0x11, 0x0);
|
|
#ifdef SUPPORT_PMEB_WOL
|
|
/* disable pulse low */
|
|
phy_write(phydev, 0x13, 0x2);
|
|
#else
|
|
/* read wol interrupt */
|
|
phy_write(phydev, MAXIO_PAGE_SELECT, 0xa43);
|
|
phy_read(phydev, 0x1d);
|
|
#endif
|
|
|
|
phy_write(phydev, MAXIO_PAGE_SELECT, 0);
|
|
// mutex_unlock(&phydev->lock);
|
|
pr_debug("%s %d\n", __func__, __LINE__);
|
|
} else {
|
|
// genphy_resume(phydev);
|
|
maxio_mae0621aq3ci_resume(phydev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static struct phy_driver maxio_nc_drvs[] = {
|
|
{
|
|
.phy_id = 0x7b744411,
|
|
.phy_id_mask = 0x7fffffff,
|
|
.name = "MAE0621A-Q2C Gigabit Ethernet",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.probe = maxio_mae0621a_probe,
|
|
.config_init = maxio_mae0621a_config_init,
|
|
.config_aneg = &genphy_config_aneg,
|
|
.read_status = maxio_mae0621a_status,
|
|
.suspend = maxio_mae0621a_suspend,
|
|
.resume = maxio_mae0621a_resume,
|
|
.remove = maxio_mae0621a_remove,
|
|
},
|
|
{
|
|
.phy_id = 0x7b744412,
|
|
.phy_id_mask = 0x7fffffff,
|
|
.name = "MAE0621A/B-Q3C(I) Gigabit Ethernet",
|
|
.features = PHY_GBIT_FEATURES,
|
|
.probe = maxio_mae0621aq3ci_probe,
|
|
.config_aneg = &genphy_config_aneg,
|
|
.config_init = maxio_mae0621aq3ci_config_init,
|
|
.read_status = &maxio_mae0621a_status,
|
|
#if IS_ENABLED(CONFIG_AMLOGIC_ETH_PRIVE)
|
|
.suspend = mae0621a_suspend,
|
|
.resume = mae0621a_resume,
|
|
#else
|
|
.suspend = maxio_mae0621aq3ci_suspend,
|
|
.resume = maxio_mae0621aq3ci_resume,
|
|
#endif
|
|
.remove = maxio_mae0621a_remove,
|
|
},
|
|
};
|
|
|
|
module_phy_driver(maxio_nc_drvs);
|
|
static struct mdio_device_id __maybe_unused maxio_nc_tbl[] = {
|
|
{ 0x7b744411, 0x7fffffff },
|
|
{ 0x7b744412, 0x7fffffff },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, maxio_nc_tbl);
|
|
|
|
MODULE_DESCRIPTION("Maxio PHY driver");
|
|
MODULE_AUTHOR("Zhao Yang");
|
|
MODULE_LICENSE("GPL");
|