96 lines
3.4 KiB
C
96 lines
3.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __A1_H
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#define __A1_H
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/*
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* Clock controller register address
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* APB_BASE: APB0_BASE_ADDR = 0xfe000800
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*/
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#define SYS_OSCIN_CTRL 0x0
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#define RTC_BY_OSCIN_CTRL0 0x4
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#define RTC_BY_OSCIN_CTRL1 0x8
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#define RTC_CTRL 0xc
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#define SYS_CLK_CTRL0 0x10
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#define AXI_CLK_CTRL0 0x14
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#define SYS_CLK_EN0 0x1c
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#define SYS_CLK_EN1 0x20
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#define AXI_CLK_EN 0x24
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#define DSPA_CLK_EN 0x28
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#define DSPB_CLK_EN 0x2c
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#define DSPA_CLK_CTRL0 0x30
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#define DSPB_CLK_CTRL0 0x34
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#define CLK12_24_CTRL 0x38
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#define GEN_CLK_CTRL 0x3c
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#define TIMESTAMP_CTRL0 0x40
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#define TIMESTAMP_CTRL1 0x44
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#define TIMESTAMP_CTRL2 0x48
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#define TIMESTAMP_VAL0 0x4c
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#define TIMESTAMP_VAL1 0x50
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#define TIMEBASE_CTRL0 0x54
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#define TIMEBASE_CTRL1 0x58
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#define SAR_ADC_CLK_CTRL 0xc0
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#define PWM_CLK_AB_CTRL 0xc4
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#define PWM_CLK_CD_CTRL 0xc8
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#define PWM_CLK_EF_CTRL 0xcc
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#define SPICC_CLK_CTRL 0xd0
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#define TS_CLK_CTRL 0xd4
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#define SPIFC_CLK_CTRL 0xd8
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#define USB_BUSCLK_CTRL 0xdc
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#define SD_EMMC_CLK_CTRL 0xe0
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#define CECA_CLK_CTRL0 0xe4
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#define CECA_CLK_CTRL1 0xe8
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#define CECB_CLK_CTRL0 0xec
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#define CECB_CLK_CTRL1 0xf0
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#define PSRAM_CLK_CTRL 0xf4
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#define DMC_CLK_CTRL 0xf8
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#define FCLK_DIV1_SEL 0xfc
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#define TST_CTRL 0x100
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/*
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* For PLl register offset
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* APB_BASE: APB0_BASE_ADDR = 0xfe007c00
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*/
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#define ANACTRL_FIXPLL_CTRL0 0x80
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#define ANACTRL_FIXPLL_CTRL1 0x84
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#define ANACTRL_FIXPLL_CTRL2 0x88
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#define ANACTRL_FIXPLL_CTRL3 0x8c
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#define ANACTRL_FIXPLL_CTRL4 0x90
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#define ANACTRL_FIXPLL_STS 0x94
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#define ANACTRL_SYSPLL_CTRL0 0x100
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#define ANACTRL_SYSPLL_CTRL1 0x104
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#define ANACTRL_SYSPLL_CTRL2 0x108
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#define ANACTRL_SYSPLL_CTRL3 0x10c
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#define ANACTRL_SYSPLL_CTRL4 0x110
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#define ANACTRL_SYSPLL_STS 0x114
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#define ANACTRL_HIFIPLL_CTRL0 0x140
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#define ANACTRL_HIFIPLL_CTRL1 0x144
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#define ANACTRL_HIFIPLL_CTRL2 0x148
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#define ANACTRL_HIFIPLL_CTRL3 0x14c
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#define ANACTRL_HIFIPLL_CTRL4 0x150
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#define ANACTRL_HIFIPLL_STS 0x154
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#define ANACTRL_AUDDDS_CTRL0 0x180
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#define ANACTRL_AUDDDS_CTRL1 0x184
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#define ANACTRL_AUDDDS_CTRL2 0x188
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#define ANACTRL_AUDDDS_CTRL3 0x18c
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#define ANACTRL_AUDDDS_CTRL4 0x190
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#define ANACTRL_AUDDDS_STS 0x194
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#define ANACTRL_MISCTOP_CTRL0 0x1c0
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#define ANACTRL_POR_CNTL 0x208
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/*
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* CPU clok register offset
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* APB_BASE: APB1_BASE_ADDR = 0xfd000000
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*/
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#define CPUCTRL_CLK_CTRL0 0x80
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#define CPUCTRL_CLK_CTRL1 0x84
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#include <dt-bindings/clock/amlogic,a1-clkc.h>
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#define NR_CLKS (BASIC_BASE2 + 20)
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#endif /* __A1_H */
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