347 lines
13 KiB
C
347 lines
13 KiB
C
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*
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* This source code is subject to the terms and conditions defined in below
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* which is part of this source code package.
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*
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* Description:
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*/
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// Copyright (C) 2019 Amlogic, Inc. All rights reserved.
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//
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// All information contained herein is Amlogic confidential.
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//
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// This software is provided to you pursuant to Software License
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// Agreement (SLA) with Amlogic Inc ("Amlogic"). This software may be
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// used only in accordance with the terms of this agreement.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification is strictly prohibited without prior written permission
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// from Amlogic.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef _VDI_H_
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#define _VDI_H_
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#include "vpuconfig.h"
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#include "vputypes.h"
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/************************************************************************/
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/* COMMON REGISTERS */
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/************************************************************************/
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#define VPU_PRODUCT_NAME_REGISTER 0x1040
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#define VPU_PRODUCT_CODE_REGISTER 0x1044
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#define SUPPORT_MULTI_CORE_IN_ONE_DRIVER
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#define MAX_VPU_CORE_NUM MAX_NUM_VPU_CORE
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#ifndef __ANDROID__
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/*
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* Fixed for glibc2.33
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* error: The futex facility returned an unexpected error code.
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*
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*/
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#define AML_FIXED_FOR_GLIBC_2_33
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#define VPU_SHARED_FILE_NAME "/tmp/vpu_mutex.map"
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#define VPU_SHARED_FILE_SIZE 4096
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#endif
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#define MAX_VPU_BUFFER_POOL (1000)
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#define VpuWriteReg( CORE, ADDR, DATA ) vdi_write_register( CORE, ADDR, DATA ) // system register write
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#define VpuReadReg( CORE, ADDR ) vdi_read_register( CORE, ADDR ) // system register read
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#define VpuWriteMem( CORE, ADDR, DATA, LEN, ENDIAN ) vdi_write_memory( CORE, ADDR, DATA, LEN, ENDIAN ) // system memory write
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#define VpuReadMem( CORE, ADDR, DATA, LEN, ENDIAN ) vdi_read_memory( CORE, ADDR, DATA, LEN, ENDIAN ) // system memory read
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typedef Uint32 u32;
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typedef Int32 s32;
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typedef unsigned long ulong;
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typedef Int16 s16;
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typedef Uint16 u16;
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typedef Uint8 u8;
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typedef Int8 s8;
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typedef struct vpu_bit_firmware_info_t {
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u32 size; /* size of this structure*/
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u32 core_idx;
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u32 reg_base_offset;
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u16 bit_code[512];
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} vpu_bit_firmware_info_t;
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typedef struct vpudrv_inst_info_t {
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u32 core_idx;
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u32 inst_idx;
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s32 inst_open_count; /* for output only*/
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} vpudrv_inst_info_t;
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typedef struct vpudrv_intr_info_t {
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u32 timeout;
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s32 intr_reason;
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s32 intr_inst_index;
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} vpudrv_intr_info_t;
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typedef struct vpu_buffer_t {
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u32 size;
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u32 cached;
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PhysicalAddress phys_addr;
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ulong base;
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ulong virt_addr;
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} vpu_buffer_t;
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typedef struct vpu_dma_buf_info_t {
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u32 num_planes;
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int fd[3];
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ulong phys_addr[3]; /* phys address for DMA buffer */
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} vpu_dma_buf_info_t;
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//hoan add for canvas
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typedef struct vpu_dma_buf_canvas_info_t {
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u32 num_planes;
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u32 canvas_index;
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int fd[3];
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ulong phys_addr[3]; /* phys address for DMA buffer */
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} vpu_dma_buf_canvas_info_t;
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//end
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struct vpudrv_inst_param_t {
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u32 core_idx;
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u32 inst_idx;
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u32 stream_type; /*Unkonw:0, H264: 264, H265: 265*/
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int picWidth;
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int picHeight;
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int profile; /* encoding profile: 0 auto (H.264 high, H.265 main profile) */
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/* H.264 1: baseline 2: Main, 3 High profile*/
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int streamBufSize; /* the encoded bitstream buffer size in MB (range 1-32)*/
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/* 0: use the default value 2MB */
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int frameRateInfo;
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int intraPeriod; /*A period of intra picture in GOP size */
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int gopOption; /*:0 (default), 1:I only 2:IP, 3: IBBBP, 4: IP_SVC1, 5:IP_SVC2*/
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/* 6: IP_SVC3, 7: IP_SVC4, 8:CustP*/
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u32 rcMode; /*CBR:0, VBR: 1*/
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int bitRate; /*target bit rate in kbps*/
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int minQpI; /*A minimum QP of I picture for rate control */
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int maxQpI; /*A maximum QP of I picture for rate control */
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int minQpP; /*A minimum QP of P picture for rate control */
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int maxQpP; /*A maximum QP of P picture for rate control */
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int minQpB; /*A minimum QP of B picture for rate control */
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int maxQpB; /*A maximum QP of B picture for rate control */
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int maxDeltaQp; /*A maximum delta QP for HVS */
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int independSliceMode; /*A slice mode for independent slice 0 : no multi-slice*/
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/*1 : slice in MB(CTU) number*/
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int independSliceModeArg; /*The number of CTU for a slice when independSliceMode */
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/*is set with 1 */
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int dependSliceMode; /*A slice mode for independent slice (for HEVC only)*/
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/*0 : no multi-slice 1 : slice in CTU number */
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/*2 : slice in number of byte*/
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int dependSliceModeArg; /*The number of CTU or bytes for a slice when*/
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/*dependSliceMode is set with 1 or 2*/
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int intraRefreshMode; /*refresh mode select */
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/*0: no refresh, 1:row 2:column, 3: step size in MB(CTU)*/
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/*4 (for HEVC only): Adaptive intra refresh */
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int IntraRefreshArg; /*The number of consecutive MB(CTU) rows(row mode),The*/
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/*number of consecutive MB(CTU) columns(column mode), */
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/*A step size in MB(CTU) (step size mode),The* number*/
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/* The number of Intra CTUs to be encoded in a picture*/
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/*(Adaptive mode)*/
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int custQpDelta;
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};
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#define VPUDRV_BUF_LEN vpu_buffer_t
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#define VPUDRV_INST_LEN vpudrv_inst_info_t
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#define VPUDRV_DMABUF_LEN vpu_dma_buf_info_t
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//hoan add for canvas
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#define VPUDRV_DMABUF_CANVAS_LEN vpu_dma_buf_canvas_info_t
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//end
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#define VPUDRV_INST_PARAM_LEN struct vpudrv_inst_param_t
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#define VDI_MAGIC 'V'
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#define VDI_IOCTL_ALLOCATE_PHYSICAL_MEMORY \
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_IOW(VDI_MAGIC, 0, VPUDRV_BUF_LEN)
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#define VDI_IOCTL_FREE_PHYSICALMEMORY \
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_IOW(VDI_MAGIC, 1, VPUDRV_BUF_LEN)
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#define VDI_IOCTL_WAIT_INTERRUPT \
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_IOW(VDI_MAGIC, 2, vpudrv_intr_info_t)
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#define VDI_IOCTL_SET_CLOCK_GATE \
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_IOW(VDI_MAGIC, 3, u32)
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#define VDI_IOCTL_RESET \
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_IOW(VDI_MAGIC, 4, u32)
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#define VDI_IOCTL_GET_INSTANCE_POOL \
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_IOW(VDI_MAGIC, 5, VPUDRV_BUF_LEN)
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#define VDI_IOCTL_GET_COMMON_MEMORY \
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_IOW(VDI_MAGIC, 6, VPUDRV_BUF_LEN)
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#define VDI_IOCTL_GET_RESERVED_VIDEO_MEMORY_INFO \
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_IOW(VDI_MAGIC, 8, VPUDRV_BUF_LEN)
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#define VDI_IOCTL_OPEN_INSTANCE \
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_IOW(VDI_MAGIC, 9, VPUDRV_INST_LEN)
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#define VDI_IOCTL_CLOSE_INSTANCE \
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_IOW(VDI_MAGIC, 10, VPUDRV_INST_LEN)
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#define VDI_IOCTL_GET_INSTANCE_NUM \
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_IOW(VDI_MAGIC, 11, VPUDRV_INST_LEN)
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#define VDI_IOCTL_GET_REGISTER_INFO \
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_IOW(VDI_MAGIC, 12, VPUDRV_BUF_LEN)
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#define VDI_IOCTL_GET_FREE_MEM_SIZE \
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_IOW(VDI_MAGIC, 13, u32)
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#define VDI_IOCTL_FLUSH_BUFFER \
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_IOW(VDI_MAGIC, 14, VPUDRV_BUF_LEN)
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#define VDI_IOCTL_CACHE_INV_BUFFER \
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_IOW(VDI_MAGIC, 15, VPUDRV_BUF_LEN)
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#define VDI_IOCTL_CONFIG_DMA \
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_IOW(VDI_MAGIC, 16, VPUDRV_DMABUF_LEN)
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#define VDI_IOCTL_UNMAP_DMA \
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_IOW(VDI_MAGIC, 17, VPUDRV_DMABUF_LEN)
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#define VDI_IOCTL_SYNC_INSTANCE_PARAM \
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_IOW(VDI_MAGIC, 18, VPUDRV_INST_PARAM_LEN)
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//hoan add for canvas
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#define VDI_IOCTL_READ_CANVAS \
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_IOW(VDI_MAGIC, 20, VPUDRV_DMABUF_CANVAS_LEN)
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//end
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typedef enum {
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VDI_LITTLE_ENDIAN = 0, /* 64bit LE */
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VDI_BIG_ENDIAN, /* 64bit BE */
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VDI_32BIT_LITTLE_ENDIAN,
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VDI_32BIT_BIG_ENDIAN,
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/* VPU PRODUCTS */
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VDI_128BIT_LITTLE_ENDIAN = 16,
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VDI_128BIT_LE_BYTE_SWAP,
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VDI_128BIT_LE_WORD_SWAP,
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VDI_128BIT_LE_WORD_BYTE_SWAP,
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VDI_128BIT_LE_DWORD_SWAP,
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VDI_128BIT_LE_DWORD_BYTE_SWAP,
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VDI_128BIT_LE_DWORD_WORD_SWAP,
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VDI_128BIT_LE_DWORD_WORD_BYTE_SWAP,
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VDI_128BIT_BE_DWORD_WORD_BYTE_SWAP,
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VDI_128BIT_BE_DWORD_WORD_SWAP,
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VDI_128BIT_BE_DWORD_BYTE_SWAP,
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VDI_128BIT_BE_DWORD_SWAP,
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VDI_128BIT_BE_WORD_BYTE_SWAP,
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VDI_128BIT_BE_WORD_SWAP,
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VDI_128BIT_BE_BYTE_SWAP,
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VDI_128BIT_BIG_ENDIAN = 31,
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VDI_ENDIAN_MAX
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} EndianMode;
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#define VDI_128BIT_ENDIAN_MASK 0xf
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typedef struct vpu_instance_pool_t {
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/* Since VDI don't know the size of CodecInst structure, VDI should have
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the enough space not to overflow. */
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u8 codecInstPool[MAX_NUM_INSTANCE][MAX_INST_HANDLE_SIZE];
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vpu_buffer_t vpu_common_buffer;
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u32 vpu_instance_num;
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u8 instance_pool_inited;
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void* pendingInst;
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u32 pendingInstIdxPlus1;
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u32 lastPerformanceCycles;
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} vpu_instance_pool_t;
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#if defined (__cplusplus)
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extern "C" {
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#endif
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int vdi_probe(u32 core_idx);
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int vdi_init(u32 core_idx);
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int vdi_release(u32 core_idx); //this function may be called only at system off.
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vpu_instance_pool_t * vdi_get_instance_pool(u32 core_idx);
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int vdi_allocate_common_memory(u32 core_idx);
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int vdi_get_common_memory(u32 core_idx, vpu_buffer_t *vb);
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int vdi_allocate_dma_memory(u32 core_idx, vpu_buffer_t *vb, int memTypes, int instIndex);
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int vdi_attach_dma_memory(u32 core_idx, vpu_buffer_t *vb);
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void vdi_free_dma_memory(u32 core_idx, vpu_buffer_t *vb, int memTypes, int instIndex);
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int vdi_get_sram_memory(u32 core_idx, vpu_buffer_t *vb);
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int vdi_dettach_dma_memory(u32 core_idx, vpu_buffer_t *vb);
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int vdi_flush_memory(u32 core_idx, vpu_buffer_t *vb);
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int vdi_invalidate_memory(u32 core_idx, vpu_buffer_t *vb);
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int vdi_config_dma(u32 core_idx, vpu_dma_buf_info_t *info);
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int vdi_unmap_dma(u32 core_idx, vpu_dma_buf_info_t *info);
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int vdi_wait_interrupt(u32 coreIdx, u32 instIdx, int timeout);
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int vdi_wait_vpu_busy(u32 core_idx, int timeout, unsigned int addr_bit_busy_flag);
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int vdi_wait_vcpu_bus_busy(u32 core_idx, int timeout, unsigned int addr_bit_busy_flag);
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int vdi_wait_bus_busy(u32 core_idx, int timeout, unsigned int gdi_busy_flag);
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int vdi_hw_reset(u32 core_idx);
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int vdi_set_clock_gate(u32 core_idx, int enable);
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int vdi_get_clock_gate(u32 core_idx);
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/**
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* @brief make clock stable before changing clock frequency
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* @detail Before inoking vdi_set_clock_freg() caller MUST invoke vdi_ready_change_clock() function.
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* after changing clock frequency caller also invoke vdi_done_change_clock() function.
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* @return 0 failure
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* 1 success
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*/
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int vdi_ready_change_clock(u32 core_idx);
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int vdi_set_change_clock(u32 core_idx, unsigned long clock_mask);
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int vdi_done_change_clock(u32 core_idx);
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u32 vdi_get_instance_num(u32 core_idx);
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void vdi_write_register(u32 core_idx, unsigned int addr, unsigned int data);
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unsigned int vdi_read_register(u32 core_idx, unsigned int addr);
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void vdi_fio_write_register(u32 core_idx, unsigned int addr, unsigned int data);
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unsigned int vdi_fio_read_register(u32 core_idx, unsigned int addr);
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int vdi_clear_memory(u32 core_idx, PhysicalAddress addr, int len, int endian);
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int vdi_set_memory(u32 core_idx, PhysicalAddress addr, int len, int endian, Uint32 data);
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int vdi_write_memory(u32 core_idx, PhysicalAddress addr, unsigned char *data, int len, int endian);
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int vdi_read_memory(u32 core_idx, PhysicalAddress addr, unsigned char *data, int len, int endian);
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int vdi_lock(u32 core_idx);
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void vdi_unlock(u32 core_idx);
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int vdi_disp_lock(u32 core_idx);
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void vdi_disp_unlock(u32 core_idx);
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int vdi_open_instance(u32 core_idx, u32 inst_idx);
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int vdi_close_instance(u32 core_idx, u32 inst_idx);
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int vdi_set_bit_firmware_to_pm(u32 core_idx, const u16 *code);
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int vdi_get_system_endian(u32 core_idx);
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int vdi_convert_endian(u32 core_idx, unsigned int endian);
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int vdi_sys_sync_inst_param(struct vpudrv_inst_param_t *pvip);
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int vdi_config_dma_canvas(u32 core_idx, vpu_dma_buf_canvas_info_t *info);
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#if defined(SUPPORT_SW_UART) || defined(SUPPORT_SW_UART_V2)
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int vdi_get_task_num(u32 core_idx);
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#endif
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#if defined (__cplusplus)
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}
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#endif
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#endif//#ifndef _VDI_H_
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