72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _CLK_PLL_H
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#define _CLK_PLL_H
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#include <clk.h>
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/* PLL Parameters */
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struct pll_parm {
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u16 reg_off;
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u8 shift;
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u8 width;
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};
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struct pll_params_table {
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unsigned long rate;
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unsigned int m;
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unsigned int n;
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unsigned int od;
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unsigned int frac;
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};
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struct reg_sequence {
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unsigned int reg_off;
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unsigned int def;
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unsigned int delay_us;
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};
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#define CLK_AML_PLL_ROUND_CLOSEST BIT(0)
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#define CLK_AML_PLL_NOINIT_ENABLED BIT(1)
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#define CLK_AML_PLL_FIXED_FRAC_WEIGHT_PRECISION BIT(2)
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#define CLK_AML_PLL_POWER_OF_TWO BIT(3)
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#define CLK_AML_PLL_FIXED_N BIT(4)
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#define CLK_AML_PLL_FIXED_EN0P5 BIT(5)
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#define CLK_AML_PLL_RSTN BIT(6)
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#define CLK_AML_PLL_L_RSTN BIT(7)
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struct aml_pll_data {
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struct pll_parm en;
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struct pll_parm l;
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struct pll_parm rst;
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struct pll_parm l_rst;
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struct pll_parm m;
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struct pll_parm n;
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struct pll_parm frac;
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struct pll_parm od;
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const struct reg_sequence *init_regs;
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unsigned int init_count;
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const struct pll_params_table *table;
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unsigned int table_count;
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unsigned int flags;
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};
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/* PLL Structure */
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struct aml_pll {
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struct clk clk;
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void __iomem *addr;
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const struct aml_pll_data *data;
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// unsigned int parent_index;
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};
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extern const struct clk_ops clk_pll_ops;
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struct clk *aml_clk_register_pll(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *addr,
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const struct aml_pll_data *data);
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#endif
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