97 lines
2.8 KiB
Diff
97 lines
2.8 KiB
Diff
From 698bf35ed797f2a9ffdbeea5e83ea4ad7ed5a7b2 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <[email protected]>
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Date: Wed, 2 Apr 2025 19:54:47 +0200
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Subject: [PATCH] board: rock5b-rk3588: add ROCK 5B+ support
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The ROCK 5B and ROCK 5B+ are quite similar, but there are also a
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few changes, which require a different device tree. Most of the
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changes are not easily detectable at runtime, but it is possible
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to tell the boards apart by checking the memory type. All ROCK
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5B models use LPDDR4 and all ROCK 5B+ models use LPDDR5.
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Signed-off-by: Sebastian Reichel <[email protected]>
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---
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board/radxa/rock5b-rk3588/rock5b-rk3588.c | 65 +++++++++++++++++++++++
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1 file changed, 65 insertions(+)
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diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
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index fc2f69db224..afe10ca0d16 100644
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--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
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+++ b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
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@@ -5,6 +5,10 @@
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#include <fdtdec.h>
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#include <fdt_support.h>
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+#include <linux/bitfield.h>
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+#include <linux/bitops.h>
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+#include <env.h>
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+#include <asm/io.h>
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, struct bd_info *bd)
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@@ -14,3 +18,64 @@ int ft_board_setup(void *blob, struct bd_info *bd)
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return 0;
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}
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#endif
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+
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+enum {
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+ ROCKCHIP_DDR4 = 0,
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+ ROCKCHIP_DDR2 = 2,
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+ ROCKCHIP_DDR3 = 3,
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+ ROCKCHIP_LPDDR2 = 5,
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+ ROCKCHIP_LPDDR3 = 6,
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+ ROCKCHIP_LPDDR4 = 7,
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+ ROCKCHIP_LPDDR4X = 8,
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+ ROCKCHIP_LPDDR5 = 9,
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+ ROCKCHIP_DDR5 = 10,
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+ ROCKCHIP_UNUSED = 0xFF
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+};
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+
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+#define RK3588_PMUGRF_BASE_ADDR 0xfd58a000
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+#define RK3588_PMUGRF_OS_REG2 0x208
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+#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13)
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+#define RK3588_PMUGRF_OS_REG3 0x20c
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+#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
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+#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
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+
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+static int rk3588_get_memory_type(void)
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+{
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+ u32 reg2 = readl(RK3588_PMUGRF_BASE_ADDR + RK3588_PMUGRF_OS_REG2);
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+ u32 reg3 = readl(RK3588_PMUGRF_BASE_ADDR + RK3588_PMUGRF_OS_REG3);
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+ u32 ddr_type;
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+
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+ /* lower 3 bits of the DDR type */
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+ ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
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+
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+ /*
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+ * For version three and higher the upper two bits of the DDR type are
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+ * in RK3588_PMUGRF_OS_REG3
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+ */
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+ if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
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+ ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
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+
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+ return ddr_type;
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+}
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+
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+static const char* rock5_get_model_devicetree(void)
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+{
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+ switch (rk3588_get_memory_type()) {
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+ case ROCKCHIP_LPDDR5:
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+ return "rockchip/rk3588-rock-5b-plus.dtb";
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+ case ROCKCHIP_LPDDR4:
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+ default:
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+ return "rockchip/rk3588-rock-5b.dtb";
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+ }
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+}
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+
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+int board_fit_config_name_match(const char *name)
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+{
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+ return strcmp(name, rock5_get_model_devicetree());
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+}
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+
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+int rk_board_late_init(void)
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+{
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+ env_set("fdtfile", rock5_get_model_devicetree());
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+ return 0;
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+}
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