2872 lines
66 KiB
Diff
2872 lines
66 KiB
Diff
From a7dfe216ceb5718a6a02b7f0ac7cedbe33f8923d Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <[email protected]>
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Date: Wed, 2 Apr 2025 19:48:45 +0200
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Subject: [PATCH] [HACK] arm64: dts: rockchip: Copy recent DT for Rock 5B+
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This is a simple copy of the latest RK3588 DT from upstream
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Linux including the ROCK 5B+ devicetree, which I'm currently
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working on. The goal is a combined U-Boot image, which works
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on the ROCK 5B and the ROCK 5B+ and chooses the correct DT
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file at runtime.
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Signed-off-by: Sebastian Reichel <[email protected]>
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---
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.../src/arm64/rockchip/rk3588-base.dtsi | 293 ++++-
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.../src/arm64/rockchip/rk3588-extra.dtsi | 189 +++
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.../arm64/rockchip/rk3588-rock-5b-plus.dts | 113 ++
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.../src/arm64/rockchip/rk3588-rock-5b.dts | 875 +------------
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.../src/arm64/rockchip/rk3588-rock-5b.dtsi | 1088 +++++++++++++++++
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5 files changed, 1671 insertions(+), 887 deletions(-)
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create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts
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create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi
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diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
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index a337f3fb837..bb77d5987e7 100644
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--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
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+++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
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@@ -358,11 +358,6 @@
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};
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firmware {
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- optee: optee {
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- compatible = "linaro,optee-tz";
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- method = "smc";
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- };
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-
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scmi: scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0x82000010>;
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@@ -382,6 +377,22 @@
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};
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};
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+ hdmi0_sound: hdmi0-sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,mclk-fs = <128>;
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+ simple-audio-card,name = "hdmi0";
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+ status = "disabled";
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+
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+ simple-audio-card,codec {
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+ sound-dai = <&hdmi0>;
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+ };
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&i2s5_8ch>;
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+ };
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+ };
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+
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pmu-a55 {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
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@@ -549,22 +560,21 @@
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mmu600_pcie: iommu@fc900000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0xfc900000 0x0 0x200000>;
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- interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
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- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
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- <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
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- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
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+ interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>,
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+ <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>,
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+ <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
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+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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#iommu-cells = <1>;
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- status = "disabled";
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};
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mmu600_php: iommu@fcb00000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0xfcb00000 0x0 0x200000>;
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- interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
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- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
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- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
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- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
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+ interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>,
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+ <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>,
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+ <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>,
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+ <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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#iommu-cells = <1>;
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status = "disabled";
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@@ -580,6 +590,16 @@
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reg = <0x0 0xfd58c000 0x0 0x1000>;
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};
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+ mipidcphy0_grf: syscon@fd5e8000 {
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+ compatible = "rockchip,rk3588-dcphy-grf", "syscon";
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+ reg = <0x0 0xfd5e8000 0x0 0x4000>;
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+ };
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+
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+ mipidcphy1_grf: syscon@fd5ec000 {
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+ compatible = "rockchip,rk3588-dcphy-grf", "syscon";
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+ reg = <0x0 0xfd5ec000 0x0 0x4000>;
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+ };
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+
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vop_grf: syscon@fd5a4000 {
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compatible = "rockchip,rk3588-vop-grf", "syscon";
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reg = <0x0 0xfd5a4000 0x0 0x2000>;
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@@ -865,7 +885,7 @@
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};
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};
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/* These power domains are grouped by VD_GPU */
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- power-domain@RK3588_PD_GPU {
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+ pd_gpu: power-domain@RK3588_PD_GPU {
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reg = <RK3588_PD_GPU>;
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clocks = <&cru CLK_GPU>,
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<&cru CLK_GPU_COREGROUP>,
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@@ -1238,6 +1258,44 @@
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#iommu-cells = <0>;
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};
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+ vdec0: video-decoder@fdc38000 {
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+ compatible = "rockchip,rk3588-vdec";
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+ reg = <0x0 0xfdc38000 0x0 0x100>, <0x0 0xfdc38100 0x0 0x500>, <0x0 0xfdc38600 0x0 0x100>;
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+ reg-names = "link", "function", "cache";
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+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
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+ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
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+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
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+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
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+ assigned-clock-rates = <800000000>, <600000000>,
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+ <600000000>, <1000000000>;
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+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
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+ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
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+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ power-domains = <&power RK3588_PD_RKVDEC0>;
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+ sram = <&vdec0_sram>;
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+ };
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+
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+ vdec1: video-decoder@fdc40000 {
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+ compatible = "rockchip,rk3588-vdec";
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+ reg = <0x0 0xfdc40000 0x0 0x100>, <0x0 0xfdc40100 0x0 0x500>, <0x0 0xfdc40600 0x0 0x100>;
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+ reg-names = "link", "function", "cache";
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+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
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+ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
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+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
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+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
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+ assigned-clock-rates = <800000000>, <600000000>,
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+ <600000000>, <1000000000>;
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+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
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+ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
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+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
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+ power-domains = <&power RK3588_PD_RKVDEC1>;
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+ sram = <&vdec1_sram>;
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+ };
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+
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av1d: video-codec@fdc70000 {
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compatible = "rockchip,rk3588-av1-vpu";
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reg = <0x0 0xfdc70000 0x0 0x800>;
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@@ -1262,16 +1320,30 @@
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<&cru DCLK_VOP1>,
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<&cru DCLK_VOP2>,
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<&cru DCLK_VOP3>,
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- <&cru PCLK_VOP_ROOT>;
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+ <&cru PCLK_VOP_ROOT>,
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+ <&hdptxphy0>;
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clock-names = "aclk",
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"hclk",
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"dclk_vp0",
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"dclk_vp1",
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"dclk_vp2",
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"dclk_vp3",
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- "pclk_vop";
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+ "pclk_vop",
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+ "pll_hdmiphy0";
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iommus = <&vop_mmu>;
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power-domains = <&power RK3588_PD_VOP>;
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+ resets = <&cru SRST_A_VOP>,
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+ <&cru SRST_H_VOP>,
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+ <&cru SRST_D_VOP0>,
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+ <&cru SRST_D_VOP1>,
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+ <&cru SRST_D_VOP2>,
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+ <&cru SRST_D_VOP3>;
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+ reset-names = "aclk",
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+ "hclk",
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+ "dclk_vp0",
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+ "dclk_vp1",
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+ "dclk_vp2",
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+ "dclk_vp3";
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rockchip,grf = <&sys_grf>;
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rockchip,vop-grf = <&vop_grf>;
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rockchip,vo1-grf = <&vo1_grf>;
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@@ -1319,6 +1391,21 @@
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status = "disabled";
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};
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+ spdif_tx2: spdif-tx@fddb0000 {
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+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
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+ reg = <0x0 0xfddb0000 0x0 0x1000>;
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+ assigned-clock-parents = <&cru PLL_AUPLL>;
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+ assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
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+ clock-names = "mclk", "hclk";
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+ clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>;
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+ dma-names = "tx";
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+ dmas = <&dmac1 6>;
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+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
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+ power-domains = <&power RK3588_PD_VO0>;
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+ #sound-dai-cells = <0>;
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+ status = "disabled";
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+ };
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+
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i2s4_8ch: i2s@fddc0000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc0000 0x0 0x1000>;
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@@ -1336,6 +1423,21 @@
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status = "disabled";
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};
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+ spdif_tx3: spdif-tx@fdde0000 {
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+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
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+ reg = <0x0 0xfdde0000 0x0 0x1000>;
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+ assigned-clock-parents = <&cru PLL_AUPLL>;
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+ assigned-clocks = <&cru CLK_SPDIF3_SRC>;
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+ clock-names = "mclk", "hclk";
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+ clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>;
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+ dma-names = "tx";
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+ dmas = <&dmac1 7>;
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+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
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+ power-domains = <&power RK3588_PD_VO1>;
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+ #sound-dai-cells = <0>;
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+ status = "disabled";
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+ };
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+
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i2s5_8ch: i2s@fddf0000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf0000 0x0 0x1000>;
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@@ -1370,6 +1472,62 @@
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status = "disabled";
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};
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+ dsi0: dsi@fde20000 {
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+ compatible = "rockchip,rk3588-mipi-dsi2";
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+ reg = <0x0 0xfde20000 0x0 0x10000>;
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+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
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+ clock-names = "pclk", "sys";
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+ resets = <&cru SRST_P_DSIHOST0>;
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+ reset-names = "apb";
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+ power-domains = <&power RK3588_PD_VOP>;
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+ phys = <&mipidcphy0>;
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+ phy-names = "dcphy";
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+ rockchip,grf = <&vop_grf>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ dsi0_in: port@0 {
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+ reg = <0>;
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+ };
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+
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+ dsi0_out: port@1 {
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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+ dsi1: dsi@fde30000 {
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+ compatible = "rockchip,rk3588-mipi-dsi2";
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+ reg = <0x0 0xfde30000 0x0 0x10000>;
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+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>;
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+ clock-names = "pclk", "sys";
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+ resets = <&cru SRST_P_DSIHOST1>;
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+ reset-names = "apb";
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+ power-domains = <&power RK3588_PD_VOP>;
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+ phys = <&mipidcphy1>;
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+ phy-names = "dcphy";
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+ rockchip,grf = <&vop_grf>;
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ dsi1_in: port@0 {
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+ reg = <0>;
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+ };
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+
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+ dsi1_out: port@1 {
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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hdmi0: hdmi@fde80000 {
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compatible = "rockchip,rk3588-dw-hdmi-qp";
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reg = <0x0 0xfde80000 0x0 0x20000>;
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@@ -1386,7 +1544,7 @@
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "avp", "cec", "earc", "main", "hpd";
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- phys = <&hdptxphy_hdmi0>;
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+ phys = <&hdptxphy0>;
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pinctrl-names = "default";
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pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
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&hdmim0_tx0_scl &hdmim0_tx0_sda>;
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@@ -1395,6 +1553,7 @@
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reset-names = "ref", "hdp";
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rockchip,grf = <&sys_grf>;
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rockchip,vo-grf = <&vo1_grf>;
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+ #sound-dai-cells = <0>;
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status = "disabled";
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ports {
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@@ -1686,6 +1845,7 @@
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linux,pci-domain = <3>;
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max-link-speed = <2>;
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msi-map = <0x3000 &its0 0x3000 0x1000>;
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+ iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy2_psu PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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@@ -1737,6 +1897,7 @@
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linux,pci-domain = <4>;
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max-link-speed = <2>;
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msi-map = <0x4000 &its0 0x4000 0x1000>;
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+ iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy0_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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@@ -1920,6 +2081,14 @@
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status = "disabled";
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};
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+ rng@fe378000 {
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+ compatible = "rockchip,rk3588-rng";
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+ reg = <0x0 0xfe378000 0x0 0x200>;
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+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
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+ resets = <&scmi_reset 48>;
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+ };
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+
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i2s0_8ch: i2s@fe470000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfe470000 0x0 0x1000>;
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@@ -2015,12 +2184,47 @@
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status = "disabled";
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};
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+ spdif_tx0: spdif-tx@fe4e0000 {
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+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
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+ reg = <0x0 0xfe4e0000 0x0 0x1000>;
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+ assigned-clock-parents = <&cru PLL_AUPLL>;
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+ assigned-clocks = <&cru CLK_SPDIF0_SRC>;
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+ clock-names = "mclk", "hclk";
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+ clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>;
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+ dma-names = "tx";
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+ dmas = <&dmac0 5>;
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+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
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+ pinctrl-0 = <&spdif0m0_tx>;
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+ pinctrl-names = "default";
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+ power-domains = <&power RK3588_PD_AUDIO>;
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+ #sound-dai-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spdif_tx1: spdif-tx@fe4f0000 {
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+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
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+ reg = <0x0 0xfe4f0000 0x0 0x1000>;
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+ assigned-clock-parents = <&cru PLL_AUPLL>;
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+ assigned-clocks = <&cru CLK_SPDIF1_SRC>;
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+ clock-names = "mclk", "hclk";
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+ clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>;
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+ dma-names = "tx";
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+ dmas = <&dmac1 5>;
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+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
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+ pinctrl-0 = <&spdif1m0_tx>;
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+ pinctrl-names = "default";
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+ power-domains = <&power RK3588_PD_AUDIO>;
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+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
gic: interrupt-controller@fe600000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
|
|
<0x0 0xfe680000 0 0x100000>; /* GICR */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
interrupt-controller;
|
|
+ dma-noncoherent;
|
|
mbi-alias = <0x0 0xfe610000>;
|
|
mbi-ranges = <424 56>;
|
|
msi-controller;
|
|
@@ -2032,6 +2236,7 @@
|
|
its0: msi-controller@fe640000 {
|
|
compatible = "arm,gic-v3-its";
|
|
reg = <0x0 0xfe640000 0x0 0x20000>;
|
|
+ dma-noncoherent;
|
|
msi-controller;
|
|
#msi-cells = <1>;
|
|
};
|
|
@@ -2039,6 +2244,7 @@
|
|
its1: msi-controller@fe660000 {
|
|
compatible = "arm,gic-v3-its";
|
|
reg = <0x0 0xfe660000 0x0 0x20000>;
|
|
+ dma-noncoherent;
|
|
msi-controller;
|
|
#msi-cells = <1>;
|
|
};
|
|
@@ -2667,9 +2873,9 @@
|
|
rockchip,hw-tshut-temp = <120000>;
|
|
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
|
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
|
- pinctrl-0 = <&tsadc_gpio_func>;
|
|
- pinctrl-1 = <&tsadc_shut>;
|
|
- pinctrl-names = "gpio", "otpout";
|
|
+ pinctrl-0 = <&tsadc_shut_org>;
|
|
+ pinctrl-1 = <&tsadc_gpio_func>;
|
|
+ pinctrl-names = "default", "sleep";
|
|
#thermal-sensor-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
@@ -2806,11 +3012,12 @@
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
- hdptxphy_hdmi0: phy@fed60000 {
|
|
+ hdptxphy0: phy@fed60000 {
|
|
compatible = "rockchip,rk3588-hdptx-phy";
|
|
reg = <0x0 0xfed60000 0x0 0x2000>;
|
|
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
|
|
clock-names = "ref", "apb";
|
|
+ #clock-cells = <0>;
|
|
#phy-cells = <0>;
|
|
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
|
|
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
|
|
@@ -2844,6 +3051,38 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ mipidcphy0: phy@feda0000 {
|
|
+ compatible = "rockchip,rk3588-mipi-dcphy";
|
|
+ reg = <0x0 0xfeda0000 0x0 0x10000>;
|
|
+ rockchip,grf = <&mipidcphy0_grf>;
|
|
+ clocks = <&cru PCLK_MIPI_DCPHY0>,
|
|
+ <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
|
|
+ clock-names = "pclk", "ref";
|
|
+ resets = <&cru SRST_M_MIPI_DCPHY0>,
|
|
+ <&cru SRST_P_MIPI_DCPHY0>,
|
|
+ <&cru SRST_P_MIPI_DCPHY0_GRF>,
|
|
+ <&cru SRST_S_MIPI_DCPHY0>;
|
|
+ reset-names = "m_phy", "apb", "grf", "s_phy";
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mipidcphy1: phy@fedb0000 {
|
|
+ compatible = "rockchip,rk3588-mipi-dcphy";
|
|
+ reg = <0x0 0xfedb0000 0x0 0x10000>;
|
|
+ rockchip,grf = <&mipidcphy1_grf>;
|
|
+ clocks = <&cru PCLK_MIPI_DCPHY1>,
|
|
+ <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
|
|
+ clock-names = "pclk", "ref";
|
|
+ resets = <&cru SRST_M_MIPI_DCPHY1>,
|
|
+ <&cru SRST_P_MIPI_DCPHY1>,
|
|
+ <&cru SRST_P_MIPI_DCPHY1_GRF>,
|
|
+ <&cru SRST_S_MIPI_DCPHY1>;
|
|
+ reset-names = "m_phy", "apb", "grf", "s_phy";
|
|
+ #phy-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
combphy0_ps: phy@fee00000 {
|
|
compatible = "rockchip,rk3588-naneng-combphy";
|
|
reg = <0x0 0xfee00000 0x0 0x100>;
|
|
@@ -2882,6 +3121,16 @@
|
|
ranges = <0x0 0x0 0xff001000 0xef000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
+
|
|
+ vdec0_sram: codec-sram@0 {
|
|
+ reg = <0x0 0x78000>;
|
|
+ pool;
|
|
+ };
|
|
+
|
|
+ vdec1_sram: codec-sram@78000 {
|
|
+ reg = <0x78000 0x77000>;
|
|
+ pool;
|
|
+ };
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
|
|
index 0ce0934ec6b..099edb3fd0f 100644
|
|
--- a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
|
|
+++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi
|
|
@@ -7,6 +7,46 @@
|
|
#include "rk3588-extra-pinctrl.dtsi"
|
|
|
|
/ {
|
|
+ hdmi1_sound: hdmi1-sound {
|
|
+ compatible = "simple-audio-card";
|
|
+ simple-audio-card,format = "i2s";
|
|
+ simple-audio-card,mclk-fs = <128>;
|
|
+ simple-audio-card,name = "hdmi1";
|
|
+ status = "disabled";
|
|
+
|
|
+ simple-audio-card,codec {
|
|
+ sound-dai = <&hdmi1>;
|
|
+ };
|
|
+
|
|
+ simple-audio-card,cpu {
|
|
+ sound-dai = <&i2s6_8ch>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ reserved-memory {
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+
|
|
+ /*
|
|
+ * The 4k HDMI capture controller works only with 32bit
|
|
+ * phys addresses and doesn't support IOMMU. HDMI RX CMA
|
|
+ * must be reserved below 4GB.
|
|
+ * The size of 160MB was determined as follows:
|
|
+ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
|
|
+ * To ensure sufficient support for practical use-cases,
|
|
+ * we doubled the 66MB value.
|
|
+ */
|
|
+ hdmi_receiver_cma: hdmi-receiver-cma {
|
|
+ compatible = "shared-dma-pool";
|
|
+ alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
|
|
+ size = <0x0 (160 * 0x100000)>; /* 160MiB */
|
|
+ alignment = <0x0 0x40000>; /* 64K */
|
|
+ no-map;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
usb_host1_xhci: usb@fc400000 {
|
|
compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
|
|
reg = <0x0 0xfc400000 0x0 0x400000>;
|
|
@@ -67,6 +107,26 @@
|
|
};
|
|
};
|
|
|
|
+ hdptxphy1_grf: syscon@fd5e4000 {
|
|
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
|
|
+ reg = <0x0 0xfd5e4000 0x0 0x100>;
|
|
+ };
|
|
+
|
|
+ spdif_tx5: spdif-tx@fddb8000 {
|
|
+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
|
+ reg = <0x0 0xfddb8000 0x0 0x1000>;
|
|
+ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
+ assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
|
|
+ clock-names = "mclk", "hclk";
|
|
+ clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>;
|
|
+ dma-names = "tx";
|
|
+ dmas = <&dmac1 22>;
|
|
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ power-domains = <&power RK3588_PD_VO0>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
i2s8_8ch: i2s@fddc8000 {
|
|
compatible = "rockchip,rk3588-i2s-tdm";
|
|
reg = <0x0 0xfddc8000 0x0 0x1000>;
|
|
@@ -84,6 +144,21 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ spdif_tx4: spdif-tx@fdde8000 {
|
|
+ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
|
+ reg = <0x0 0xfdde8000 0x0 0x1000>;
|
|
+ assigned-clock-parents = <&cru PLL_AUPLL>;
|
|
+ assigned-clocks = <&cru CLK_SPDIF4_SRC>;
|
|
+ clock-names = "mclk", "hclk";
|
|
+ clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>;
|
|
+ dma-names = "tx";
|
|
+ dmas = <&dmac1 8>;
|
|
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ power-domains = <&power RK3588_PD_VO1>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
i2s6_8ch: i2s@fddf4000 {
|
|
compatible = "rockchip,rk3588-i2s-tdm";
|
|
reg = <0x0 0xfddf4000 0x0 0x1000>;
|
|
@@ -135,6 +210,79 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ hdmi1: hdmi@fdea0000 {
|
|
+ compatible = "rockchip,rk3588-dw-hdmi-qp";
|
|
+ reg = <0x0 0xfdea0000 0x0 0x20000>;
|
|
+ clocks = <&cru PCLK_HDMITX1>,
|
|
+ <&cru CLK_HDMITX1_EARC>,
|
|
+ <&cru CLK_HDMITX1_REF>,
|
|
+ <&cru MCLK_I2S6_8CH_TX>,
|
|
+ <&cru CLK_HDMIHDP1>,
|
|
+ <&cru HCLK_VO1>;
|
|
+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
|
|
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
|
|
+ phys = <&hdptxphy1>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
|
|
+ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
|
|
+ power-domains = <&power RK3588_PD_VO1>;
|
|
+ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
|
|
+ reset-names = "ref", "hdp";
|
|
+ rockchip,grf = <&sys_grf>;
|
|
+ rockchip,vo-grf = <&vo1_grf>;
|
|
+ #sound-dai-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ hdmi1_in: port@0 {
|
|
+ reg = <0>;
|
|
+ };
|
|
+
|
|
+ hdmi1_out: port@1 {
|
|
+ reg = <1>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hdmi_receiver: hdmi_receiver@fdee0000 {
|
|
+ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
|
|
+ reg = <0x0 0xfdee0000 0x0 0x6000>;
|
|
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
|
|
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ interrupt-names = "cec", "hdmi", "dma";
|
|
+ clocks = <&cru ACLK_HDMIRX>,
|
|
+ <&cru CLK_HDMIRX_AUD>,
|
|
+ <&cru CLK_CR_PARA>,
|
|
+ <&cru PCLK_HDMIRX>,
|
|
+ <&cru CLK_HDMIRX_REF>,
|
|
+ <&cru PCLK_S_HDMIRX>,
|
|
+ <&cru HCLK_VO1>;
|
|
+ clock-names = "aclk",
|
|
+ "audio",
|
|
+ "cr_para",
|
|
+ "pclk",
|
|
+ "ref",
|
|
+ "hclk_s_hdmirx",
|
|
+ "hclk_vo1";
|
|
+ memory-region = <&hdmi_receiver_cma>;
|
|
+ power-domains = <&power RK3588_PD_VO1>;
|
|
+ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
|
|
+ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
|
|
+ reset-names = "axi", "apb", "ref", "biu";
|
|
+ rockchip,grf = <&sys_grf>;
|
|
+ rockchip,vo1-grf = <&vo1_grf>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
pcie3x4: pcie@fe150000 {
|
|
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
|
#address-cells = <3>;
|
|
@@ -162,6 +310,7 @@
|
|
linux,pci-domain = <0>;
|
|
max-link-speed = <3>;
|
|
msi-map = <0x0000 &its1 0x0000 0x1000>;
|
|
+ iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>;
|
|
num-lanes = <4>;
|
|
phys = <&pcie30phy>;
|
|
phy-names = "pcie-phy";
|
|
@@ -248,6 +397,7 @@
|
|
linux,pci-domain = <1>;
|
|
max-link-speed = <3>;
|
|
msi-map = <0x1000 &its1 0x1000 0x1000>;
|
|
+ iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>;
|
|
num-lanes = <2>;
|
|
phys = <&pcie30phy>;
|
|
phy-names = "pcie-phy";
|
|
@@ -297,6 +447,7 @@
|
|
linux,pci-domain = <2>;
|
|
max-link-speed = <2>;
|
|
msi-map = <0x2000 &its0 0x2000 0x1000>;
|
|
+ iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>;
|
|
num-lanes = <1>;
|
|
phys = <&combphy1_ps PHY_TYPE_PCIE>;
|
|
phy-names = "pcie-phy";
|
|
@@ -395,6 +546,23 @@
|
|
};
|
|
};
|
|
|
|
+ hdptxphy1: phy@fed70000 {
|
|
+ compatible = "rockchip,rk3588-hdptx-phy";
|
|
+ reg = <0x0 0xfed70000 0x0 0x2000>;
|
|
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
|
|
+ clock-names = "ref", "apb";
|
|
+ #clock-cells = <0>;
|
|
+ #phy-cells = <0>;
|
|
+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
|
|
+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
|
|
+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
|
|
+ <&cru SRST_HDPTX1_LCPLL>;
|
|
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
|
|
+ "lcpll";
|
|
+ rockchip,grf = <&hdptxphy1_grf>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
usbdp_phy1: phy@fed90000 {
|
|
compatible = "rockchip,rk3588-usbdp-phy";
|
|
reg = <0x0 0xfed90000 0x0 0x10000>;
|
|
@@ -446,3 +614,24 @@
|
|
status = "disabled";
|
|
};
|
|
};
|
|
+
|
|
+&vop {
|
|
+ clocks = <&cru ACLK_VOP>,
|
|
+ <&cru HCLK_VOP>,
|
|
+ <&cru DCLK_VOP0>,
|
|
+ <&cru DCLK_VOP1>,
|
|
+ <&cru DCLK_VOP2>,
|
|
+ <&cru DCLK_VOP3>,
|
|
+ <&cru PCLK_VOP_ROOT>,
|
|
+ <&hdptxphy0>,
|
|
+ <&hdptxphy1>;
|
|
+ clock-names = "aclk",
|
|
+ "hclk",
|
|
+ "dclk_vp0",
|
|
+ "dclk_vp1",
|
|
+ "dclk_vp2",
|
|
+ "dclk_vp3",
|
|
+ "pclk_vop",
|
|
+ "pll_hdmiphy0",
|
|
+ "pll_hdmiphy1";
|
|
+};
|
|
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts
|
|
new file mode 100644
|
|
index 00000000000..74c7b6502e4
|
|
--- /dev/null
|
|
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b-plus.dts
|
|
@@ -0,0 +1,113 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include "rk3588-rock-5b.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Radxa ROCK 5B+";
|
|
+ compatible = "radxa,rock-5b-plus", "rockchip,rk3588";
|
|
+
|
|
+ rfkill-wwan {
|
|
+ compatible = "rfkill-gpio";
|
|
+ label = "rfkill-m2-wwan";
|
|
+ radio-type = "wwan";
|
|
+ shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+
|
|
+ vcc3v3_4g: regulator-vcc3v3-4g {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
|
|
+ /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */
|
|
+ regulator-name = "vcc3v3_4g";
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ startup-delay-us = <50000>;
|
|
+ vin-supply = <&vcc5v0_sys>;
|
|
+ };
|
|
+
|
|
+ vcc3v3_wwan_pwr: regulator-vcc3v3-wwan {
|
|
+ compatible = "regulator-fixed";
|
|
+ enable-active-high;
|
|
+ gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&wwan_power_en>;
|
|
+ regulator-name = "vcc3v3_wwan_pwr";
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ vin-supply = <&vcc3v3_4g>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&gpio0 {
|
|
+ wwan-disable2-n-hog {
|
|
+ gpios = <RK_PB2 GPIO_ACTIVE_LOW>;
|
|
+ output-low;
|
|
+ line-name = "M.2 B-key W_DISABLE2#";
|
|
+ gpio-hog;
|
|
+ };
|
|
+};
|
|
+
|
|
+&gpio2 {
|
|
+ wwan-reset-n-hog {
|
|
+ gpios = <RK_PB3 GPIO_ACTIVE_LOW>;
|
|
+ output-low;
|
|
+ line-name = "M.2 B-key RESET#";
|
|
+ gpio-hog;
|
|
+ };
|
|
+
|
|
+ wwan-wake-n-hog {
|
|
+ gpios = <RK_PB2 GPIO_ACTIVE_LOW>;
|
|
+ input;
|
|
+ line-name = "M.2 B-key WoWWAN#";
|
|
+ gpio-hog;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pcie30phy {
|
|
+ data-lanes = <1 1 2 2>;
|
|
+};
|
|
+
|
|
+&pcie3x2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie3x2_rst>;
|
|
+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
|
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pcie3x4 {
|
|
+ num-lanes = <2>;
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ wwan {
|
|
+ wwan_power_en: wwan-pwr-en {
|
|
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie3 {
|
|
+ pcie3x2_rst: pcie3x2-rst {
|
|
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb {
|
|
+ vcc5v0_host_en: vcc5v0-host-en {
|
|
+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&vcc5v0_host {
|
|
+ enable-active-high;
|
|
+ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&vcc5v0_host_en>;
|
|
+};
|
|
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
|
|
index d597112f1d5..9407a7c9910 100644
|
|
--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
|
|
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts
|
|
@@ -2,462 +2,11 @@
|
|
|
|
/dts-v1/;
|
|
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
-#include <dt-bindings/leds/common.h>
|
|
-#include <dt-bindings/soc/rockchip,vop2.h>
|
|
-#include "rk3588.dtsi"
|
|
+#include "rk3588-rock-5b.dtsi"
|
|
|
|
/ {
|
|
model = "Radxa ROCK 5B";
|
|
compatible = "radxa,rock-5b", "rockchip,rk3588";
|
|
-
|
|
- aliases {
|
|
- mmc0 = &sdhci;
|
|
- mmc1 = &sdmmc;
|
|
- mmc2 = &sdio;
|
|
- };
|
|
-
|
|
- chosen {
|
|
- stdout-path = "serial2:1500000n8";
|
|
- };
|
|
-
|
|
- analog-sound {
|
|
- compatible = "audio-graph-card";
|
|
- label = "rk3588-es8316";
|
|
-
|
|
- widgets = "Microphone", "Mic Jack",
|
|
- "Headphone", "Headphones";
|
|
-
|
|
- routing = "MIC2", "Mic Jack",
|
|
- "Headphones", "HPOL",
|
|
- "Headphones", "HPOR";
|
|
-
|
|
- dais = <&i2s0_8ch_p0>;
|
|
- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&hp_detect>;
|
|
- };
|
|
-
|
|
- hdmi0-con {
|
|
- compatible = "hdmi-connector";
|
|
- type = "a";
|
|
-
|
|
- port {
|
|
- hdmi0_con_in: endpoint {
|
|
- remote-endpoint = <&hdmi0_out_con>;
|
|
- };
|
|
- };
|
|
- };
|
|
-
|
|
- leds {
|
|
- compatible = "gpio-leds";
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&led_rgb_b>;
|
|
-
|
|
- led_rgb_b {
|
|
- function = LED_FUNCTION_STATUS;
|
|
- color = <LED_COLOR_ID_BLUE>;
|
|
- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
|
- linux,default-trigger = "heartbeat";
|
|
- };
|
|
- };
|
|
-
|
|
- fan: pwm-fan {
|
|
- compatible = "pwm-fan";
|
|
- cooling-levels = <0 120 150 180 210 240 255>;
|
|
- fan-supply = <&vcc5v0_sys>;
|
|
- pwms = <&pwm1 0 50000 0>;
|
|
- #cooling-cells = <2>;
|
|
- };
|
|
-
|
|
- rfkill {
|
|
- compatible = "rfkill-gpio";
|
|
- label = "rfkill-m2-wlan";
|
|
- radio-type = "wlan";
|
|
- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
|
|
- };
|
|
-
|
|
- rfkill-bt {
|
|
- compatible = "rfkill-gpio";
|
|
- label = "rfkill-m2-bt";
|
|
- radio-type = "bluetooth";
|
|
- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
|
|
- };
|
|
-
|
|
- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
|
|
- compatible = "regulator-fixed";
|
|
- enable-active-high;
|
|
- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&pcie2_0_vcc3v3_en>;
|
|
- regulator-name = "vcc3v3_pcie2x1l0";
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- startup-delay-us = <50000>;
|
|
- vin-supply = <&vcc5v0_sys>;
|
|
- };
|
|
-
|
|
- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
|
|
- compatible = "regulator-fixed";
|
|
- regulator-name = "vcc3v3_pcie2x1l2";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- startup-delay-us = <5000>;
|
|
- vin-supply = <&vcc_3v3_s3>;
|
|
- };
|
|
-
|
|
- vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
|
|
- compatible = "regulator-fixed";
|
|
- enable-active-high;
|
|
- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&pcie3_vcc3v3_en>;
|
|
- regulator-name = "vcc3v3_pcie30";
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- startup-delay-us = <5000>;
|
|
- vin-supply = <&vcc5v0_sys>;
|
|
- };
|
|
-
|
|
- vcc5v0_host: regulator-vcc5v0-host {
|
|
- compatible = "regulator-fixed";
|
|
- regulator-name = "vcc5v0_host";
|
|
- regulator-boot-on;
|
|
- regulator-always-on;
|
|
- regulator-min-microvolt = <5000000>;
|
|
- regulator-max-microvolt = <5000000>;
|
|
- enable-active-high;
|
|
- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&vcc5v0_host_en>;
|
|
- vin-supply = <&vcc5v0_sys>;
|
|
- };
|
|
-
|
|
- vcc5v0_sys: regulator-vcc5v0-sys {
|
|
- compatible = "regulator-fixed";
|
|
- regulator-name = "vcc5v0_sys";
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <5000000>;
|
|
- regulator-max-microvolt = <5000000>;
|
|
- };
|
|
-
|
|
- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
|
|
- compatible = "regulator-fixed";
|
|
- regulator-name = "vcc_1v1_nldo_s3";
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <1100000>;
|
|
- regulator-max-microvolt = <1100000>;
|
|
- vin-supply = <&vcc5v0_sys>;
|
|
- };
|
|
-};
|
|
-
|
|
-&combphy0_ps {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&combphy1_ps {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&combphy2_psu {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&cpu_b0 {
|
|
- cpu-supply = <&vdd_cpu_big0_s0>;
|
|
-};
|
|
-
|
|
-&cpu_b1 {
|
|
- cpu-supply = <&vdd_cpu_big0_s0>;
|
|
-};
|
|
-
|
|
-&cpu_b2 {
|
|
- cpu-supply = <&vdd_cpu_big1_s0>;
|
|
-};
|
|
-
|
|
-&cpu_b3 {
|
|
- cpu-supply = <&vdd_cpu_big1_s0>;
|
|
-};
|
|
-
|
|
-&cpu_l0 {
|
|
- cpu-supply = <&vdd_cpu_lit_s0>;
|
|
-};
|
|
-
|
|
-&cpu_l1 {
|
|
- cpu-supply = <&vdd_cpu_lit_s0>;
|
|
-};
|
|
-
|
|
-&cpu_l2 {
|
|
- cpu-supply = <&vdd_cpu_lit_s0>;
|
|
-};
|
|
-
|
|
-&cpu_l3 {
|
|
- cpu-supply = <&vdd_cpu_lit_s0>;
|
|
-};
|
|
-
|
|
-&gpu {
|
|
- mali-supply = <&vdd_gpu_s0>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&hdmi0 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&hdmi0_in {
|
|
- hdmi0_in_vp0: endpoint {
|
|
- remote-endpoint = <&vp0_out_hdmi0>;
|
|
- };
|
|
-};
|
|
-
|
|
-&hdmi0_out {
|
|
- hdmi0_out_con: endpoint {
|
|
- remote-endpoint = <&hdmi0_con_in>;
|
|
- };
|
|
-};
|
|
-
|
|
-&hdptxphy_hdmi0 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&i2c0 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c0m2_xfer>;
|
|
- status = "okay";
|
|
-
|
|
- vdd_cpu_big0_s0: regulator@42 {
|
|
- compatible = "rockchip,rk8602";
|
|
- reg = <0x42>;
|
|
- fcs,suspend-voltage-selector = <1>;
|
|
- regulator-name = "vdd_cpu_big0_s0";
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <550000>;
|
|
- regulator-max-microvolt = <1050000>;
|
|
- regulator-ramp-delay = <2300>;
|
|
- vin-supply = <&vcc5v0_sys>;
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_cpu_big1_s0: regulator@43 {
|
|
- compatible = "rockchip,rk8603", "rockchip,rk8602";
|
|
- reg = <0x43>;
|
|
- fcs,suspend-voltage-selector = <1>;
|
|
- regulator-name = "vdd_cpu_big1_s0";
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <550000>;
|
|
- regulator-max-microvolt = <1050000>;
|
|
- regulator-ramp-delay = <2300>;
|
|
- vin-supply = <&vcc5v0_sys>;
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&i2c6 {
|
|
- status = "okay";
|
|
-
|
|
- hym8563: rtc@51 {
|
|
- compatible = "haoyu,hym8563";
|
|
- reg = <0x51>;
|
|
- #clock-cells = <0>;
|
|
- clock-output-names = "hym8563";
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&hym8563_int>;
|
|
- interrupt-parent = <&gpio0>;
|
|
- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
|
|
- wakeup-source;
|
|
- };
|
|
-};
|
|
-
|
|
-&i2c7 {
|
|
- status = "okay";
|
|
-
|
|
- es8316: audio-codec@11 {
|
|
- compatible = "everest,es8316";
|
|
- reg = <0x11>;
|
|
- clocks = <&cru I2S0_8CH_MCLKOUT>;
|
|
- clock-names = "mclk";
|
|
- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
|
|
- assigned-clock-rates = <12288000>;
|
|
- #sound-dai-cells = <0>;
|
|
-
|
|
- port {
|
|
- es8316_p0_0: endpoint {
|
|
- remote-endpoint = <&i2s0_8ch_p0_0>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&i2s0_8ch {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2s0_lrck
|
|
- &i2s0_mclk
|
|
- &i2s0_sclk
|
|
- &i2s0_sdi0
|
|
- &i2s0_sdo0>;
|
|
- status = "okay";
|
|
-
|
|
- i2s0_8ch_p0: port {
|
|
- i2s0_8ch_p0_0: endpoint {
|
|
- dai-format = "i2s";
|
|
- mclk-fs = <256>;
|
|
- remote-endpoint = <&es8316_p0_0>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&package_thermal {
|
|
- polling-delay = <1000>;
|
|
-
|
|
- trips {
|
|
- package_fan0: package-fan0 {
|
|
- temperature = <55000>;
|
|
- hysteresis = <2000>;
|
|
- type = "active";
|
|
- };
|
|
-
|
|
- package_fan1: package-fan1 {
|
|
- temperature = <65000>;
|
|
- hysteresis = <2000>;
|
|
- type = "active";
|
|
- };
|
|
- };
|
|
-
|
|
- cooling-maps {
|
|
- map0 {
|
|
- trip = <&package_fan0>;
|
|
- cooling-device = <&fan THERMAL_NO_LIMIT 1>;
|
|
- };
|
|
-
|
|
- map1 {
|
|
- trip = <&package_fan1>;
|
|
- cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&pcie2x1l0 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&pcie2_0_rst>;
|
|
- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
|
|
- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&pcie2x1l2 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&pcie2_2_rst>;
|
|
- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
|
- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&pcie30phy {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&pcie3x4 {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&pcie3_rst>;
|
|
- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
|
- vpcie3v3-supply = <&vcc3v3_pcie30>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&pinctrl {
|
|
- hym8563 {
|
|
- hym8563_int: hym8563-int {
|
|
- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
- };
|
|
-
|
|
- leds {
|
|
- led_rgb_b: led-rgb-b {
|
|
- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
- };
|
|
-
|
|
- sound {
|
|
- hp_detect: hp-detect {
|
|
- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
- };
|
|
-
|
|
- pcie2 {
|
|
- pcie2_0_rst: pcie2-0-rst {
|
|
- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
-
|
|
- pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
|
|
- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
-
|
|
- pcie2_2_rst: pcie2-2-rst {
|
|
- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
- };
|
|
-
|
|
- pcie3 {
|
|
- pcie3_rst: pcie3-rst {
|
|
- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
-
|
|
- pcie3_vcc3v3_en: pcie3-vcc3v3-en {
|
|
- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
- };
|
|
-
|
|
- usb {
|
|
- vcc5v0_host_en: vcc5v0-host-en {
|
|
- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&pwm1 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&saradc {
|
|
- vref-supply = <&avcc_1v8_s0>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&sdhci {
|
|
- bus-width = <8>;
|
|
- no-sdio;
|
|
- no-sd;
|
|
- non-removable;
|
|
- mmc-hs400-1_8v;
|
|
- mmc-hs400-enhanced-strobe;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&sdmmc {
|
|
- max-frequency = <200000000>;
|
|
- no-sdio;
|
|
- no-mmc;
|
|
- bus-width = <4>;
|
|
- cap-mmc-highspeed;
|
|
- cap-sd-highspeed;
|
|
- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
|
- disable-wp;
|
|
- sd-uhs-sdr104;
|
|
- vmmc-supply = <&vcc_3v3_s3>;
|
|
- vqmmc-supply = <&vccio_sd_s0>;
|
|
- status = "okay";
|
|
};
|
|
|
|
&sdio {
|
|
@@ -481,427 +30,23 @@
|
|
status = "okay";
|
|
};
|
|
|
|
-&sfc {
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&fspim2_pins>;
|
|
- status = "okay";
|
|
-
|
|
- flash@0 {
|
|
- compatible = "jedec,spi-nor";
|
|
- reg = <0>;
|
|
- spi-max-frequency = <104000000>;
|
|
- spi-rx-bus-width = <4>;
|
|
- spi-tx-bus-width = <1>;
|
|
- };
|
|
-};
|
|
-
|
|
&uart6 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
|
|
status = "okay";
|
|
};
|
|
|
|
-&spi2 {
|
|
- status = "okay";
|
|
- assigned-clocks = <&cru CLK_SPI2>;
|
|
- assigned-clock-rates = <200000000>;
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
|
|
- num-cs = <1>;
|
|
-
|
|
- pmic@0 {
|
|
- compatible = "rockchip,rk806";
|
|
- spi-max-frequency = <1000000>;
|
|
- reg = <0x0>;
|
|
-
|
|
- interrupt-parent = <&gpio0>;
|
|
- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
|
-
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
|
- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
|
-
|
|
- system-power-controller;
|
|
-
|
|
- vcc1-supply = <&vcc5v0_sys>;
|
|
- vcc2-supply = <&vcc5v0_sys>;
|
|
- vcc3-supply = <&vcc5v0_sys>;
|
|
- vcc4-supply = <&vcc5v0_sys>;
|
|
- vcc5-supply = <&vcc5v0_sys>;
|
|
- vcc6-supply = <&vcc5v0_sys>;
|
|
- vcc7-supply = <&vcc5v0_sys>;
|
|
- vcc8-supply = <&vcc5v0_sys>;
|
|
- vcc9-supply = <&vcc5v0_sys>;
|
|
- vcc10-supply = <&vcc5v0_sys>;
|
|
- vcc11-supply = <&vcc_2v0_pldo_s3>;
|
|
- vcc12-supply = <&vcc5v0_sys>;
|
|
- vcc13-supply = <&vcc_1v1_nldo_s3>;
|
|
- vcc14-supply = <&vcc_1v1_nldo_s3>;
|
|
- vcca-supply = <&vcc5v0_sys>;
|
|
-
|
|
- gpio-controller;
|
|
- #gpio-cells = <2>;
|
|
-
|
|
- rk806_dvs1_null: dvs1-null-pins {
|
|
- pins = "gpio_pwrctrl1";
|
|
- function = "pin_fun0";
|
|
- };
|
|
-
|
|
- rk806_dvs2_null: dvs2-null-pins {
|
|
- pins = "gpio_pwrctrl2";
|
|
- function = "pin_fun0";
|
|
- };
|
|
-
|
|
- rk806_dvs3_null: dvs3-null-pins {
|
|
- pins = "gpio_pwrctrl3";
|
|
- function = "pin_fun0";
|
|
- };
|
|
-
|
|
- regulators {
|
|
- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <550000>;
|
|
- regulator-max-microvolt = <950000>;
|
|
- regulator-ramp-delay = <12500>;
|
|
- regulator-name = "vdd_gpu_s0";
|
|
- regulator-enable-ramp-delay = <400>;
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <550000>;
|
|
- regulator-max-microvolt = <950000>;
|
|
- regulator-ramp-delay = <12500>;
|
|
- regulator-name = "vdd_cpu_lit_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_log_s0: dcdc-reg3 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <675000>;
|
|
- regulator-max-microvolt = <750000>;
|
|
- regulator-ramp-delay = <12500>;
|
|
- regulator-name = "vdd_log_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- regulator-suspend-microvolt = <750000>;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <550000>;
|
|
- regulator-max-microvolt = <950000>;
|
|
- regulator-ramp-delay = <12500>;
|
|
- regulator-name = "vdd_vdenc_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_ddr_s0: dcdc-reg5 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <675000>;
|
|
- regulator-max-microvolt = <900000>;
|
|
- regulator-ramp-delay = <12500>;
|
|
- regulator-name = "vdd_ddr_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- regulator-suspend-microvolt = <850000>;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd2_ddr_s3: dcdc-reg6 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-name = "vdd2_ddr_s3";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-on-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vcc_2v0_pldo_s3: dcdc-reg7 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <2000000>;
|
|
- regulator-max-microvolt = <2000000>;
|
|
- regulator-ramp-delay = <12500>;
|
|
- regulator-name = "vdd_2v0_pldo_s3";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-on-in-suspend;
|
|
- regulator-suspend-microvolt = <2000000>;
|
|
- };
|
|
- };
|
|
-
|
|
- vcc_3v3_s3: dcdc-reg8 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-name = "vcc_3v3_s3";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-on-in-suspend;
|
|
- regulator-suspend-microvolt = <3300000>;
|
|
- };
|
|
- };
|
|
-
|
|
- vddq_ddr_s0: dcdc-reg9 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-name = "vddq_ddr_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vcc_1v8_s3: dcdc-reg10 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- regulator-name = "vcc_1v8_s3";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-on-in-suspend;
|
|
- regulator-suspend-microvolt = <1800000>;
|
|
- };
|
|
- };
|
|
-
|
|
- avcc_1v8_s0: pldo-reg1 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- regulator-name = "avcc_1v8_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vcc_1v8_s0: pldo-reg2 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- regulator-name = "vcc_1v8_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- regulator-suspend-microvolt = <1800000>;
|
|
- };
|
|
- };
|
|
-
|
|
- avdd_1v2_s0: pldo-reg3 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <1200000>;
|
|
- regulator-max-microvolt = <1200000>;
|
|
- regulator-name = "avdd_1v2_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vcc_3v3_s0: pldo-reg4 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <3300000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-ramp-delay = <12500>;
|
|
- regulator-name = "vcc_3v3_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vccio_sd_s0: pldo-reg5 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <3300000>;
|
|
- regulator-ramp-delay = <12500>;
|
|
- regulator-name = "vccio_sd_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- pldo6_s3: pldo-reg6 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <1800000>;
|
|
- regulator-max-microvolt = <1800000>;
|
|
- regulator-name = "pldo6_s3";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-on-in-suspend;
|
|
- regulator-suspend-microvolt = <1800000>;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_0v75_s3: nldo-reg1 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <750000>;
|
|
- regulator-max-microvolt = <750000>;
|
|
- regulator-name = "vdd_0v75_s3";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-on-in-suspend;
|
|
- regulator-suspend-microvolt = <750000>;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_ddr_pll_s0: nldo-reg2 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <850000>;
|
|
- regulator-max-microvolt = <850000>;
|
|
- regulator-name = "vdd_ddr_pll_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- regulator-suspend-microvolt = <850000>;
|
|
- };
|
|
- };
|
|
-
|
|
- avdd_0v75_s0: nldo-reg3 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <750000>;
|
|
- regulator-max-microvolt = <750000>;
|
|
- regulator-name = "avdd_0v75_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_0v85_s0: nldo-reg4 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <850000>;
|
|
- regulator-max-microvolt = <850000>;
|
|
- regulator-name = "vdd_0v85_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
-
|
|
- vdd_0v75_s0: nldo-reg5 {
|
|
- regulator-always-on;
|
|
- regulator-boot-on;
|
|
- regulator-min-microvolt = <750000>;
|
|
- regulator-max-microvolt = <750000>;
|
|
- regulator-name = "vdd_0v75_s0";
|
|
-
|
|
- regulator-state-mem {
|
|
- regulator-off-in-suspend;
|
|
- };
|
|
- };
|
|
+&pinctrl {
|
|
+ usb {
|
|
+ vcc5v0_host_en: vcc5v0-host-en {
|
|
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
|
|
-&tsadc {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&uart2 {
|
|
- pinctrl-0 = <&uart2m0_xfer>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&u2phy1 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&u2phy1_otg {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&u2phy2 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&u2phy2_host {
|
|
- /* connected to USB hub, which is powered by vcc5v0_sys */
|
|
- phy-supply = <&vcc5v0_sys>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&u2phy3 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&u2phy3_host {
|
|
- phy-supply = <&vcc5v0_host>;
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usbdp_phy1 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usb_host0_ehci {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usb_host0_ohci {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usb_host1_ehci {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usb_host1_ohci {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usb_host1_xhci {
|
|
- dr_mode = "host";
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&usb_host2_xhci {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vop_mmu {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vop {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&vp0 {
|
|
- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
|
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
|
- remote-endpoint = <&hdmi0_in_vp0>;
|
|
- };
|
|
+&vcc5v0_host {
|
|
+ enable-active-high;
|
|
+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&vcc5v0_host_en>;
|
|
};
|
|
diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi
|
|
new file mode 100644
|
|
index 00000000000..4bdc16ea36a
|
|
--- /dev/null
|
|
+++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dtsi
|
|
@@ -0,0 +1,1088 @@
|
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/leds/common.h>
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+#include <dt-bindings/soc/rockchip,vop2.h>
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+#include <dt-bindings/usb/pd.h>
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+#include "rk3588.dtsi"
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+
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+/ {
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+ aliases {
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+ mmc0 = &sdhci;
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+ mmc1 = &sdmmc;
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+ mmc2 = &sdio;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ analog-sound {
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+ compatible = "audio-graph-card";
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+ label = "rk3588-es8316";
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+
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+ widgets = "Microphone", "Mic Jack",
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+ "Headphone", "Headphones";
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+
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+ routing = "MIC2", "Mic Jack",
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+ "Headphones", "HPOL",
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+ "Headphones", "HPOR";
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+
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+ dais = <&i2s0_8ch_p0>;
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+ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hp_detect>;
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+ };
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+
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+ hdmi0-con {
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+ compatible = "hdmi-connector";
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+ type = "a";
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+
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+ port {
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+ hdmi0_con_in: endpoint {
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+ remote-endpoint = <&hdmi0_out_con>;
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+ };
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+ };
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+ };
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+
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+ hdmi1-con {
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+ compatible = "hdmi-connector";
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+ type = "a";
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+
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+ port {
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+ hdmi1_con_in: endpoint {
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+ remote-endpoint = <&hdmi1_out_con>;
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+ };
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+ };
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&led_rgb_b>;
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+
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+ led_rgb_b {
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+ function = LED_FUNCTION_STATUS;
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+ color = <LED_COLOR_ID_BLUE>;
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+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "heartbeat";
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+ };
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+ };
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+
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+ fan: pwm-fan {
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+ compatible = "pwm-fan";
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+ cooling-levels = <0 120 150 180 210 240 255>;
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+ fan-supply = <&vcc5v0_sys>;
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+ pwms = <&pwm1 0 50000 0>;
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+ #cooling-cells = <2>;
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+ };
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+
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+ rfkill {
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+ compatible = "rfkill-gpio";
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+ label = "rfkill-m2-wlan";
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+ radio-type = "wlan";
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+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ rfkill-bt {
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+ compatible = "rfkill-gpio";
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+ label = "rfkill-m2-bt";
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+ radio-type = "bluetooth";
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+ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+
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+ vbus5v0_typec: vbus5v0-typec {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vbus5v0_typec_en>;
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+ regulator-name = "vbus5v0_typec";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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+ vcc12v_dcin: regulator-vcc12v-dcin {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc12v_dcin";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <12000000>;
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+ regulator-max-microvolt = <12000000>;
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+ };
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+
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+ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
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+ regulator-name = "vcc3v3_pcie2x1l0";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <50000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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+ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3_pcie2x1l2";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <5000>;
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+ vin-supply = <&vcc_3v3_s3>;
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+ };
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+
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+ vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie3_vcc3v3_en>;
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+ regulator-name = "vcc3v3_pcie30";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <5000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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+ vcc5v0_host: regulator-vcc5v0-host {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_host";
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+ regulator-boot-on;
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+ regulator-always-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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+ vcc5v0_sys: regulator-vcc5v0-sys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&vcc12v_dcin>;
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+ };
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+
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+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_1v1_nldo_s3";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1100000>;
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+ regulator-max-microvolt = <1100000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+};
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+
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+&combphy0_ps {
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+ status = "okay";
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+};
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+
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+&combphy1_ps {
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+ status = "okay";
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+};
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+
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+&combphy2_psu {
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+ status = "okay";
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+};
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+
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+&cpu_b0 {
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+ cpu-supply = <&vdd_cpu_big0_s0>;
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+};
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+
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+&cpu_b1 {
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+ cpu-supply = <&vdd_cpu_big0_s0>;
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+};
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+
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+&cpu_b2 {
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+ cpu-supply = <&vdd_cpu_big1_s0>;
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+};
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+
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+&cpu_b3 {
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+ cpu-supply = <&vdd_cpu_big1_s0>;
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+};
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+
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+&cpu_l0 {
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+ cpu-supply = <&vdd_cpu_lit_s0>;
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+};
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+
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+&cpu_l1 {
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+ cpu-supply = <&vdd_cpu_lit_s0>;
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+};
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+
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+&cpu_l2 {
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+ cpu-supply = <&vdd_cpu_lit_s0>;
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+};
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+
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+&cpu_l3 {
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+ cpu-supply = <&vdd_cpu_lit_s0>;
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+};
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+
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+&gpu {
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+ mali-supply = <&vdd_gpu_s0>;
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+ status = "okay";
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+};
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+
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+&hdmi0 {
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+ status = "okay";
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+};
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+
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+&hdmi0_in {
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+ hdmi0_in_vp0: endpoint {
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+ remote-endpoint = <&vp0_out_hdmi0>;
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+ };
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+};
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+
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+&hdmi0_out {
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+ hdmi0_out_con: endpoint {
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+ remote-endpoint = <&hdmi0_con_in>;
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+ };
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+};
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+
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+&hdmi0_sound {
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+ status = "okay";
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+};
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+
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+&hdmi1 {
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+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
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+ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
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+ status = "okay";
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+};
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+
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+&hdmi1_in {
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+ hdmi1_in_vp1: endpoint {
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+ remote-endpoint = <&vp1_out_hdmi1>;
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+ };
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+};
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+
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+&hdmi1_out {
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+ hdmi1_out_con: endpoint {
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+ remote-endpoint = <&hdmi1_con_in>;
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+ };
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+};
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+
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+&hdmi1_sound {
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+ status = "okay";
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+};
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+
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+&hdmi_receiver_cma {
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+ status = "okay";
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+};
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+
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+&hdmi_receiver {
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+ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
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+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&hdptxphy0 {
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+ status = "okay";
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+};
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+
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+&hdptxphy1 {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c0m2_xfer>;
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+ status = "okay";
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+
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+ vdd_cpu_big0_s0: regulator@42 {
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+ compatible = "rockchip,rk8602";
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+ reg = <0x42>;
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+ fcs,suspend-voltage-selector = <1>;
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+ regulator-name = "vdd_cpu_big0_s0";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <550000>;
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+ regulator-max-microvolt = <1050000>;
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+ regulator-ramp-delay = <2300>;
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+ vin-supply = <&vcc5v0_sys>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vdd_cpu_big1_s0: regulator@43 {
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+ compatible = "rockchip,rk8603", "rockchip,rk8602";
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+ reg = <0x43>;
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+ fcs,suspend-voltage-selector = <1>;
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+ regulator-name = "vdd_cpu_big1_s0";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <550000>;
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+ regulator-max-microvolt = <1050000>;
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+ regulator-ramp-delay = <2300>;
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+ vin-supply = <&vcc5v0_sys>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+};
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+
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+&i2c3 {
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+ status = "okay";
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+};
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+
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+&i2c4 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c4m1_xfer>;
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+ status = "okay";
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+
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+ usbc0: usb-typec@22 {
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+ compatible = "fcs,fusb302";
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+ reg = <0x22>;
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+ interrupt-parent = <&gpio3>;
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+ interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&usbc0_int>;
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+ vbus-supply = <&vcc12v_dcin>;
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+ /*
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+ * When the board is starting to send power-delivery messages
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+ * too late (5 seconds according to the specification), the
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+ * power-supply reacts with a hard-reset. That removes the
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+ * power from VBUS for some time, which resets te whole board.
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+ */
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+ status = "fail";
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+
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+ usb_con: connector {
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+ compatible = "usb-c-connector";
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+ label = "USB-C";
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+ data-role = "dual";
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+ power-role = "sink";
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+ try-power-role = "sink";
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+ op-sink-microwatt = <1000000>;
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+ sink-pdos =
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+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>,
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+ <PDO_VAR(5000, 20000, 5000)>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ usbc0_role_sw: endpoint {
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+ remote-endpoint = <&dwc3_0_role_switch>;
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+ };
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ usbc0_orien_sw: endpoint {
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+ remote-endpoint = <&usbdp_phy0_orientation_switch>;
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+ };
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ dp_altmode_mux: endpoint {
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+ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
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+ };
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+&i2c6 {
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+ status = "okay";
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+
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+ hym8563: rtc@51 {
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+ compatible = "haoyu,hym8563";
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+ reg = <0x51>;
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+ #clock-cells = <0>;
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+ clock-output-names = "hym8563";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hym8563_int>;
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+ interrupt-parent = <&gpio0>;
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+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
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+ wakeup-source;
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+ };
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+};
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+
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+&i2c7 {
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+ status = "okay";
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+
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+ es8316: audio-codec@11 {
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+ compatible = "everest,es8316";
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+ reg = <0x11>;
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+ clocks = <&cru I2S0_8CH_MCLKOUT>;
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+ clock-names = "mclk";
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+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
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+ assigned-clock-rates = <12288000>;
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+ #sound-dai-cells = <0>;
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+
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+ port {
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+ es8316_p0_0: endpoint {
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+ remote-endpoint = <&i2s0_8ch_p0_0>;
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+ };
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+ };
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+ };
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+};
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+
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+&i2s0_8ch {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2s0_lrck
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+ &i2s0_mclk
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+ &i2s0_sclk
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+ &i2s0_sdi0
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+ &i2s0_sdo0>;
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+ status = "okay";
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+
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+ i2s0_8ch_p0: port {
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+ i2s0_8ch_p0_0: endpoint {
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+ dai-format = "i2s";
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+ mclk-fs = <256>;
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+ remote-endpoint = <&es8316_p0_0>;
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+ };
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+ };
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+};
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+
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+&i2s5_8ch {
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+ status = "okay";
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+};
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+
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+&i2s6_8ch {
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+ status = "okay";
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+};
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+
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+&package_thermal {
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+ polling-delay = <1000>;
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+
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+ trips {
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+ package_fan0: package-fan0 {
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+ temperature = <55000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+
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+ package_fan1: package-fan1 {
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+ temperature = <65000>;
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+ hysteresis = <2000>;
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+ type = "active";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&package_fan0>;
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+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
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+ };
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+
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+ map1 {
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+ trip = <&package_fan1>;
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+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
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+ };
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+ };
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+};
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+
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+&pcie2x1l0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie2_0_rst>;
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+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
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+ status = "okay";
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+};
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+
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+&pcie2x1l2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie2_2_rst>;
|
|
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
|
+ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pcie30phy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pcie3x4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie3_rst>;
|
|
+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
|
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pd_gpu {
|
|
+ domain-supply = <&vdd_gpu_s0>;
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ hdmirx {
|
|
+ hdmirx_hpd: hdmirx-5v-detection {
|
|
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ hym8563 {
|
|
+ hym8563_int: hym8563-int {
|
|
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ led_rgb_b: led-rgb-b {
|
|
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sound {
|
|
+ hp_detect: hp-detect {
|
|
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie2 {
|
|
+ pcie2_0_rst: pcie2-0-rst {
|
|
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
|
|
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pcie2_2_rst: pcie2-2-rst {
|
|
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie3 {
|
|
+ pcie3_rst: pcie3-rst {
|
|
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
|
|
+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb {
|
|
+ usbc0_int: usbc0-int {
|
|
+ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+
|
|
+ vbus5v0_typec_en: vbus5v0-typec-en {
|
|
+ rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pwm1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&saradc {
|
|
+ vref-supply = <&avcc_1v8_s0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdhci {
|
|
+ bus-width = <8>;
|
|
+ no-sdio;
|
|
+ no-sd;
|
|
+ non-removable;
|
|
+ max-frequency = <150000000>;
|
|
+ mmc-hs200-1_8v;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sdmmc {
|
|
+ max-frequency = <200000000>;
|
|
+ no-sdio;
|
|
+ no-mmc;
|
|
+ bus-width = <4>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-sd-highspeed;
|
|
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
|
+ disable-wp;
|
|
+ sd-uhs-sdr104;
|
|
+ vmmc-supply = <&vcc_3v3_s3>;
|
|
+ vqmmc-supply = <&vccio_sd_s0>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&sfc {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&fspim2_pins>;
|
|
+ status = "okay";
|
|
+
|
|
+ flash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <104000000>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-tx-bus-width = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&spi2 {
|
|
+ status = "okay";
|
|
+ assigned-clocks = <&cru CLK_SPI2>;
|
|
+ assigned-clock-rates = <200000000>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
|
|
+ num-cs = <1>;
|
|
+
|
|
+ pmic@0 {
|
|
+ compatible = "rockchip,rk806";
|
|
+ spi-max-frequency = <1000000>;
|
|
+ reg = <0x0>;
|
|
+
|
|
+ interrupt-parent = <&gpio0>;
|
|
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
|
+
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
|
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
|
+
|
|
+ system-power-controller;
|
|
+
|
|
+ vcc1-supply = <&vcc5v0_sys>;
|
|
+ vcc2-supply = <&vcc5v0_sys>;
|
|
+ vcc3-supply = <&vcc5v0_sys>;
|
|
+ vcc4-supply = <&vcc5v0_sys>;
|
|
+ vcc5-supply = <&vcc5v0_sys>;
|
|
+ vcc6-supply = <&vcc5v0_sys>;
|
|
+ vcc7-supply = <&vcc5v0_sys>;
|
|
+ vcc8-supply = <&vcc5v0_sys>;
|
|
+ vcc9-supply = <&vcc5v0_sys>;
|
|
+ vcc10-supply = <&vcc5v0_sys>;
|
|
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
|
|
+ vcc12-supply = <&vcc5v0_sys>;
|
|
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
|
|
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
|
|
+ vcca-supply = <&vcc5v0_sys>;
|
|
+
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+
|
|
+ rk806_dvs1_null: dvs1-null-pins {
|
|
+ pins = "gpio_pwrctrl1";
|
|
+ function = "pin_fun0";
|
|
+ };
|
|
+
|
|
+ rk806_dvs2_null: dvs2-null-pins {
|
|
+ pins = "gpio_pwrctrl2";
|
|
+ function = "pin_fun0";
|
|
+ };
|
|
+
|
|
+ rk806_dvs3_null: dvs3-null-pins {
|
|
+ pins = "gpio_pwrctrl3";
|
|
+ function = "pin_fun0";
|
|
+ };
|
|
+
|
|
+ regulators {
|
|
+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <550000>;
|
|
+ regulator-max-microvolt = <950000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-name = "vdd_gpu_s0";
|
|
+ regulator-enable-ramp-delay = <400>;
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <550000>;
|
|
+ regulator-max-microvolt = <950000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-name = "vdd_cpu_lit_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_log_s0: dcdc-reg3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <675000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-name = "vdd_log_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ regulator-suspend-microvolt = <750000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <550000>;
|
|
+ regulator-max-microvolt = <950000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-name = "vdd_vdenc_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_ddr_s0: dcdc-reg5 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <675000>;
|
|
+ regulator-max-microvolt = <900000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-name = "vdd_ddr_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ regulator-suspend-microvolt = <850000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd2_ddr_s3: dcdc-reg6 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-name = "vdd2_ddr_s3";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_2v0_pldo_s3: dcdc-reg7 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <2000000>;
|
|
+ regulator-max-microvolt = <2000000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-name = "vdd_2v0_pldo_s3";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <2000000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_3v3_s3: dcdc-reg8 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-name = "vcc_3v3_s3";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <3300000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vddq_ddr_s0: dcdc-reg9 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-name = "vddq_ddr_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_1v8_s3: dcdc-reg10 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc_1v8_s3";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ avcc_1v8_s0: pldo-reg1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "avcc_1v8_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_1v8_s0: pldo-reg2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "vcc_1v8_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ avdd_1v2_s0: pldo-reg3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ regulator-name = "avdd_1v2_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vcc_3v3_s0: pldo-reg4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-name = "vcc_3v3_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vccio_sd_s0: pldo-reg5 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-ramp-delay = <12500>;
|
|
+ regulator-name = "vccio_sd_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pldo6_s3: pldo-reg6 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-name = "pldo6_s3";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <1800000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_0v75_s3: nldo-reg1 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <750000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-name = "vdd_0v75_s3";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-on-in-suspend;
|
|
+ regulator-suspend-microvolt = <750000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_ddr_pll_s0: nldo-reg2 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <850000>;
|
|
+ regulator-max-microvolt = <850000>;
|
|
+ regulator-name = "vdd_ddr_pll_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ regulator-suspend-microvolt = <850000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ avdd_0v75_s0: nldo-reg3 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <750000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-name = "avdd_0v75_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_0v85_s0: nldo-reg4 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <850000>;
|
|
+ regulator-max-microvolt = <850000>;
|
|
+ regulator-name = "vdd_0v85_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ vdd_0v75_s0: nldo-reg5 {
|
|
+ regulator-always-on;
|
|
+ regulator-boot-on;
|
|
+ regulator-min-microvolt = <750000>;
|
|
+ regulator-max-microvolt = <750000>;
|
|
+ regulator-name = "vdd_0v75_s0";
|
|
+
|
|
+ regulator-state-mem {
|
|
+ regulator-off-in-suspend;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&tsadc {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ pinctrl-0 = <&uart2m0_xfer>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy0_otg {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy1_otg {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy2 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy2_host {
|
|
+ /* connected to USB hub, which is powered by vcc5v0_sys */
|
|
+ phy-supply = <&vcc5v0_sys>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&u2phy3_host {
|
|
+ phy-supply = <&vcc5v0_host>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdp_phy1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbdp_phy0 {
|
|
+ mode-switch;
|
|
+ orientation-switch;
|
|
+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
|
|
+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ usbdp_phy0_orientation_switch: endpoint@0 {
|
|
+ reg = <0>;
|
|
+ remote-endpoint = <&usbc0_orien_sw>;
|
|
+ };
|
|
+
|
|
+ usbdp_phy0_dp_altmode_mux: endpoint@1 {
|
|
+ reg = <1>;
|
|
+ remote-endpoint = <&dp_altmode_mux>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&usb_host0_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_ohci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host0_xhci {
|
|
+ usb-role-switch;
|
|
+ status = "okay";
|
|
+
|
|
+ port {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dwc3_0_role_switch: endpoint {
|
|
+ remote-endpoint = <&usbc0_role_sw>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&usb_host1_ehci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host1_ohci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host1_xhci {
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb_host2_xhci {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vop_mmu {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&vp0 {
|
|
+ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
|
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
|
+ remote-endpoint = <&hdmi0_in_vp0>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&vp1 {
|
|
+ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
|
|
+ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
|
|
+ remote-endpoint = <&hdmi1_in_vp1>;
|
|
+ };
|
|
+};
|
|
--
|
|
GitLab
|