214 lines
6.3 KiB
Diff
214 lines
6.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Paolo Sabatino <[email protected]>
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Date: Sun, 30 Jun 2024 16:46:51 +0200
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Subject: OTG/EHCI USB support for rk322x
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---
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arch/arm/mach-rockchip/rk322x/syscon_rk322x.c | 3 +
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drivers/clk/rockchip/clk_rk322x.c | 121 ++++++++++
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drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 32 +++
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3 files changed, 156 insertions(+)
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diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
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index 111111111111..222222222222 100644
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--- a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
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+++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
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@@ -17,5 +17,8 @@ static const struct udevice_id rk322x_syscon_ids[] = {
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U_BOOT_DRIVER(syscon_rk322x) = {
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.name = "rk322x_syscon",
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.id = UCLASS_SYSCON,
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+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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+ .bind = dm_scan_fdt_dev,
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+#endif
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.of_match = rk322x_syscon_ids,
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};
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diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
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index 111111111111..222222222222 100644
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--- a/drivers/clk/rockchip/clk_rk322x.c
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+++ b/drivers/clk/rockchip/clk_rk322x.c
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@@ -596,10 +596,131 @@ static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
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return -ENOENT;
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}
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+static int rk322x_clk_enable(struct clk *clk)
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+{
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+
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+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
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+ struct rk322x_cru *cru = priv->cru;
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+
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+ switch (clk->id) {
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+ case SCLK_OTGPHY0:
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+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(5));
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+ break;
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+ case SCLK_OTGPHY1:
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+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(6));
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+ break;
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+ case HCLK_OTG:
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+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(12));
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+ break;
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+ case HCLK_HOST0:
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+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(6));
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+ break;
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+ case HCLK_HOST1:
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+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(8));
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+ break;
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+ case HCLK_HOST2:
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+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(10));
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+ break;
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+ case SCLK_MAC:
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+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(6));
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+ break;
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+ case SCLK_MAC_SRC:
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+ rk_clrreg(&cru->cru_clkgate_con[1], BIT(7));
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+ break;
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+ case SCLK_MAC_RX:
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+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(5));
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+ break;
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+ case SCLK_MAC_TX:
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+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(6));
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+ break;
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+ case SCLK_MAC_REF:
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+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(3));
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+ break;
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+ case SCLK_MAC_REFOUT:
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+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(4));
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+ break;
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+ case SCLK_MAC_PHY:
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+ rk_clrreg(&cru->cru_clkgate_con[5], BIT(7));
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+ break;
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+ case ACLK_GMAC:
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+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(4));
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+ break;
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+ case PCLK_GMAC:
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+ rk_clrreg(&cru->cru_clkgate_con[11], BIT(5));
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+ break;
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+ default:
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+ log_debug("%s: unsupported clk %ld\n", __func__, clk->id);
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+ return -ENOENT;
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+ }
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+
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+ return 0;
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+
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+}
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+
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+static int rk322x_clk_disable(struct clk *clk)
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+{
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+
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+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
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+ struct rk322x_cru *cru = priv->cru;
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+
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+ switch (clk->id) {
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+ case SCLK_OTGPHY0:
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+ rk_setreg(&cru->cru_clkgate_con[1], BIT(5));
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+ break;
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+ case SCLK_OTGPHY1:
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+ rk_setreg(&cru->cru_clkgate_con[1], BIT(6));
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+ break;
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+ case HCLK_OTG:
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+ rk_setreg(&cru->cru_clkgate_con[11], BIT(12));
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+ break;
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+ case HCLK_HOST0:
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+ rk_setreg(&cru->cru_clkgate_con[11], BIT(6));
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+ break;
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+ case HCLK_HOST1:
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+ rk_setreg(&cru->cru_clkgate_con[11], BIT(8));
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+ break;
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+ case HCLK_HOST2:
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+ rk_setreg(&cru->cru_clkgate_con[11], BIT(10));
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+ break;
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+ case SCLK_MAC_SRC:
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+ rk_setreg(&cru->cru_clkgate_con[1], BIT(7));
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+ break;
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+ case SCLK_MAC_RX:
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+ rk_setreg(&cru->cru_clkgate_con[5], BIT(5));
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+ break;
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+ case SCLK_MAC_TX:
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+ rk_setreg(&cru->cru_clkgate_con[5], BIT(6));
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+ break;
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+ case SCLK_MAC_REF:
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+ rk_setreg(&cru->cru_clkgate_con[5], BIT(3));
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+ break;
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+ case SCLK_MAC_REFOUT:
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+ rk_setreg(&cru->cru_clkgate_con[5], BIT(4));
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+ break;
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+ case SCLK_MAC_PHY:
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+ rk_setreg(&cru->cru_clkgate_con[5], BIT(7));
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+ break;
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+ case ACLK_GMAC:
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+ rk_setreg(&cru->cru_clkgate_con[11], BIT(4));
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+ break;
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+ case PCLK_GMAC:
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+ rk_setreg(&cru->cru_clkgate_con[11], BIT(5));
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+ break;
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+ default:
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+ log_debug("%s: unsupported clk %ld\n", __func__, clk->id);
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+ return -ENOENT;
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+ }
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+
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+ return 0;
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+
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+}
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+
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static struct clk_ops rk322x_clk_ops = {
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.get_rate = rk322x_clk_get_rate,
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.set_rate = rk322x_clk_set_rate,
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.set_parent = rk322x_clk_set_parent,
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+ .enable = rk322x_clk_enable,
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+ .disable = rk322x_clk_disable
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};
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static int rk322x_clk_of_to_plat(struct udevice *dev)
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diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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index 111111111111..222222222222 100644
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--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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@@ -361,6 +361,34 @@ static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
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{ /* sentinel */ }
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};
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+static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
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+ {
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+ .reg = 0x760,
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+ .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
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+ .port_cfgs = {
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+ [USB2PHY_PORT_OTG] = {
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+ .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 },
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+ },
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+ [USB2PHY_PORT_HOST] = {
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+ .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 },
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+ }
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+ },
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+ },
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+ {
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+ .reg = 0x800,
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+ .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
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+ .port_cfgs = {
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+ [USB2PHY_PORT_OTG] = {
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+ .phy_sus = { 0x800, 15, 0, 0, 0x1d1 },
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+ },
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+ [USB2PHY_PORT_HOST] = {
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+ .phy_sus = { 0x804, 15, 0, 0, 0x1d1 },
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+ }
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+ },
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+ },
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+ { /* sentinel */ }
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+};
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+
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static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
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{
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.reg = 0xe450,
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@@ -466,6 +494,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
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.compatible = "rockchip,rk3328-usb2phy",
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.data = (ulong)&rk3328_usb2phy_cfgs,
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},
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+ {
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+ .compatible = "rockchip,rk3228-usb2phy",
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+ .data = (ulong)&rk3228_phy_cfgs,
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+ },
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{
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.compatible = "rockchip,rk3399-usb2phy",
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.data = (ulong)&rk3399_usb2phy_cfgs,
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--
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Armbian
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