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BPI-CM9-Linux/build/patch/u-boot/u-boot-genio/0016-arm-dts-add-radxa-nio-12l.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Julien Massot <[email protected]>
Date: Mon, 3 Feb 2025 14:33:01 +0100
Subject: arm: dts: add radxa nio 12l
Signed-off-by: Stephen Chen <[email protected]>
(cherry picked from commit 537815754b4f715c240fff9c6a59836b1ffe7b4a)
---
arch/arm/dts/Makefile | 5 +-
arch/arm/dts/genio-1200-radxa-nio-12l-d16.dts | 18 +
arch/arm/dts/genio-1200-radxa-nio-12l-d4.dts | 18 +
arch/arm/dts/genio-1200-radxa-nio-12l-d8.dts | 18 +
arch/arm/dts/genio-1200-radxa-nio-12l.dtsi | 265 ++++++++++
5 files changed, 323 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 111111111111..222222222222 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1248,7 +1248,10 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
genio-720-evk-ufs-qspi.dtb \
genio-1200-evk.dtb \
genio-1200-evk-ufs.dtb \
- genio-1200-evk-ufs-qspi.dtb
+ genio-1200-evk-ufs-qspi.dtb \
+ genio-1200-radxa-nio-12l-d4.dtb \
+ genio-1200-radxa-nio-12l-d8.dtb \
+ genio-1200-radxa-nio-12l-d16.dtb
dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb
dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
diff --git a/arch/arm/dts/genio-1200-radxa-nio-12l-d16.dts b/arch/arm/dts/genio-1200-radxa-nio-12l-d16.dts
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm/dts/genio-1200-radxa-nio-12l-d16.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Macpaul Lin <[email protected]>
+ * Copyright (C) 2024 Radxa Limited
+ */
+
+/dts-v1/;
+
+#include "genio-1200-radxa-nio-12l.dtsi"
+
+/ {
+ memory@40000000 {
+ /* 16GB */
+ device_type = "memory";
+ reg = <0 0x40000000 4 0x00000000>;
+ };
+};
diff --git a/arch/arm/dts/genio-1200-radxa-nio-12l-d4.dts b/arch/arm/dts/genio-1200-radxa-nio-12l-d4.dts
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm/dts/genio-1200-radxa-nio-12l-d4.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Macpaul Lin <[email protected]>
+ * Copyright (C) 2024 Radxa Limited
+ */
+
+/dts-v1/;
+
+#include "genio-1200-radxa-nio-12l.dtsi"
+
+/ {
+ memory@40000000 {
+ /* 4GB */
+ device_type = "memory";
+ reg = <0 0x40000000 1 0x00000000>;
+ };
+};
diff --git a/arch/arm/dts/genio-1200-radxa-nio-12l-d8.dts b/arch/arm/dts/genio-1200-radxa-nio-12l-d8.dts
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm/dts/genio-1200-radxa-nio-12l-d8.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Macpaul Lin <[email protected]>
+ * Copyright (C) 2024 Radxa Limited
+ */
+
+/dts-v1/;
+
+#include "genio-1200-radxa-nio-12l.dtsi"
+
+/ {
+ memory@40000000 {
+ /* 8GB */
+ device_type = "memory";
+ reg = <0 0x40000000 2 0x00000000>;
+ };
+};
diff --git a/arch/arm/dts/genio-1200-radxa-nio-12l.dtsi b/arch/arm/dts/genio-1200-radxa-nio-12l.dtsi
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm/dts/genio-1200-radxa-nio-12l.dtsi
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2021 BayLibre SAS.
+ * Author: Fabien Parent <[email protected]>
+ * Copyright (C) 2024 Radxa Limited
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8195.dtsi"
+
+/ {
+ model = "Radxa NIO 12L";
+ compatible = "radxa,nio-12l", "mediatek,mt8195";
+
+ memory@40000000 {
+ /* 8GB */
+ device_type = "memory";
+ reg = <0 0x40000000 2 0x00000000>;
+ };
+
+ firmware: firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+
+ dsi_reserved: dsi@60000000 {
+ reg = <0 0x60000000 0 0x02000000>;
+ no-map;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pio {
+ i2c0_pins: i2c0 {
+ pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
+ <PINMUX_GPIO9__FUNC_SCL0>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ i2c1_pins: i2c1 {
+ pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
+ <PINMUX_GPIO11__FUNC_SCL1>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ i2c2_pins: i2c2 {
+ pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
+ <PINMUX_GPIO13__FUNC_SCL2>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ i2c3_pins: i2c3 {
+ pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
+ <PINMUX_GPIO15__FUNC_SCL3>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ i2c6_pins: i2c6 {
+ pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
+ <PINMUX_GPIO26__FUNC_SCL6>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ ethdefault: ethdefault {
+ txdpins {
+ pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+ <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+ <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+ <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ ccpins {
+ pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+ <PINMUX_GPIO88__FUNC_GBE_TXEN>,
+ <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+ <PINMUX_GPIO86__FUNC_GBE_RXC>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ };
+ rxdpins {
+ pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+ <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+ <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+ <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+ };
+ mdiopins {
+ pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+ <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+ input-enable;
+ };
+ powerpins {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ output-high;
+ };
+ phyresetpin {
+ pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
+ };
+ };
+
+ ethsleep: ethsleep {
+ txdpins {
+ pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+ <PINMUX_GPIO78__FUNC_GPIO78>,
+ <PINMUX_GPIO79__FUNC_GPIO79>,
+ <PINMUX_GPIO80__FUNC_GPIO80>;
+ };
+ ccpins {
+ pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+ <PINMUX_GPIO88__FUNC_GPIO88>,
+ <PINMUX_GPIO87__FUNC_GPIO87>,
+ <PINMUX_GPIO86__FUNC_GPIO86>;
+ };
+ rxdpins {
+ pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+ <PINMUX_GPIO82__FUNC_GPIO82>,
+ <PINMUX_GPIO83__FUNC_GPIO83>,
+ <PINMUX_GPIO84__FUNC_GPIO84>;
+ };
+ mdiopins {
+ pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+ <PINMUX_GPIO90__FUNC_GPIO90>;
+ input-disable;
+ bias-disable;
+ };
+ powerpins {
+ pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+ <PINMUX_GPIO92__FUNC_GPIO92>;
+ input-disable;
+ bias-disable;
+ };
+ phyresetpin {
+ pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
+ input-disable;
+ bias-disable;
+ };
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&ufs {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&i2c6 {
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c6_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&eth {
+ phy-mode ="rgmii-rxid";
+ phy-handle = <&ethphy0>;
+ mediatek,tx-delay-ps = <2030>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&ethdefault>;
+ pinctrl-1 = <&ethsleep>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethphy0@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ };
+ };
+};
--
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