202 lines
3.9 KiB
Plaintext
202 lines
3.9 KiB
Plaintext
This document describes overlays provided in the kernel packages
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For generic Armbian overlays documentation please see
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https://docs.armbian.com/Hardware_Allwinner_overlays/
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### Platform:
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sun50i-a64 (Allwinner A64)
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### Platform details:
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Supported pin banks: PB, PC, PD, PH
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Both SPI controllers have only one hardware CS pin exposed,
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adding fixed software (GPIO) chip selects is possible with a separate overlay
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I2C controller 2 (PE14, PE15) pins are used for non-I2C CSI functions or are not available
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on supported boards, so this controller is not supported in provided overlays
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### Provided overlays:
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- i2c0
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- i2c1
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- pine64-7inch-lcd
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- pps-gpio
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- spi-add-cs1
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- spi-jedec-nor
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- spi-spidev
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- uart1
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- uart2
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- uart3
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- uart4
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- w1-gpio
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### Overlay details:
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### i2c0
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Activates TWI/I2C bus 0
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I2C0 pins (SCL, SDA): PH0, PH1
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### i2c1
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Activates TWI/I2C bus 1
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I2C1 pins (SCL, SDA): PH2, PH3
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### pine64-7inch-lcd
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Activates the Pine64 7" LCD on pine64/pine64so boards
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### pps-gpio
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Activates pulse-per-second GPIO client
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Parameters:
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param_pps_pin (pin)
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Pin PPS source is connected to
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Optional
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Default: PD4
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param_pps_falling_edge (bool)
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Assert by falling edge
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Optional
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Default: 0
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When set (to 1), assert is indicated by a falling edge
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(instead of by a rising edge)
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### spi-add-cs1
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Adds support for using SPI chip select 1 with GPIO for both SPI controllers
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Respective GPIO will be claimed only if controller is enabled by another overlay
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This overlay is required for using chip select 1 with other SPI overlays
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SPI 0 pins (CS1): PB6
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SPI 1 pins (CS1): PD6
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### spi-jedec-nor
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Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
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supported by the kernel SPI NOR driver
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SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
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SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0
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Parameters:
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param_spinor_spi_bus (int)
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SPI bus to activate SPI NOR flash support on
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Required
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Supported values: 0, 1
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param_spinor_spi_cs (int)
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SPI chip select number
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Optional
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Default: 0
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Supported values: 0, 1
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Using chip select 1 requires using "spi-add-cs1" overlay
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param_spinor_max_freq (int)
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Maximum SPI frequency
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Optional
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Default: 1000000
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Range: 3000 - 100000000
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### spi-spidev
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Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
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where X is the bus number and Y is the CS number
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SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
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SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0
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Parameters:
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param_spidev_spi_bus (int)
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SPI bus to activate SPIdev support on
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Required
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Supported values: 0, 1
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param_spidev_spi_cs (int)
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SPI chip select number
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Optional
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Default: 0
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Supported values: 0, 1
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Using chip select 1 requires using "spi-add-cs1" overlay
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param_spidev_max_freq (int)
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Maximum SPIdev frequency
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Optional
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Default: 1000000
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Range: 3000 - 100000000
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### uart1
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Activates serial port 1 (/dev/ttyS1)
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UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
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Parameters:
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param_uart1_rtscts (bool)
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Enable RTS and CTS pins
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Optional
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Default: 0
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Set to 1 to enable
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### uart2
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Activates serial port 2 (/dev/ttyS2)
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UART 2 pins (TX, RX, RTS, CTS): PB0, PB1, PB2, PB3
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Parameters:
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param_uart2_rtscts (bool)
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Enable RTS and CTS pins
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Optional
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Default: 0
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Set to 1 to enable CTS and RTS pins
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### uart3
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Activates serial port 3 (/dev/ttyS3)
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UART 3 pins (TX, RX): PD0, PD1
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### uart4
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Activates serial port 4 (/dev/ttyS4)
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UART 4 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5
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Parameters:
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param_uart2_rtscts (bool)
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Enable RTS and CTS pins
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Optional
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Default: 0
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Set to 1 to enable CTS and RTS pins
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### w1-gpio
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Activates 1-Wire GPIO master
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Requires external pull-up resistor on data pin
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Parameters:
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param_w1_pin (pin)
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Data pin for 1-Wire master
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Optional
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Default: PD4
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param_w1_pin_int_pullup (bool)
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Enable internal pull-up for the data pin
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Optional
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Default: 0
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Set to 1 to enable the pull-up
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This option should not be used with multiple devices, parasite power setup
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or long wires - please use external pull-up resistor instead
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