67 lines
1.9 KiB
Diff
67 lines
1.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <[email protected]>
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Date: Fri, 21 Feb 2025 00:57:58 +0000
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Subject: dt-bindings: power: Add Allwinner H6/H616 PRCM PPU
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The Allwinner H6 and some later SoCs contain some bits in the PRCM (Power
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Reset Clock Management) block that control some power domains.
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Those power domains include the one for the GPU, the PLLs and some
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analogue circuits.
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Signed-off-by: Andre Przywara <[email protected]>
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---
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Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml | 42 ++++++++++
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1 file changed, 42 insertions(+)
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diff --git a/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml
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new file mode 100644
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index 000000000000..111111111111
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml
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@@ -0,0 +1,42 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/power/allwinner,sun50i-h6-prcm-ppu.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Allwinner SoCs PRCM power domain controller
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+
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+maintainers:
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+ - Andre Przywara <[email protected]>
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+
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+description:
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+ The Allwinner Power Reset Clock Management (PRCM) unit contains bits to
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+ control a few power domains.
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+
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+properties:
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+ compatible:
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+ enum:
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+ - allwinner,sun50i-h6-prcm-ppu
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+ - allwinner,sun50i-h616-prcm-ppu
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+ - allwinner,sun55i-a523-prcm-ppu
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+
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+ reg:
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+ maxItems: 1
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+
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+ '#power-domain-cells':
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+ const: 1
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+
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+required:
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+ - compatible
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+ - reg
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+ - '#power-domain-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ prcm_ppu: power-controller@7010210 {
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+ compatible = "allwinner,sun50i-h616-prcm-ppu";
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+ reg = <0x07010250 0x10>;
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+ #power-domain-cells = <1>;
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+ };
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--
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Armbian
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