54 lines
1.6 KiB
Diff
54 lines
1.6 KiB
Diff
From 21978408039e18129cad415257317407aa6482f3 Mon Sep 17 00:00:00 2001
|
|
From: Teguh Sobirin <[email protected]>
|
|
Date: Wed, 12 Feb 2025 17:53:48 +0800
|
|
Subject: [PATCH] arm64: dts: qcom: sm8550: add UART15
|
|
|
|
Signed-off-by: Teguh Sobirin <[email protected]>
|
|
---
|
|
arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 ++++++++++++++++++++++
|
|
1 file changed, 22 insertions(+)
|
|
|
|
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
|
|
index 42cd9649a962..86fc8bd0af1f 100644
|
|
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
|
|
@@ -1133,6 +1133,20 @@ spi15: spi@89c000 {
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ uart15: serial@89c000 {
|
|
+ compatible = "qcom,geni-uart";
|
|
+ reg = <0 0x89c000 0 0x4000>;
|
|
+ clock-names = "se";
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&qup_uart15_default>;
|
|
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
|
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
|
|
+ interconnect-names = "qup-core", "qup-config";
|
|
+ status = "disabled";
|
|
+ };
|
|
};
|
|
|
|
i2c_master_hub_0: geniqup@9c0000 {
|
|
@@ -4325,6 +4339,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
|
|
bias-pull-down;
|
|
};
|
|
|
|
+ qup_uart15_default: qup-uart15-default-state {
|
|
+ /* TX, RX */
|
|
+ pins = "gpio74", "gpio75";
|
|
+ function = "qup2_se7";
|
|
+ drive-strength = <2>;
|
|
+ bias-pull-up;
|
|
+ };
|
|
+
|
|
sdc2_sleep: sdc2-sleep-state {
|
|
clk-pins {
|
|
pins = "sdc2_clk";
|
|
--
|
|
2.34.1
|
|
|