118 lines
4.3 KiB
Diff
118 lines
4.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Hans Zhang <[email protected]>
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Date: Fri, 28 Nov 2025 01:09:08 +0800
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Subject: PCI: dwc: Remove redundant MPS configuration
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The Meson PCIe controller driver manually configures maximum payload
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size (MPS) through meson_set_max_payload, duplicating functionality now
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centralized in the PCI core. Deprecating redundant code simplifies the
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driver and aligns it with the consolidated MPS management strategy,
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improving long-term maintainability.
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Signed-off-by: Hans Zhang <[email protected]>
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---
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drivers/pci/controller/dwc/pci-meson.c | 17 ----------
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1 file changed, 17 deletions(-)
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diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c
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index 111111111111..222222222222 100644
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--- a/drivers/pci/controller/dwc/pci-meson.c
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+++ b/drivers/pci/controller/dwc/pci-meson.c
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@@ -272,22 +272,6 @@ static int meson_size_to_payload(struct meson_pcie *mp, int size)
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return fls(size) - 8;
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}
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-static void meson_set_max_payload(struct meson_pcie *mp, int size)
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-{
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- struct dw_pcie *pci = &mp->pci;
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- u32 val;
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- u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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- int max_payload_size = meson_size_to_payload(mp, size);
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-
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- val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
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- val &= ~PCI_EXP_DEVCTL_PAYLOAD;
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- dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
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-
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- val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
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- val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
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- dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
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-}
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-
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static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
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{
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struct dw_pcie *pci = &mp->pci;
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@@ -362,7 +346,6 @@ static int meson_pcie_host_init(struct dw_pcie_rp *pp)
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pp->bridge->ops = &meson_pci_ops;
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- meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
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meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
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return 0;
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--
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Armbian
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Hans Zhang <[email protected]>
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Date: Fri, 28 Nov 2025 01:09:07 +0800
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Subject: PCI: Configure Root Port MPS during host probing
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Current PCIe initialization logic may leave Root Ports operating with
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non-optimal Maximum Payload Size (MPS) settings. The existing code in
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pci_configure_mps() returns early for devices without an upstream bridge
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which includes Root Ports, so their MPS values remain at firmware
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defaults. This fails to utilize the controller's full capabilities,
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leading to suboptimal data transfer efficiency across the PCIe hierarchy.
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With this patch, during the host controller probing phase:
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- When PCIe bus tuning is enabled (not PCIE_BUS_TUNE_OFF) and not
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PCIE_BUS_PEER2PEER (which requires the default 128 bytes for optimal
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peer-to-peer operation), and
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- The device is a Root Port, the Root Port's MPS is set to its maximum
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supported value.
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Note that this initial maximum MPS setting may be reduced later, during
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downstream device enumeration, if any downstream device does not support
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the Root Port's maximum MPS.
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This change ensures Root Ports are initialized to their maximum MPS before
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downstream devices negotiate MPS, while maintaining backward compatibility
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via the PCIE_BUS_TUNE_OFF check and not interfering with the
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PCIE_BUS_PEER2PEER strategy.
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Suggested-by: Niklas Cassel <[email protected]>
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Suggested-by: Manivannan Sadhasivam <[email protected]>
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Signed-off-by: Hans Zhang <[email protected]>
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Tested-by: Mahesh Vaidya <[email protected]>
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Tested-by: Shawn Lin <[email protected]>
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---
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drivers/pci/probe.c | 12 ++++++++++
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1 file changed, 12 insertions(+)
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diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
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index 111111111111..222222222222 100644
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--- a/drivers/pci/probe.c
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+++ b/drivers/pci/probe.c
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@@ -2203,6 +2203,18 @@ static void pci_configure_mps(struct pci_dev *dev)
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return;
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}
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+ /*
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+ * Unless MPS strategy is PCIE_BUS_TUNE_OFF (don't touch MPS at all) or
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+ * PCIE_BUS_PEER2PEER (use minimum MPS for peer-to-peer), set Root Ports'
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+ * MPS to their maximum supported value. Depending on the MPS strategy
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+ * and MPSS of downstream devices, a Root Port's MPS may be reduced
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+ * later during device enumeration.
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+ */
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+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
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+ pcie_bus_config != PCIE_BUS_TUNE_OFF &&
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+ pcie_bus_config != PCIE_BUS_PEER2PEER)
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+ pcie_set_mps(dev, 128 << dev->pcie_mpss);
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+
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if (!bridge || !pci_is_pcie(bridge))
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return;
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--
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Armbian
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