185 lines
4.1 KiB
Diff
185 lines
4.1 KiB
Diff
From 2292b669f7c265c39f2836b894270305b1d32a39 Mon Sep 17 00:00:00 2001
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From: Frank Wunderlich <[email protected]>
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Date: Sat, 1 Feb 2025 15:18:12 +0100
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Subject: [PATCH 27/84] arm64: dts: mediatek: mt7988: add switch node
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Add mt7988 builtin mt753x switch nodes.
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Signed-off-by: Daniel Golle <[email protected]>
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Signed-off-by: Frank Wunderlich <[email protected]>
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Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
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---
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v4:
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- drop phy-mode for gsw-phy
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- reorder phy-mode after phy-handle
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- drop interrupt parent from switch
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v2:
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- drop labels and led-function too (have to be in board)
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 148 ++++++++++++++++++++++
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1 file changed, 148 insertions(+)
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diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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index 897b5a82b53e..366203a72d6d 100644
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -742,6 +742,154 @@ ethsys: clock-controller@15000000 {
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#reset-cells = <1>;
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};
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+ switch: switch@15020000 {
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+ compatible = "mediatek,mt7988-switch";
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+ reg = <0 0x15020000 0 0x8000>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ gsw_port0: port@0 {
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+ reg = <0>;
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+ phy-handle = <&gsw_phy0>;
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+ phy-mode = "internal";
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+ };
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+
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+ gsw_port1: port@1 {
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+ reg = <1>;
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+ phy-handle = <&gsw_phy1>;
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+ phy-mode = "internal";
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+ };
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+
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+ gsw_port2: port@2 {
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+ reg = <2>;
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+ phy-handle = <&gsw_phy2>;
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+ phy-mode = "internal";
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+ };
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+
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+ gsw_port3: port@3 {
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+ reg = <3>;
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+ phy-handle = <&gsw_phy3>;
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+ phy-mode = "internal";
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ ethernet = <&gmac0>;
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+ phy-mode = "internal";
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+
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+ fixed-link {
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+ speed = <10000>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+ };
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ mediatek,pio = <&pio>;
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+
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+ gsw_phy0: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+ interrupts = <0>;
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+ nvmem-cells = <&phy_calibration_p0>;
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+ nvmem-cell-names = "phy-cal-data";
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+
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+ leds {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ gsw_phy0_led0: led@0 {
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+ reg = <0>;
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+ status = "disabled";
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+ };
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+
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+ gsw_phy0_led1: led@1 {
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+ reg = <1>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ gsw_phy1: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ interrupts = <1>;
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+ nvmem-cells = <&phy_calibration_p1>;
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+ nvmem-cell-names = "phy-cal-data";
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+
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+ leds {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ gsw_phy1_led0: led@0 {
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+ reg = <0>;
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+ status = "disabled";
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+ };
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+
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+ gsw_phy1_led1: led@1 {
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+ reg = <1>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ gsw_phy2: ethernet-phy@2 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <2>;
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+ interrupts = <2>;
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+ nvmem-cells = <&phy_calibration_p2>;
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+ nvmem-cell-names = "phy-cal-data";
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+
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+ leds {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ gsw_phy2_led0: led@0 {
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+ reg = <0>;
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+ status = "disabled";
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+ };
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+
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+ gsw_phy2_led1: led@1 {
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+ reg = <1>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ gsw_phy3: ethernet-phy@3 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <3>;
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+ interrupts = <3>;
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+ nvmem-cells = <&phy_calibration_p3>;
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+ nvmem-cell-names = "phy-cal-data";
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+
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+ leds {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ gsw_phy3_led0: led@0 {
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+ reg = <0>;
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+ status = "disabled";
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+ };
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+
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+ gsw_phy3_led1: led@1 {
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+ reg = <1>;
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+ status = "disabled";
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+ };
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+ };
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+ };
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+ };
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+ };
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+
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ethwarp: clock-controller@15031000 {
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compatible = "mediatek,mt7988-ethwarp";
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reg = <0 0x15031000 0 0x1000>;
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--
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2.30.2
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