97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_CLOCK_A9_H
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#define __DT_BINDINGS_CLOCK_A9_H
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/*
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* FIXME: In CCF, the clock with clkid equal to 0 is marked as a non-valid clock,
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* so here the clkid starts with 1.
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*/
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#define CLKID_FIX_PLL 0
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#define CLKID_FCLK_DIV2 1
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#define CLKID_FCLK_DIV3 2
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#define CLKID_FCLK_DIV4 3
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#define CLKID_FCLK_DIV5 4
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#define CLKID_FCLK_DIV7 5
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#define CLKID_FCLK_DIV2P5 6
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#define CLKID_SYS_CLK 7
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#define CLKID_GP0_PLL 8
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#define CLKID_HIFI_PLL 9
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#define CLKID_SAR_ADC_SEL 10
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#define CLKID_SAR_ADC_DIV 11
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#define CLKID_SAR_ADC 12
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#define CLKID_SPISG_0_SEL 13
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#define CLKID_SPISG_0_DIV 14
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#define CLKID_SPISG_0 15
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#define CLKID_SPISG_1_SEL 16
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#define CLKID_SPISG_1_DIV 17
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#define CLKID_SPISG_1 18
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#define CLKID_SPISG_2_SEL 19
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#define CLKID_SPISG_2_DIV 20
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#define CLKID_SPISG_2 21
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#define CLKID_SD_EMMC_A_SEL 22
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#define CLKID_SD_EMMC_A_DIV 23
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#define CLKID_SD_EMMC_A 24
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#define CLKID_SD_EMMC_B_SEL 25
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#define CLKID_SD_EMMC_B_DIV 26
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#define CLKID_SD_EMMC_B 27
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#define CLKID_SD_EMMC_C_SEL 28
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#define CLKID_SD_EMMC_C_DIV 29
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#define CLKID_SD_EMMC_C 30
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#define CLKID_ETH_RMII_DIV 31
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#define CLKID_ETH_RMII 32
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#define CLKID_TS_DIV 33
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#define CLKID_TS 34
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#define CLKID_AMFC_SEL 35
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#define CLKID_AMFC_DIV 36
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#define CLKID_AMFC 37
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#define CLKID_VPU_0_SEL 38
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#define CLKID_VPU_0_DIV 39
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#define CLKID_VPU_0 40
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#define CLKID_VPU_1_SEL 41
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#define CLKID_VPU_1_DIV 42
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#define CLKID_VPU_1 43
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#define CLKID_VPU 44
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#define CLKID_VAPB_0_SEL 45
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#define CLKID_VAPB_0_DIV 46
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#define CLKID_VAPB_0 47
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#define CLKID_VAPB_1_SEL 48
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#define CLKID_VAPB_1_DIV 49
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#define CLKID_VAPB_1 50
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#define CLKID_VAPB 51
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#define CLKID_GE2D 52
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#define CLKID_SYS_ETH_PHY 53
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#define CLKID_SYS_ETH_AXI 54
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#define CLKID_SYS_SD_EMMC_A 55
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#define CLKID_SYS_SD_EMMC_B 56
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#define CLKID_SYS_SD_EMMC_C 57
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#define CLKID_SYS_ETH 58
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#define CLKID_SYS_TS_A55 59
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#define CLKID_SYS_TS_CORE 60
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#define CLKID_SYS_TS_PLL 61
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#define CLKID_SYS_GE2D 62
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#define CLKID_SYS_SPISG_0 63
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#define CLKID_SYS_VPU_INTR 64
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#define CLKID_SYS_SAR_ADC 65
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#define CLKID_I3C_SEL 66
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#define CLKID_I3C_DIV 67
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#define CLKID_I3C 68
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#define CLKID_SYS_PCIE_MAC_A 69
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#define CLKID_SYS_PCIE_PHY 70
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#define CLKID_SYS_PCIE_MAC_B 71
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#define CLKID_SYS_PERIPH 72
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#define CLKID_PCIE0_TL_SEL 73
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#define CLKID_PCIE0_TL_DIV 74
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#define CLKID_PCIE0_TL 75
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#define CLKID_PCIE1_TL_SEL 76
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#define CLKID_PCIE1_TL_DIV 77
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#define CLKID_PCIE1_TL 78
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#define CLKID_PP_SEL 79
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#define CLKID_PP_DIV 80
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#define CLKID_PP 81
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#endif /* __A9_CLKC_H */
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