66 lines
2.0 KiB
C
66 lines
2.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __RAMDUMP_H__
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#define __RAMDUMP_H__
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/* PAGE_SHIFT determines the page size */
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#define PAGE_SHIFT 12
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/* align addr on a size boundary - adjust address up/down if needed */
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#define _ALIGN_UP(addr, size) (((addr) + ((size) - 1)) & (~((typeof(addr))(size) - 1)))
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#define _ALIGN_DOWN(addr, size) ((addr) & (~((typeof(addr))(size) - 1)))
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/* align addr on a size boundary - adjust address up if needed */
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#define _ALIGN(addr, size) _ALIGN_UP(addr, size)
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/* to align the pointer to the (next) page boundary */
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#define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE)
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#define RAMDUMP_STICKY_DATA_MASK (0xFFFF)
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extern void check_ramdump(void);
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extern void ramdump_init(void);
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extern unsigned long ramdump_base;
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extern unsigned long ramdump_size;
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extern int g_ramdump_skip_osd_lcd;
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extern struct bootm_headers images;
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int ramdump_save_compress_data(void);
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/* ramdump ddr md5 check */
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#define MD5_BLOCK_SIZE (8 << 20)
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#define MD5_STORE_SIZE (64 << 10)
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#define MD5_PER_ROW_NUM (32)
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#define MD5_BL2E_1_BASE_ADDR (0x00B00000)
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#define MD5_BL2E_2_BASE_ADDR (0x00B10000)
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#define MD5_BL33Z_1_BASE_ADDR (0x00B20000)
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#define MD5_BL33Z_2_BASE_ADDR (0x00B30000)
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#define MD5_BL33X_1_BASE_ADDR (0x00B40000)
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#define MD5_BL33X_2_BASE_ADDR (0x00B50000)
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#define MD5_BL33Z_RAMDUMP_STR (0x00B60000)
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#define MD5_MAGIC "RAMDUMPMD5"
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#define REG_SPACE_START_ADDR (0xE0000000) /* reg space: 3.5g ~ 4.0g */
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/* ramdump clean ddr */
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#define RAMDUMP_SKIP_BL31_START (0x05000000)
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#define RAMDUMP_SKIP_BL32_END (0x08400000)
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#define RAMDUMP_COMPRESS_START (0x0C000000)
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#define RAMDUMP_ISOLATION_SIZE (0x01000000)
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struct rammd5_info_t {
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char magic[16];
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char stage[16];
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unsigned int block_size;
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unsigned int ddr_size;
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unsigned int area1_start;
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unsigned int area1_end;
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unsigned int area2_start;
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unsigned int area2_end;
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};
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#endif /* __RAMDUMP_H__ */
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