574 lines
16 KiB
C
574 lines
16 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __MESON_NAND_H_
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#define __MESON_NAND_H_
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <nand.h>
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#include "partition_table.h"
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#include <linux/mtd/partitions.h>
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#include "aml_nand.h"
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#include "aml_hwctrl.h"
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#include "aml_rsv.h"
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#include "aml_mtd.h"
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#define NAND_MAX_DEVICE 4
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/*MAX page list cnt for usrdef mode*/
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#define NAND_PAGELIST_CNT 16
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/*nand read retry info,max equal to zero,
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*that means no need retry*/
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struct nand_retry_t {
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unsigned id;
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unsigned max;
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unsigned no_rb;
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};
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typedef struct _nand_cmd {
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unsigned char type;
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unsigned char val;
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} nand_cmd_t;
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struct meson_slcnand_platdata {
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u32 reg_base;
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u8 nand_user_mode;
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u8 nand_ran_mode;
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};
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union sc2_cmdinfo {
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uint32_t d32;
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struct {
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unsigned cmd:22; //20-21b' code0/1 17b' WE_n(r/w->1/0b)
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unsigned page_list:1;
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unsigned reserved:1;
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unsigned new_type:8;
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} b;
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};
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typedef struct nand_setup_sc2 {
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union sc2_cmdinfo cfg;
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uint16_t id;
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uint16_t max; // id:0x100 user, max:0 disable.
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} nand_setup_sc2_t;
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union cmdinfo {
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uint32_t d32;
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struct {
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unsigned cmd:22;
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unsigned large_page:1; // 22
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unsigned no_rb:1; // 23 from efuse
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unsigned a2:1; // 24
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unsigned reserved25:1; // 25
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unsigned page_list:1; // 26
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unsigned sync_mode:2; // 27 from efuse
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unsigned size:2; // 29 from efuse
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unsigned active:1; // 31
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} b;
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};
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typedef struct nand_setup {
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union cmdinfo cfg;
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uint16_t id;
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uint16_t max; // id:0x100 user, max:0 disable.
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} nand_setup_t;
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typedef struct _ext_info{
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uint32_t read_info; //nand_read_info;
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uint32_t new_type; //new_nand_type;
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uint32_t page_per_blk; //pages_in_block;
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uint32_t xlc; //slc=1,mlc=2,tlc=3;
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uint32_t ce_mask;
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/*copact mode: boot means whole uboot
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it's easy to understand that copies off_type
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bl2 and fip are the same.
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* discrete mode,boot means the fip only*/
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uint32_t boot_num;
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uint32_t each_boot_pages;
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/*for compatible reason*/
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uint32_t bbt_occupy_pages;
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uint32_t bbt_start_block;
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} ext_info_t;
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#define NAND_FIPMODE_COMPACT (0)
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#define NAND_FIPMODE_DISCRETE (1)
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/* if you don't need skip the bad blocks when address
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* partitions,please enable this macro.
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* #define CONFIG_NOT_SKIP_BAD_BLOCK
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*/
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typedef struct _fip_info {
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uint16_t version; //version
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uint16_t mode; //compact or discrete
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uint32_t fip_start; //fip start,pages
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} fip_info_t;
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typedef struct _nand_page0_sc2 {
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nand_setup_sc2_t nand_setup;
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unsigned char page_list[32];
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nand_cmd_t retry_usr[32];
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ext_info_t ext_info;
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fip_info_t fip_info;
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} nand_page0_sc2_t;
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typedef struct _nand_page0 {
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nand_setup_t nand_setup;
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unsigned char page_list[16];
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nand_cmd_t retry_usr[32];
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ext_info_t ext_info;
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fip_info_t fip_info;
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uint32_t ddrp_start_page;
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} nand_page0_t;
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typedef union nand_core_clk {
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/*raw register data*/
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uint32_t d32;
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struct {
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unsigned clk_div:7;
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unsigned reserved0:1;
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unsigned clk_en:1;
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unsigned clk_sel:3;
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unsigned not_used:20;
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} b;
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} nand_core_clk_t;
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/***************ERROR CODING*******************/
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#define NAND_CHIP_ID_ERR 1
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#define NAND_SHIP_BAD_BLOCK_ERR 2
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#define NAND_CHIP_REVB_HY_ERR 3
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/** Register defination **/
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#define NAND_BOOT_NAME "bootloader"
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#define NAND_NORMAL_NAME "nandnormal"
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#define NAND_RESERVED_NAME "nandreserved"
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#define AML_CHIP_NONE_RB 4
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#define AML_INTERLEAVING_MODE 8
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#define AML_NAND_CE0 0xe
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#define AML_NAND_CE1 0xd
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#define AML_NAND_CE2 0xb
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#define AML_NAND_CE3 0x7
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#define AML_BADBLK_POS 0
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#define NAND_ECC_OPTIONS_MASK 0x0000000f
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#define NAND_PLANE_OPTIONS_MASK 0x000000f0
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#define NAND_TIMING_OPTIONS_MASK 0x00000f00
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#define NAND_BUSW_OPTIONS_MASK 0x0000f000
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#define NAND_INTERLEAVING_OPTIONS_MASK 0x000f0000
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#define NAND_TWO_PLANE_MODE 0x00000010
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#define NAND_TIMING_MODE0 0x00000000
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#define NAND_TIMING_MODE1 0x00000100
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#define NAND_TIMING_MODE2 0x00000200
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#define NAND_TIMING_MODE3 0x00000300
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#define NAND_TIMING_MODE4 0x00000400
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#define NAND_TIMING_MODE5 0x00000500
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#define NAND_INTERLEAVING_MODE 0x00010000
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#define DEFAULT_T_REA 40
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#define DEFAULT_T_RHOH 0
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#define NAND_DEFAULT_OPTIONS (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)
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#define AML_NAND_BUSY_TIMEOUT 0x40000
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#define AML_DMA_BUSY_TIMEOUT 0x100000
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#define MAX_ID_LEN 8
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#define NAND_CMD_PLANE2_READ_START 0x06
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#define NAND_CMD_TWOPLANE_PREVIOS_READ 0x60
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#define NAND_CMD_TWOPLANE_READ1 0x5a
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#define NAND_CMD_TWOPLANE_READ2 0xa5
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#define NAND_CMD_TWOPLANE_WRITE2_MICRO 0x80
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#define NAND_CMD_TWOPLANE_WRITE2 0x81
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#define NAND_CMD_DUMMY_PROGRAM 0x11
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#define NAND_CMD_ERASE1_END 0xd1
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#define NAND_CMD_MULTI_CHIP_STATUS 0x78
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#define ONFI_TIMING_ADDR 0x01
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#define NAND_STATUS_READY_MULTI 0x20
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#define NAND_BLOCK_GOOD 0
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#define NAND_BLOCK_BAD 1
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#define NAND_FACTORY_BAD 2
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#define BAD_BLK_LEVEL 2
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#define FACTORY_BAD_BLOCK_ERROR 159
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#define MINI_PART_SIZE 0x100000
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#define NAND_MINI_PART_NUM 4
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#define MAX_BAD_BLK_NUM 2000
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#define MAX_MTD_PART_NUM 16
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#define MAX_MTD_PART_NAME_LEN 24
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#define NAND_SYS_PART_SIZE 0x8000000
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struct aml_nand_flash_dev {
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char *name;
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u8 id[MAX_ID_LEN];
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unsigned pagesize;
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unsigned chipsize;
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unsigned erasesize;
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unsigned oobsize;
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unsigned internal_chipnr;
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unsigned T_REA;
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unsigned T_RHOH;
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u8 onfi_mode;
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unsigned options;
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};
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struct aml_nand_part_info {
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char mtd_part_magic[4];
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char mtd_part_name[MAX_MTD_PART_NAME_LEN];
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uint64_t size;
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uint64_t offset;
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u_int32_t mask_flags;
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};
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struct aml_nand_bch_desc {
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char *name;
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unsigned bch_mode;
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unsigned bch_unit_size;
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unsigned bch_bytes;
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unsigned user_byte_mode;
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};
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struct aml_nand_chip {
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struct nand_chip chip;
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struct hw_controller *controller;
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/* mtd info */
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u8 mfr_type;
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unsigned onfi_mode;
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unsigned T_REA;
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unsigned T_RHOH;
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unsigned options;
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unsigned page_size;
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unsigned block_size;
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unsigned oob_size;
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unsigned virtual_page_size;
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unsigned virtual_block_size;
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u8 plane_num;
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u8 internal_chipnr;
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unsigned internal_page_nums;
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unsigned internal_chip_shift;
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unsigned int ran_mode;
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unsigned int rbpin_mode;
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unsigned int rbpin_detect;
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unsigned int short_pgsz;
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/* bch for infopage on short mode */
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unsigned int bch_info;
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unsigned bch_mode;
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u8 user_byte_mode;
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u8 ops_mode;
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u8 cached_prog_status;
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u8 max_bch_mode;
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unsigned valid_chip[MAX_CHIP_NUM];
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unsigned page_addr;
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unsigned char *aml_nand_data_buf;
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unsigned int *user_info_buf;
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int8_t *block_status;
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unsigned int toggle_mode;
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u8 ecc_cnt_limit;
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u8 ecc_cnt_cur;
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u8 ecc_max;
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unsigned zero_cnt;
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unsigned oob_fill_cnt;
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unsigned boot_oob_fill_cnt;
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/*add property field for key private data*/
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int dtbsize;
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int keysize;
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uint32_t boot_copy_num; /*tell how many bootloader copies*/
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u8 key_protect;
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unsigned char *rsv_data_buf;
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struct meson_rsv_handler_t *rsv;
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struct aml_nand_bch_desc *bch_desc;
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/* platform info */
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struct aml_nand_platform *platform;
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/* device info */
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struct device *device;
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unsigned max_ecc;
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struct ecc_desc_s *ecc;
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// unsigned onfi_mode;
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unsigned err_sts;
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/* plateform operation function*/
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void (*aml_nand_hw_init)(struct aml_nand_chip *aml_chip);
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void (*aml_nand_adjust_timing)(struct aml_nand_chip *aml_chip);
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int (*aml_nand_options_confirm)(struct aml_nand_chip *aml_chip);
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void (*aml_nand_cmd_ctrl)(struct aml_nand_chip *aml_chip,
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int cmd, unsigned int ctrl);
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void (*aml_nand_select_chip)(struct aml_nand_chip *aml_chip,
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int chipnr);
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void (*aml_nand_write_byte)(struct aml_nand_chip *aml_chip,
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u8 data);
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void (*aml_nand_get_user_byte)(struct aml_nand_chip *aml_chip,
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unsigned char *oob_buf, int byte_num);
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void (*aml_nand_set_user_byte)(struct aml_nand_chip *aml_chip,
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unsigned char *oob_buf, int byte_num);
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void (*aml_nand_command)(struct aml_nand_chip *aml_chip,
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unsigned command, int column, int page_addr, int chipnr);
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int (*aml_nand_wait_devready)(struct aml_nand_chip *aml_chip,
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int chipnr);
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int (*aml_nand_dma_read)(struct aml_nand_chip *aml_chip,
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unsigned char *buf, int len, unsigned bch_mode);
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int (*aml_nand_dma_write)(struct aml_nand_chip *aml_chip,
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unsigned char *buf, int len, unsigned bch_mode);
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int (*aml_nand_hwecc_correct)(struct aml_nand_chip *aml_chip,
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unsigned char *buf, unsigned size, unsigned char *oob_buf);
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int (*aml_nand_block_bad_scrub)(struct mtd_info *mtd);
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};
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struct aml_pre_scan {
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u8 pre_scan_flag;
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u8 is_nand;
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};
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struct aml_nand_platform {
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struct aml_nand_flash_dev *nand_flash_dev;
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char *name;
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unsigned chip_enable_pad;
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unsigned ready_busy_pad;
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/* DMA RD/WR delay loop timing */
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unsigned int T_REA; /* for dma wating delay */
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/* not equal of (nandchip->delay, which is for dev ready func)*/
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unsigned int T_RHOH;
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unsigned int ran_mode; /*def close, for all part*/
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unsigned int rbpin_mode; /*may get from romboot*/
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unsigned int rbpin_detect;
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unsigned int short_pgsz; /*zero means no short*/
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struct aml_nand_chip *aml_chip;
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struct platform_nand_data platform_nand_data;
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};
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struct aml_nand_device {
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struct aml_nand_platform *aml_nand_platform;
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u8 dev_num;
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};
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static inline struct aml_nand_chip *mtd_to_nand_chip(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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return container_of(chip, struct aml_nand_chip, chip);
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}
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#ifdef CONFIG_PARAMETER_PAGE
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struct parameter_page {
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/*0~31 byte: Revision information and features block*/
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unsigned char signature[4];
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unsigned short ver;
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unsigned short feature;
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unsigned short opt_commd;
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unsigned short reserve0;
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unsigned short ex_para_page_len;
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unsigned char num_para_page;
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unsigned char reserve1[17];
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/*32~79 byte: Manufacturer information block*/
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unsigned char dev_manu[12];
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unsigned char dev_model[20];
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unsigned char JEDEC_manu_ID;
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unsigned short date_code;
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unsigned char reserve2[13];
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/*80~127 byte: Memory organization block*/
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unsigned int data_bytes_perpage;
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unsigned short spare_bytes_perpage;
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unsigned int data_bytes_perpartial;
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unsigned short spare_bytes_perpartial;
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unsigned int pages_perblk;
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unsigned int blks_perLUN;
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unsigned char num_LUN;
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/* 4-7: column addr cycles; 0-3: row addr cycles*/
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unsigned char num_addr_cycle;
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unsigned char bits_percell;
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unsigned short max_badblk_perLUN;
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unsigned short blk_edurce;
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/*Guaranteed valid blocks at beginning of target*/
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unsigned char g_v_blk_begin;
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unsigned short blk_edurce_g_v_blk;
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unsigned char progm_perpage;
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unsigned char prt_prog_att;//obsolete
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unsigned char bits_ECC_correctable;
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/*0-3: number of interleaved address bits*/
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unsigned char bits_intleav_addr;
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/*6-7 Reserved (0)
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5 1 = lower bit XNOR block address restriction
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4 1 = read cache supported
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3 Address restrictions for cache operations
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2 1 = program cache supported
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1 1 = no block address restrictions
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0 Overlapped / concurrent interleaving support
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*/
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unsigned char intleav_op_attr;
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unsigned char reserve3[13];
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/*128~163 byte: Electrical parameters block*/
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unsigned char max_io_pin;
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/*6-15 Reserved (0)
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5 1 = supports timing mode 5
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4 1 = supports timing mode 4
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3 1 = supports timing mode 3
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2 1 = supports timing mode 2
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1 1 = supports timing mode 1
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0 1 = supports timing mode 0, shall be 1
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*/
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unsigned short asy_time_mode;
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unsigned short asy_prog_cach_time_mode; /*obsolete*/
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unsigned short Tprog; /*Maximum page program time (Ts)*/
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unsigned short Tbers; /*Maximum block erase time (Ts)*/
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unsigned short Tr; /*Maximum page read time (Ts)*/
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unsigned short Tccs; /*Minimum change column setup time (ns)*/
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/* 6-15 Reserved (0)
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5 1 = supports timing mode 5
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4 1 = supports timing mode 4
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3 1 = supports timing mode 3
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2 1 = supports timing mode 2
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1 1 = supports timing mode 1
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0 1 = supports timing mode 0
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*/
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unsigned short src_syn_time_mode;
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/*3-7 Reserved (0)
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2 1 = device supports CLK stopped for data input
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1 1 = typical capacitance values present
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0 tCAD value to use
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*/
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unsigned char src_syn_feature;
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unsigned short CLK_input_pin;
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unsigned short IO_pin;
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unsigned short input_pin;
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unsigned char max_input_pin;
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unsigned char dr_strgth;
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/*Maximum interleaved page read time (Ts)*/
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unsigned short Tir;
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/*Program page register clear enhancement tADL value (ns)*/
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unsigned short Tadl;
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unsigned char reserve4[8];
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/*164~255 byte: Vendor block*/
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unsigned short vd_ver;
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unsigned char vd_spec[88];
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unsigned short int_CRC;
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/*256~ byte: Redundant Parameter Pages*/
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} __attribute__ ((__packed__));
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#endif
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extern unsigned char pagelist_1ynm_hynix256_mtd[128];
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extern struct hw_controller *controller;
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int meson_nfc_probe(struct udevice *dev);
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int aml_nand_init(struct aml_nand_chip *aml_chip);
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int aml_nand_read_page_raw(struct mtd_info *mtd,
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struct nand_chip *chip, u8 *buf, int oob_required, int page);
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int aml_nand_write_page_raw(struct mtd_info *mtd,
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struct nand_chip *chip, const u8 *buf, int oob_required,
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int page);
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int aml_nand_read_page_hwecc(struct mtd_info *mtd,
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struct nand_chip *chip, u8 *buf, int oob_required, int page);
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int aml_nand_write_page_hwecc(struct mtd_info *mtd,
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struct nand_chip *chip, const u8 *buf, int oob_required,
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int page);
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int aml_nand_read_oob(struct mtd_info *mtd,
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struct nand_chip *chip, int page);
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int aml_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page);
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int aml_nand_block_bad(struct mtd_info *mtd, loff_t ofs);
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int aml_nand_block_markbad(struct mtd_info *mtd, loff_t ofs);
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void aml_nand_dma_read_buf(struct mtd_info *mtd, u8 *buf, int len);
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void aml_nand_dma_write_buf(struct mtd_info *mtd, const u8 *buf, int len);
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void aml_platform_cmd_ctrl(struct aml_nand_chip *aml_chip,
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int cmd, unsigned int ctrl);
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void aml_platform_write_byte(struct aml_nand_chip *aml_chip, u8 data);
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int aml_platform_wait_devready(struct aml_nand_chip *aml_chip, int chipnr);
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void aml_platform_get_user_byte(struct aml_nand_chip *aml_chip,
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unsigned char *oob_buf, int byte_num);
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void aml_platform_set_user_byte(struct aml_nand_chip *aml_chip,
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unsigned char *oob_buf, int byte_num);
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void aml_nand_base_command(struct aml_nand_chip *aml_chip,
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unsigned command, int column, int page_addr, int chipnr);
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int aml_nand_block_bad_scrub_update_bbt(struct mtd_info *mtd);
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int aml_ubootenv_init(struct aml_nand_chip *aml_chip);
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int amlnf_dtb_init(struct aml_nand_chip *aml_chip);
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int aml_key_init(struct aml_nand_chip *aml_chip);
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int aml_nand_erase_key(struct mtd_info *mtd);
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int aml_nand_bbt_check(struct mtd_info *mtd);/*fixed by liuxianjun*/
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int aml_nand_scan(struct mtd_info *mtd, int maxchips);
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int aml_nand_write_page_raw(struct mtd_info *mtd,
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struct nand_chip *chip, const u8 *buf, int oob_required,
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int page);
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int aml_nand_write_page(struct mtd_info *mtd,
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struct nand_chip *chip, uint32_t offset,
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int data_len,
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const u8 *buf,
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int oob_required, int page, int raw);
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void aml_nand_base_command(struct aml_nand_chip *aml_chip,
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unsigned command, int column, int page_addr, int chipnr);
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void aml_nand_command(struct mtd_info *mtd,
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unsigned command, int column, int page_addr);
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int aml_nand_wait(struct mtd_info *mtd, struct nand_chip *chip);
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int aml_nand_erase(struct mtd_info *mtd, int page);
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int m3_nand_boot_erase_cmd(struct mtd_info *mtd, int page);
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int m3_nand_boot_read_page_hwecc(struct mtd_info *mtd,
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struct nand_chip *chip, u8 *buf, int oob_required, int page);
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int m3_nand_boot_write_page_hwecc(struct mtd_info *mtd,
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struct nand_chip *chip, const u8 *buf, int oob_required,
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int page);
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int m3_nand_boot_write_page(struct mtd_info *mtd, struct nand_chip *chip,
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uint32_t offset, int data_len, const u8 *buf,
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int oob_required, int page, int raw);
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int aml_get_samsung_fbbt_flag(void);
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int aml_nand_get_fbb_issue(void);
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void aml_nand_check_fbb_issue(u8 *dev_id);
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void aml_nand_set_onfi_features(struct aml_nand_chip *aml_chip,
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u8 *buf, int addr);
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u8 aml_nand_get_onfi_features(struct aml_nand_chip *aml_chip,
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u8 *buf, int addr);
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struct mtd_partition *get_aml_mtd_partition(void);
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int get_aml_partition_count(void);
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#endif
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