501 lines
12 KiB
C
501 lines
12 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _VINFO_H_
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#define _VINFO_H_
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#include <linux/types.h>
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#include <amlogic/media/vout/hdmi.h>
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#include <amlogic/media/vout/hdmitx_common.h>
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#include <amlogic/media/vout/aml_vmode.h>
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/* the MSB is represent vmode set by vmode_init */
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#define VMODE_INIT_BIT_MASK 0x8000
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#define VMODE_MODE_BIT_MASK 0xff
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#define VMODE_NULL_DISP_MAX 2
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enum viu_mux_e {
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VIU_MUX_ENCL = 0,
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VIU_MUX_ENCI,
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VIU_MUX_ENCP,
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VIU_MUX_MAX,
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VIU_MUX_PROJECT,
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};
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enum vout_fr_adj_type_e {
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VOUT_FR_ADJ_CLK = 0,
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VOUT_FR_ADJ_HTOTAL,
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VOUT_FR_ADJ_VTOTAL,
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VOUT_FR_ADJ_COMBO, /* vtotal + htotal + clk */
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VOUT_FR_ADJ_HDMI, /* 50<->60: htotal; 60<->59.94: clk */
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VOUT_FR_ADJ_FREERUN, /* freerun, panel fix frame rate*/
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VOUT_FR_ADJ_NONE, /* disable fr_adj */
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VOUT_FR_ADJ_MAX,
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};
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enum vinfo_3d_e {
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NON_3D = 0,
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SS_3D,
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FP_3D,
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TB_3D,
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};
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/* for dptx, besides 8/10/12/16 bits per component,
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* it also support 6/14 bits per component
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*/
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enum hdmi_color_depth {
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COLORDEPTH_24B = 4,
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COLORDEPTH_30B = 5,
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COLORDEPTH_36B = 6,
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COLORDEPTH_48B = 7,
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/* for DP */
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COLORDEPTH_18B = 8,
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COLORDEPTH_42B = 9,
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COLORDEPTH_RESERVED = 11,
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};
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typedef enum hdmi_color_depth color_depth_t;
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/*emp : extended metadata type*/
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#define VENDOR_SPECIFIC_EM_DATA 0x0
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#define COMPRESS_VIDEO_TRAMSPORT 0x1
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#define HDR_DYNAMIC_METADATA 0x2
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#define VIDEO_TIMING_EXTENDED 0x3
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#define SUPPORT_2020 0x01
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/* vpp_post_out_range */
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#define HDMI_LIMIT_COLOR_RANGE 0
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#define HDMI_FULL_COLOR_RANGE 1
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/* vpp_post_out_colorimetry */
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#define HDMI_709_COLORIMETRY 0
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#define HDMI_601_COLORIMETRY 1
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#define HDMI_2020_COLORIMETRY 2
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#define HDMI_2020C_COLORIMETRY 3
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/* master_display_info for display device */
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struct master_display_info_s {
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u32 present_flag;
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u32 features; /* feature bits bt2020/2084 */
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u32 primaries[3][2]; /* normalized 50000 in G,B,R order */
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u32 white_point[2]; /* normalized 50000 */
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u32 luminance[2]; /* max/min lumin, normalized 10000 */
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u32 max_content; /* Maximum Content Light Level */
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u32 max_frame_average; /* Maximum Frame-average Light Level */
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};
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/* SBTM packet info */
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struct vtem_sbtm_st {
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u8 sbtm_ver: 4; /* MD0 */
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unsigned char: 4;
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u8 sbtm_mode: 2; /* MD1 */
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u8 sbtm_type: 2;
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u8 grdm_min: 2;
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u8 grdm_lum: 2;
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u16 frmpblimitint; /* MD2/3 */
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};
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/*
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*hdr_dynamic_type
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* 0x0001: type_1_hdr_metadata_version
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* 0x0002: ts_103_433_spec_version
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* 0x0003: itu_t_h265_spec_version
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* 0x0004: type_4_hdr_metadata_version
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*/
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struct hdr_dynamic {
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unsigned int type;
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unsigned char support_flags;
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unsigned int of_len; /*optional_fields length*/
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unsigned char optional_fields[28];
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};
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struct hdr10_plus_info {
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u32 ieeeoui;
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u8 length;
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u8 application_version;
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};
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struct cuva_info {
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u32 cuva_support;
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u8 rawdata[15];
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u8 length;
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u32 ieeeoui;
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u8 system_start_code;
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u8 version_code;
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u32 display_max_lum;
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u16 display_min_lum;
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u8 monitor_mode_sup;
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u8 rx_mode_sup;
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};
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/* SBTM EDID capabilities */
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struct sbtm_info {
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unsigned char sbtm_support: 1;
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unsigned char max_sbtm_ver: 4;
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unsigned char grdm_support: 2;
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unsigned char drdm_ind: 1;
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unsigned char hgig_cat_drdm_sel: 3;
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unsigned char: 1;
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unsigned char use_hgig_drdm: 1;
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unsigned char maxrgb: 1;
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unsigned char gamut: 2;
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unsigned short red_x;
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unsigned short red_y;
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unsigned short green_x;
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unsigned short green_y;
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unsigned short blue_x;
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unsigned short blue_y;
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unsigned short white_x;
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unsigned short white_y;
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unsigned char min_bright_10;
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unsigned char peak_bright_100;
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unsigned char p0_exp: 2;
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unsigned char p0_mant: 6;
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unsigned char peak_bright_p0;
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unsigned char p1_exp: 2;
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unsigned char p1_mant: 6;
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unsigned char peak_bright_p1;
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unsigned char p2_exp: 2;
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unsigned char p2_mant: 6;
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unsigned char peak_bright_p2;
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unsigned char p3_exp: 2;
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unsigned char p3_mant: 6;
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unsigned char peak_bright_p3;
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};
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struct hdr_info {
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/* RX EDID hdr support types */
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/* hdr_support: bit0/SDR bit1/HDR bit2/SMPTE2084 bit3/HLG */
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u32 hdr_support;
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/* In CTA-861-I Table 52, static_metadata_type1 use only 1 bit */
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unsigned char static_metadata_type1;
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unsigned char rawdata[7];
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/*
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*dynamic_info[0] expresses type1's parameters certainly
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*dynamic_info[1] expresses type2's parameters certainly
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*dynamic_info[2] expresses type3's parameters certainly
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*dynamic_info[3] expresses type4's parameters certainly
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*if some types don't exist, the corresponding dynamic_info
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*is zero instead of inexistence
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*/
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struct hdr_dynamic dynamic_info[4];
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struct hdr10_plus_info hdr10plus_info;
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/*bit7:BT2020RGB bit6:BT2020YCC bit5:BT2020cYCC bit4:adobeRGB*/
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/*bit3:adobeYCC601 bit2:sYCC601 bit1:xvYCC709 bit0:xvYCC601*/
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u8 colorimetry_support; /* RX EDID colorimetry support types */
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u32 lumi_max; /* RX EDID Lumi Max value */
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u32 lumi_avg; /* RX EDID Lumi Avg value */
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u32 lumi_min; /* RX EDID Lumi Min value */
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u32 lumi_peak; /* RX EDID Lumi Peak value */
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u32 ldim_support; /* RX EDID Local Dimming Support */
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struct cuva_info cuva_info;
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struct sbtm_info sbtm_info; /* TV SBTM EDID capabilities */
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};
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struct hdr10plus_para {
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u8 application_version;
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u8 targeted_max_lum;
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u8 average_maxrgb;
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u8 distribution_values[9];
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u8 num_bezier_curve_anchors;
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u32 knee_point_x;
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u32 knee_point_y;
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u8 bezier_curve_anchors[9];
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u8 graphics_overlay_flag;
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u8 no_delay_flag;
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};
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enum eotf_type {
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EOTF_T_NULL = 0,
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EOTF_T_DOLBYVISION,
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EOTF_T_HDR10,
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EOTF_T_SDR,
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EOTF_T_LL_MODE,
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EOTF_T_DV_AHEAD,
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EOTF_T_MAX,
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};
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enum mode_type {
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YUV422_BIT12 = 0,
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RGB_8BIT,
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RGB_10_12BIT,
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YUV444_10_12BIT,
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};
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#define DV_IEEE_OUI 0x00D046
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#define HDR10_PLUS_IEEE_OUI 0x90848B
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#define HDR10_PLUS_DISABLE_VSIF 0
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#define HDR10_PLUS_ENABLE_VSIF 1
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#define HDR10_PLUS_ZERO_VSIF 2
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/* Dolby Version VSIF parameter*/
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struct dv_vsif_para {
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u8 ver; /* 0 or 1 or 2*/
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u8 length;/*ver1: 15 or 12*/
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u8 ver2_l11_flag;
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union {
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struct {
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u8 low_latency:1;
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u8 dobly_vision_signal:4;
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u8 backlt_ctrl_MD_present:1;
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u8 auxiliary_MD_present:1;
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u8 eff_tmax_PQ_hi;
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u8 eff_tmax_PQ_low;
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u8 auxiliary_runmode;
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u8 auxiliary_runversion;
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u8 auxiliary_debug0;
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u8 src_dm_version:3;
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} ver2;
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struct {
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u8 low_latency:1;
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u8 dobly_vision_signal:4;
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u8 backlt_ctrl_MD_present:1;
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u8 auxiliary_MD_present:1;
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u8 eff_tmax_PQ_hi;
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u8 eff_tmax_PQ_low;
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u8 auxiliary_runmode;
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u8 auxiliary_runversion;
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u8 auxiliary_debug0;
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u8 src_dm_version:3;
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u8 content_type;
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u8 content_sub_type;
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u8 crf;
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u8 intended_white_point;
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u8 l11_byte2;
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u8 l11_byte3;
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} ver2_l11;
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} vers;
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};
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struct cuva_hdr_vsif_para {
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u8 system_start_code;
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u8 version_code;
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u8 monitor_mode_en;
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u8 transfer_character;
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};
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struct cuva_hdr_vs_emds_para {
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u8 system_start_code;
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u8 version_code;
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u16 min_maxrgb_pq;
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u16 avg_maxrgb_pq;
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u16 var_maxrgb_pq;
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u16 max_maxrgb_pq;
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u16 targeted_max_lum_pq;
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u8 transfer_character;
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u8 base_enable_flag;
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u16 base_param_m_p;
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u16 base_param_m_m;
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u16 base_param_m_a;
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u16 base_param_m_b;
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u16 base_param_m_n;
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u8 base_param_k[3];
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u8 base_param_delta_enable_mode;
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u8 base_param_enable_delta;
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u8 _3spline_enable_num;
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u8 _3spline_enable_flag;
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struct {
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u8 th_enable_mode;
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u8 th_enable_mb;
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u16 th_enable;
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u16 th_enable_delta[2];
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u8 enable_strength;
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} _3spline_data[2];
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u8 color_saturation_num;
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u8 color_saturation_gain[8];
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u8 graphic_src_display_value;
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u16 max_display_mastering_lum;
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};
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struct vsif_debug_save {
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enum eotf_type type;
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enum mode_type tunnel_mode;
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struct dv_vsif_para data;
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bool signal_sdr;
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};
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struct emp_debug_save {
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unsigned char data[128];
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unsigned int type;
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unsigned int size;
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};
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/* Dolby Version support information from EDID*/
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/* Refer to DV Spec version2.9 page26 to page39*/
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enum block_type {
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ERROR_NULL = 0,
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ERROR_LENGTH,
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ERROR_OUI,
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ERROR_VER,
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CORRECT,
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};
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struct dv_info {
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unsigned char rawdata[27];
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enum block_type block_flag;
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u32 ieeeoui;
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u8 ver; /* 0 or 1 or 2*/
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u8 length;/*ver1: 15 or 12*/
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u8 sup_yuv422_12bit:1;
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/* if as 0, then support RGB tunnel mode */
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u8 sup_2160p60hz:1;
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/* if equals 0, then don't support 1080p100/120hz */
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u8 sup_1080p120hz:1;
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/* if as 0, then support 2160p30hz */
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u8 sup_global_dimming:1;
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u8 dv_emp_cap:1;
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u16 Rx;
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u16 Ry;
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u16 Gx;
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u16 Gy;
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u16 Bx;
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u16 By;
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u16 Wx;
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u16 Wy;
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u16 tminPQ;
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u16 tmaxPQ;
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u8 dm_major_ver;
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u8 dm_minor_ver;
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u8 dm_version;
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u8 tmax_lum;
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u8 colorimetry:1;/* ver1*/
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u8 tmin_lum;
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u8 low_latency;/* ver1_12 and 2*/
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u8 sup_backlight_control:1;/*only ver2*/
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u8 backlt_min_luma;/*only ver2*/
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u8 Interface;/*only ver2*/
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u8 parity:1;/*only ver2*/
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u8 sup_10b_12b_444;/*only ver2*/
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u8 support_DV_RGB_444_8BIT;
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u8 support_LL_YCbCr_422_12BIT;
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u8 support_LL_RGB_444_10BIT;
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u8 support_LL_RGB_444_12BIT;
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};
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struct vout_device_s {
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void (*fresh_tx_hdr_pkt)(void *tx_instance, struct master_display_info_s *data);
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void (*fresh_tx_sbtm_pkt)(void *tx_instance, struct vtem_sbtm_st *data);
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void (*fresh_tx_vsif_pkt)(void *tx_instance, enum eotf_type type,
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enum mode_type tunnel_mode,
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struct dv_vsif_para *data,
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bool signal_sdr);
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void (*fresh_tx_hdr10plus_pkt)(void *tx_instance, unsigned int flag,
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struct hdr10plus_para *data);
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void (*fresh_tx_cuva_hdr_vsif)(void *tx_instance, struct cuva_hdr_vsif_para *data);
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void (*fresh_tx_cuva_hdr_vs_emds)(void *tx_instance, struct cuva_hdr_vs_emds_para *data);
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void (*fresh_tx_emp_pkt)(void *tx_instance, unsigned char *data, unsigned int type,
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unsigned int size);
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/* used for SDR case, yuv/rgb, limit/full, 601/709 dynamic switching */
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void (*fresh_tx_input_vpp_info)(void *tx_instance);
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void *tx_instance;
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};
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#define LATENCY_INVALID_UNKNOWN 0
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#define LATENCY_NOT_SUPPORT 0xffff
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struct rx_av_latency {
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unsigned int vLatency;
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unsigned int aLatency;
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unsigned int i_vLatency;
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unsigned int i_aLatency;
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};
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struct vinfo_s {
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char *name;
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enum vmode_e mode;
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char ext_name[32];
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u32 frac;
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u32 width;
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u32 height;
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u32 field_height;
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u32 aspect_ratio_num;
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u32 aspect_ratio_den;
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u32 screen_real_width;
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u32 screen_real_height;
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u32 sync_duration_num;
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u32 sync_duration_den;
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/* the BaseRefreshRate value of VRR case, larger than 50, usually 60 or 120 */
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u32 brr_duration;
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u32 std_duration;
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u32 vfreq_max;
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u32 vfreq_min;
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u32 video_clk;
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u32 htotal;
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u32 vtotal;
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u32 hsw;
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u32 hbp;
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u32 hfp;
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u32 vsw;
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u32 vbp;
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u32 vfp;
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u32 connector_type;
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unsigned char hdmichecksum[10];
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enum vinfo_3d_e info_3d;
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enum vout_fr_adj_type_e fr_adj_type;
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enum color_fmt_e viu_color_fmt;
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/* viu_mux
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* bit[3:0]: venc_sel, such as encp, enci, encl;
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* bit[7:4]: venc_index, such as 0, 1, 2
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*/
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unsigned int viu_mux;
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struct master_display_info_s master_display_info;
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struct vtem_sbtm_st sbtm_pkt;
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struct dv_info dv_info;
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struct hdr_info hdr_info;
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struct rx_av_latency rx_latency;
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struct vout_device_s *vout_device;
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/*
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* new parameters for s5 or later
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* if current output is FRL or DSC mode,
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* then there may use 2 or 4 slices pixel per clock.
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* the default value is 0 or 1.
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*/
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u8 cur_enc_ppc;
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/* ultra frame rate(dlg/hsr) pretreatment
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* 0:default, 1: scale down vertically by half
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*/
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u8 ufr_mode;
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/* odd/even line pretreatment for scaler.
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* 0:default, 1:alternating odd even line by field
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*/
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u8 asf_mode;
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/* 0: yuv, 1: rgb */
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u8 vpp_post_out_color_fmt;
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/* 0: limit, 1: full */
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u8 vpp_post_out_range:1;
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/* 0: 709, 1: 601, 2:2020, 3:2020c */
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u8 vpp_post_out_colorimetry:2;
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/*dv need get the cd/cd of hdmitx.*/
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enum hdmi_color_depth cd;
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enum hdmi_colorspace cs;
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u_char vl_bpix; /* Bits per pixel, 0 = 1 */
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void *vd_base; /* Start of framebuffer memory */
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void *vd_console_address; /* Start of console buffer */
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short console_col;
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short console_row;
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int vd_color_fg;
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int vd_color_bg;
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ushort *cmap; /* Pointer to the colormap */
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void *priv; /* Pointer to driver-specific data */
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};
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#ifdef CONFIG_AMLOGIC_MEDIA_FB
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struct disp_rect_s {
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int x;
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int y;
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int w;
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int h;
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};
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#endif
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#endif /* _VINFO_H_ */
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