180 lines
4.6 KiB
C
180 lines
4.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2021 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __DSC_H__
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#define __DSC_H__
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#include <linux/types.h>
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#include "hdmi.h"
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#include <linux/printk.h>
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#include <asm/io.h>
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#define RC_BUF_THRESH_NUM 14
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#define RC_RANGE_PARAMETERS_NUM 15
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struct dsc_rc_range_parameters {
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u8 range_min_qp;
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u8 range_max_qp;
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signed char range_bpg_offset; /* only 6 bit signal variable */
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};
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struct dsc_rc_parameter_set {
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unsigned int rc_model_size;
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u8 rc_edge_factor;
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u8 rc_quant_incr_limit0;
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u8 rc_quant_incr_limit1;
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u8 rc_tgt_offset_hi;
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u8 rc_tgt_offset_lo;
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u8 rc_buf_thresh[RC_BUF_THRESH_NUM]; /* config value need note >> 6 */
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struct dsc_rc_range_parameters rc_range_parameters[RC_RANGE_PARAMETERS_NUM];
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};
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struct dsc_pps_data_s {
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u8 dsc_version_major;
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u8 dsc_version_minor;
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u8 pps_identifier;
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u8 bits_per_component;
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u8 line_buf_depth;
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u8 block_pred_enable;
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u8 convert_rgb;
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u8 simple_422;
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u8 vbr_enable;
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unsigned int bits_per_pixel;
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unsigned int pic_height;
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unsigned int pic_width;
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unsigned int slice_height;
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unsigned int slice_width;
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unsigned int chunk_size;
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unsigned int initial_xmit_delay;
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unsigned int initial_dec_delay;
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u8 initial_scale_value;
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unsigned int scale_increment_interval;
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unsigned int scale_decrement_interval;
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u8 first_line_bpg_offset;
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unsigned int nfl_bpg_offset;
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unsigned int slice_bpg_offset;
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unsigned int initial_offset;
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unsigned int final_offset;
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u8 flatness_min_qp;
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u8 flatness_max_qp;
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struct dsc_rc_parameter_set rc_parameter_set;
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u8 native_420;
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u8 native_422;
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u8 second_line_bpg_offset;
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unsigned int nsl_bpg_offset;
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unsigned int second_line_offset_adj;
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unsigned int hc_active_bytes;
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};
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enum dsc_encode_mode {
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/* 4k60hz */
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DSC_RGB_3840X2160_60HZ,
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DSC_YUV444_3840X2160_60HZ,
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DSC_YUV422_3840X2160_60HZ,
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DSC_YUV420_3840X2160_60HZ,
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/* 4k50hz */
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DSC_RGB_3840X2160_50HZ,
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DSC_YUV444_3840X2160_50HZ,
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DSC_YUV422_3840X2160_50HZ,
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DSC_YUV420_3840X2160_50HZ,
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/* 4k120hz */
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DSC_RGB_3840X2160_120HZ,
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DSC_YUV444_3840X2160_120HZ,
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DSC_YUV422_3840X2160_120HZ,
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DSC_YUV420_3840X2160_120HZ,
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/* 4k100hz */
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DSC_RGB_3840X2160_100HZ,
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DSC_YUV444_3840X2160_100HZ,
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DSC_YUV422_3840X2160_100HZ,
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DSC_YUV420_3840X2160_100HZ,
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/* 8k60hz */
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DSC_RGB_7680X4320_60HZ,
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DSC_YUV444_7680X4320_60HZ,
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DSC_YUV422_7680X4320_60HZ,
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DSC_YUV420_7680X4320_60HZ,
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/* 8k50hz */
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DSC_RGB_7680X4320_50HZ,
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DSC_YUV444_7680X4320_50HZ,
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DSC_YUV422_7680X4320_50HZ,
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DSC_YUV420_7680X4320_50HZ,
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/* 8k24hz */
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DSC_RGB_7680X4320_24HZ,
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DSC_YUV444_7680X4320_24HZ,
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DSC_YUV422_7680X4320_24HZ,
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DSC_YUV420_7680X4320_24HZ,
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/* 8k25hz */
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DSC_RGB_7680X4320_25HZ,
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DSC_YUV444_7680X4320_25HZ,
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DSC_YUV422_7680X4320_25HZ,
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DSC_YUV420_7680X4320_25HZ,
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/* 8k30hz */
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DSC_RGB_7680X4320_30HZ,
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DSC_YUV444_7680X4320_30HZ,
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DSC_YUV422_7680X4320_30HZ,
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DSC_YUV420_7680X4320_30HZ,
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DSC_ENCODE_MAX,
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};
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struct dsc_mode_map {
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enum dsc_encode_mode dsc_mode;
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const char *mode_name;
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};
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struct dsc_offer_tx_data {
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enum dsc_encode_mode dsc_mode;
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struct dsc_pps_data_s pps_data;
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unsigned int enc0_clk;
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unsigned int cts_hdmi_tx_pixel_clk;
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};
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struct dsc_notifier_data_s {
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unsigned int pic_width;
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unsigned int pic_height;
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unsigned int fps; //actual value = fps * 1000
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unsigned int bits_per_component; //color depth
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enum hdmi_colorspace color_format;
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};
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/* 0: VESA DSC 1.2a is not supported
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* 1: up to 1 slice and up to (340 MHz/K SliceAdjust) pixel clock per slice
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* 2: up to 2 slices and up to (340 MHz/K SliceAdjust) pixel clock per slice
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* 3: up to 4 slices and up to (340 MHz/K SliceAdjust) pixel clock per slice
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* 4: up to 8 slices and up to (340 MHz/K SliceAdjust) pixel clock per slice
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* 5: up to 8 slices and up to (400 MHz/K SliceAdjust) pixel clock per slice
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* 6: up to 12 slices and up to (400 MHz/K SliceAdjust) pixel clock per slice
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* 7: up to 16 slices and up to (400 MHz/K SliceAdjust) pixel clock per slice
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* 8-15: Reserved
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*/
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static const u8 dsc_max_slices_num[] = {
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0,
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1,
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2,
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4,
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8,
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8,
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12,
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16
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};
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//hdmitx inform dsc video format
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int aml_set_dsc_input_param(struct dsc_notifier_data_s *notifier_data);
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//hdmitx to enable/disable dsc
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void aml_dsc_enable(bool dsc_en);
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//hdmitx get pps and enc/pixel_clk from dsc
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void hdmitx_get_dsc_data(struct dsc_offer_tx_data *dsc_data);
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enum dsc_encode_mode dsc_enc_confirm_mode(unsigned int pic_width, unsigned int pic_height,
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unsigned int fps, enum hdmi_colorspace color_format);
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u8 dsc_get_slice_num(enum dsc_encode_mode dsc_mode);
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u32 dsc_get_bytes_target_by_mode(enum dsc_encode_mode dsc_mode);
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u32 dsc_get_hc_active_by_mode(enum dsc_encode_mode dsc_mode);
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bool get_dsc_en(void);
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void dsc_enc_rst(void);
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void dsc_enc_cap_show(void);
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void dsc_debug(int argc, char *const parm[]);
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#endif
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