78 lines
1.7 KiB
C
78 lines
1.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef CLK_MESON_H
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#define CLK_MESON_H
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/* Gate Structure */
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struct meson_gate {
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unsigned int index;
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unsigned int reg;
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unsigned int bit;
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};
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/* Mux Structure */
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struct meson_mux {
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unsigned int index;
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unsigned int reg;
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unsigned int shift;
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unsigned int mask;
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unsigned int *table;
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unsigned int table_size;
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};
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/* Div Structure */
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struct meson_div {
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unsigned int index;
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unsigned int reg;
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unsigned int shift;
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unsigned int width;
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unsigned int parent_index;
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};
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/* PLL Parameters */
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struct parm {
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u16 reg_off;
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u8 shift;
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u8 width;
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};
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#define PMASK(width) GENMASK(width - 1, 0)
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#define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)
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#define CLRPMASK(width, shift) (~SETPMASK(width, shift))
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#define PARM_GET(width, shift, reg) \
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(((reg) & SETPMASK(width, shift)) >> (shift))
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#define PARM_SET(width, shift, reg, val) \
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(((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
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#define CLK81_RATE 166666667
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struct meson_clk {
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void __iomem *addr;
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struct clk clkin;
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u32 actual_rate;
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};
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/* MPLL Parameters */
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#define SDM_DEN 16384
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#define N2_MIN 4
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#define N2_MAX 511
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int meson_set_gate_by_id(struct clk *clk, struct meson_gate *gate_arr,
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unsigned int arr_size, bool on);
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int meson_mux_set_parent_by_id(struct clk *clk, struct meson_mux *mux_arr,
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unsigned int arr_size, struct clk *parent_clk);
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int meson_clk_get_mux_parent(struct clk *clk, struct meson_mux *mux_arr,
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unsigned int arr_size, ulong parent_id);
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int meson_clk_set_div(struct meson_clk *priv, struct meson_div *div,
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unsigned int div_val);
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#endif
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