122 lines
3.0 KiB
C
122 lines
3.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _CLK_PLL_H
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#define _CLK_PLL_H
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#include <clk.h>
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/* PLL Parameters */
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struct pll_parm {
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u32 reg;
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u8 shift;
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u8 width;
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};
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struct pll_params_table {
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unsigned long rate;
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unsigned int m;
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unsigned int n;
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unsigned int od;
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unsigned int frac;
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};
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#define PLL_RATE_PARAMS(_rate, _m, _n, _od) \
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{ \
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.rate = (_rate), \
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.m = (_m), \
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.n = (_n), \
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.od = (_od), \
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}
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#define PLL_RATE_PARAMS_FRAC(_rate, _m, _n, _od, _frac) \
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{ \
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.rate = (_rate), \
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.m = (_m), \
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.n = (_n), \
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.od = (_od), \
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.frac = (_frac), \
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}
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struct reg_sequence {
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unsigned int reg;
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unsigned int def;
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unsigned int delay_us;
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};
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#define CLK_AML_PLL_ROUND_CLOSEST BIT(0)
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#define CLK_AML_PLL_FORCE_INIT BIT(1)
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#define CLK_AML_PLL_FIXED_FRAC_WEIGHT_PRECISION BIT(2)
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#define CLK_AML_PLL_POWER_OF_TWO BIT(3)
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#define CLK_AML_PLL_M_EN0P5 BIT(5)
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#define CLK_AML_PLL_RSTN BIT(6)
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#define CLK_AML_PLL_L_DETECTN BIT(7)
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#define CLK_AML_PLL_READ_ONLY BIT(9)
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struct aml_clk_pll {
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struct clk clk;
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struct pll_parm en;
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struct pll_parm l;
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struct pll_parm rst;
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struct pll_parm l_detect_en;
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struct pll_parm m;
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struct pll_parm n;
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struct pll_parm frac;
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struct pll_parm od;
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const struct reg_sequence *init_regs;
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unsigned int init_count;
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const struct pll_params_table *table;
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unsigned int table_count;
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unsigned int flags;
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};
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extern const struct clk_ops clk_pll_ops;
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#define REG_PARM(_name, _reg, _shift, _width) \
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_name = { \
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.reg = _reg, \
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.shift = _shift, \
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.width = _width, \
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}
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#define CLK_PLL(_clkid, _name, _initregs, _init_count, _table, _table_count,\
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_en_reg, _en_shift, _en_width, \
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_rst_reg, _rst_shift, _rst_width, \
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_l_detect_en_reg, _l_detect_en_shift, _l_detect_en_width,\
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_l_reg, _l_shift, _l_width, \
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_m_reg, _m_shift, _m_width, \
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_n_reg, _n_shift, _n_width, \
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_frac_reg, _frac_shift, _frac_width, \
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_od_reg, _od_shift, _od_width, \
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_pll_flags, _pname, _flags) \
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[_clkid] = { \
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.type = PLL, \
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.name = _name, \
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.parent_name = _pname, \
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.data.pll = { \
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.init_regs = _initregs, \
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.init_count = _init_count, \
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.table = _table, \
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.table_count = _table_count, \
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.REG_PARM(en, _en_reg, _en_shift, _en_width), \
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.REG_PARM(rst, _rst_reg, _rst_shift, _rst_width),\
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.REG_PARM(l_detect_en, _l_detect_en_reg, \
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_l_detect_en_shift, _l_detect_en_width),\
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.REG_PARM(l, _l_reg, _l_shift, _l_width), \
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.REG_PARM(m, _m_reg, _m_shift, _m_width), \
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.REG_PARM(n, _n_reg, _n_shift, _n_width), \
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.REG_PARM(frac, _frac_reg, _frac_shift, _frac_width),\
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.REG_PARM(od, _od_reg, _od_shift, _od_width), \
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.flags = _pll_flags, \
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}, \
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.flags = _flags, \
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}
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struct clk *aml_clk_register_pll(const char *name, const char *parent_name,
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unsigned long flags,
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struct aml_clk_pll *data);
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#endif
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