475 lines
14 KiB
C
475 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* Vipin Kumar, STMicroelectronics, [email protected].
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*/
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#ifndef _DW_ETH_H
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#define _DW_ETH_H
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#include <asm/cache.h>
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#include <net.h>
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#if CONFIG_IS_ENABLED(DM_GPIO)
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#include <asm-generic/gpio.h>
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#endif
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#define CONFIG_TX_DESCR_NUM 16
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#define CONFIG_RX_DESCR_NUM 16
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#define CONFIG_ETH_BUFSIZE 2048
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#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
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#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
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#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
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struct eth_mac_regs {
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u32 conf; /* 0x00 */
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u32 framefilt; /* 0x04 */
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u32 hashtablehigh; /* 0x08 */
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u32 hashtablelow; /* 0x0c */
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u32 miiaddr; /* 0x10 */
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u32 miidata; /* 0x14 */
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u32 flowcontrol; /* 0x18 */
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u32 vlantag; /* 0x1c */
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u32 version; /* 0x20 */
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u8 reserved_1[20];
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u32 intreg; /* 0x38 */
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u32 intmask; /* 0x3c */
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u32 macaddr0hi; /* 0x40 */
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u32 macaddr0lo; /* 0x44 */
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};
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/* MAC configuration register definitions */
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#define FRAMEBURSTENABLE (1 << 21)
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#define MII_PORTSELECT (1 << 15)
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#define FES_100 (1 << 14)
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#define DISABLERXOWN (1 << 13)
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#define FULLDPLXMODE (1 << 11)
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#define RXENABLE (1 << 2)
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#define TXENABLE (1 << 3)
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/* MII address register definitions */
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#define MII_BUSY (1 << 0)
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#define MII_WRITE (1 << 1)
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#define MII_CLKRANGE_60_100M (0)
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#define MII_CLKRANGE_100_150M (0x4)
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#define MII_CLKRANGE_20_35M (0x8)
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#define MII_CLKRANGE_35_60M (0xC)
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#define MII_CLKRANGE_150_250M (0x10)
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#define MII_CLKRANGE_250_300M (0x14)
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#define MIIADDRSHIFT (11)
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#define MIIREGSHIFT (6)
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#define MII_REGMSK (0x1F << 6)
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#define MII_ADDRMSK (0x1F << 11)
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struct eth_dma_regs {
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u32 busmode; /* 0x00 */
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u32 txpolldemand; /* 0x04 */
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u32 rxpolldemand; /* 0x08 */
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u32 rxdesclistaddr; /* 0x0c */
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u32 txdesclistaddr; /* 0x10 */
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u32 status; /* 0x14 */
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u32 opmode; /* 0x18 */
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u32 intenable; /* 0x1c */
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u32 reserved1[2];
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u32 axibus; /* 0x28 */
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u32 reserved2[7];
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u32 currhosttxdesc; /* 0x48 */
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u32 currhostrxdesc; /* 0x4c */
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u32 currhosttxbuffaddr; /* 0x50 */
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u32 currhostrxbuffaddr; /* 0x54 */
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};
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#define DW_DMA_BASE_OFFSET (0x1000)
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/* DMA Burst length */
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#define GMAC_DEFAULT_DMA_PBL 8
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/* Bus mode register definitions */
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#define FIXEDBURST (1 << 16)
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#define PRIORXTX_41 (3 << 14)
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#define PRIORXTX_31 (2 << 14)
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#define PRIORXTX_21 (1 << 14)
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#define PRIORXTX_11 (0 << 14)
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#define DMA_PBL (GMAC_DEFAULT_DMA_PBL << 8)
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#define RXHIGHPRIO (1 << 1)
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#define DMAMAC_SRST (1 << 0)
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/* Poll demand definitions */
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#define POLL_DATA (0xFFFFFFFF)
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/* Operation mode definitions */
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#define STOREFORWARD (1 << 21)
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#define FLUSHTXFIFO (1 << 20)
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#define TXSTART (1 << 13)
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#define TXSECONDFRAME (1 << 2)
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#define RXSTART (1 << 1)
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/* Descriptior related definitions */
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#define MAC_MAX_FRAME_SZ (1600)
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struct dmamacdescr {
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u32 txrx_status;
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u32 dmamac_cntl;
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u32 dmamac_addr;
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u32 dmamac_next;
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} __aligned(ARCH_DMA_MINALIGN);
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/*
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* txrx_status definitions
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*/
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/* tx status bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define DESC_TXSTS_OWNBYDMA (1 << 31)
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#define DESC_TXSTS_TXINT (1 << 30)
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#define DESC_TXSTS_TXLAST (1 << 29)
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#define DESC_TXSTS_TXFIRST (1 << 28)
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#define DESC_TXSTS_TXCRCDIS (1 << 27)
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#define DESC_TXSTS_TXPADDIS (1 << 26)
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#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
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#define DESC_TXSTS_TXRINGEND (1 << 21)
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#define DESC_TXSTS_TXCHAIN (1 << 20)
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#define DESC_TXSTS_MSK (0x1FFFF << 0)
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#else
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#define DESC_TXSTS_OWNBYDMA (1 << 31)
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#define DESC_TXSTS_MSK (0x1FFFF << 0)
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#endif
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/* rx status bits definitions */
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#define DESC_RXSTS_OWNBYDMA (1 << 31)
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#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
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#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
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#define DESC_RXSTS_FRMLENSHFT (16)
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#define DESC_RXSTS_ERROR (1 << 15)
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#define DESC_RXSTS_RXTRUNCATED (1 << 14)
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#define DESC_RXSTS_SAFILTERFAIL (1 << 13)
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#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
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#define DESC_RXSTS_RXDAMAGED (1 << 11)
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#define DESC_RXSTS_RXVLANTAG (1 << 10)
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#define DESC_RXSTS_RXFIRST (1 << 9)
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#define DESC_RXSTS_RXLAST (1 << 8)
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#define DESC_RXSTS_RXIPC_GIANT (1 << 7)
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#define DESC_RXSTS_RXCOLLISION (1 << 6)
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#define DESC_RXSTS_RXFRAMEETHER (1 << 5)
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#define DESC_RXSTS_RXWATCHDOG (1 << 4)
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#define DESC_RXSTS_RXMIIERROR (1 << 3)
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#define DESC_RXSTS_RXDRIBBLING (1 << 2)
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#define DESC_RXSTS_RXCRC (1 << 1)
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/*
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* dmamac_cntl definitions
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*/
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/* tx control bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
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#define DESC_TXCTRL_SIZE1SHFT (0)
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#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
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#define DESC_TXCTRL_SIZE2SHFT (16)
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#else
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#define DESC_TXCTRL_TXINT (1 << 31)
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#define DESC_TXCTRL_TXLAST (1 << 30)
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#define DESC_TXCTRL_TXFIRST (1 << 29)
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#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
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#define DESC_TXCTRL_TXCRCDIS (1 << 26)
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#define DESC_TXCTRL_TXRINGEND (1 << 25)
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#define DESC_TXCTRL_TXCHAIN (1 << 24)
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#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
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#define DESC_TXCTRL_SIZE1SHFT (0)
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#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
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#define DESC_TXCTRL_SIZE2SHFT (11)
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#endif
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/* rx control bits definitions */
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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#define DESC_RXCTRL_RXINTDIS (1 << 31)
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#define DESC_RXCTRL_RXRINGEND (1 << 15)
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#define DESC_RXCTRL_RXCHAIN (1 << 14)
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#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
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#define DESC_RXCTRL_SIZE1SHFT (0)
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#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
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#define DESC_RXCTRL_SIZE2SHFT (16)
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#else
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#define DESC_RXCTRL_RXINTDIS (1 << 31)
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#define DESC_RXCTRL_RXRINGEND (1 << 25)
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#define DESC_RXCTRL_RXCHAIN (1 << 24)
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#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
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#define DESC_RXCTRL_SIZE1SHFT (0)
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#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
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#define DESC_RXCTRL_SIZE2SHFT (11)
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#endif
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struct dw_eth_dev {
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struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
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struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
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char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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u32 interface;
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u32 max_speed;
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u32 tx_currdescnum;
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u32 rx_currdescnum;
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struct eth_mac_regs *mac_regs_p;
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struct eth_dma_regs *dma_regs_p;
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#ifndef CONFIG_DM_ETH
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struct eth_device *dev;
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#endif
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#if CONFIG_IS_ENABLED(DM_GPIO)
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struct gpio_desc reset_gpio;
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#endif
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#ifdef CONFIG_CLK
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struct clk *clocks; /* clock list */
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int clock_count; /* number of clock in clock list */
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#endif
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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#ifdef CONFIG_DM_ETH
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int designware_eth_of_to_plat(struct udevice *dev);
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int designware_eth_probe(struct udevice *dev);
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extern const struct eth_ops designware_eth_ops;
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struct dw_eth_pdata {
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struct eth_pdata eth_pdata;
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u32 reset_delays[3];
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};
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int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
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int designware_eth_enable(struct dw_eth_dev *priv);
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int designware_eth_send(struct udevice *dev, void *packet, int length);
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int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
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int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
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int length);
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void designware_eth_stop(struct udevice *dev);
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int designware_eth_write_hwaddr(struct udevice *dev);
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#endif
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#if defined(CONFIG_AMLOGIC_ETH)
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struct eqos_mac_regs {
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uint32_t configuration; /* 0x000 */
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uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
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uint32_t q0_tx_flow_ctrl; /* 0x070 */
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uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
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uint32_t rx_flow_ctrl; /* 0x090 */
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uint32_t unused_094; /* 0x094 */
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uint32_t txq_prty_map0; /* 0x098 */
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uint32_t unused_09c; /* 0x09c */
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uint32_t rxq_ctrl0; /* 0x0a0 */
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uint32_t unused_0a4; /* 0x0a4 */
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uint32_t rxq_ctrl2; /* 0x0a8 */
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uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
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uint32_t us_tic_counter; /* 0x0dc */
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uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
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uint32_t hw_feature0; /* 0x11c */
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uint32_t hw_feature1; /* 0x120 */
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uint32_t hw_feature2; /* 0x124 */
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uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
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uint32_t mdio_address; /* 0x200 */
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uint32_t mdio_data; /* 0x204 */
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uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
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uint32_t address0_high; /* 0x300 */
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uint32_t address0_low; /* 0x304 */
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};
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//#define BIT(X) (1<<X)
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#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
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#define EQOS_MAC_CONFIGURATION_CST BIT(21)
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#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
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#define EQOS_MAC_CONFIGURATION_WD BIT(19)
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#define EQOS_MAC_CONFIGURATION_JD BIT(17)
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#define EQOS_MAC_CONFIGURATION_JE BIT(16)
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#define EQOS_MAC_CONFIGURATION_PS BIT(15)
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#define EQOS_MAC_CONFIGURATION_FES BIT(14)
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#define EQOS_MAC_CONFIGURATION_DM BIT(13)
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#define EQOS_MAC_CONFIGURATION_TE BIT(1)
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#define EQOS_MAC_CONFIGURATION_RE BIT(0)
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#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
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#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
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#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
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#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
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#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
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#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
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#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
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#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
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#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
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#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
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#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
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#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
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#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
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#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
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#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
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#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
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#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
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#define EQOS_MAC_MDIO_ADDRESS_CR_150_250 4
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#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
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#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
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#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
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#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
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#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
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#define EQOS_MAC_MDIO_ADDRESS_GB 1
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#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
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#define EQOS_MTL_REGS_BASE 0xd00
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struct eqos_mtl_regs {
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uint32_t txq0_operation_mode; /* 0xd00 */
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uint32_t unused_d04; /* 0xd04 */
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uint32_t txq0_debug; /* 0xd08 */
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uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
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uint32_t txq0_quantum_weight; /* 0xd18 */
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uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
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uint32_t rxq0_operation_mode; /* 0xd30 */
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uint32_t unused_d34; /* 0xd34 */
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uint32_t rxq0_debug; /* 0xd38 */
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//uint32_t rxq0_cntl; /* 0xd3C */
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};
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
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#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
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#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
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#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
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#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
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#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
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#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
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#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
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#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
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#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
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#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
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#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
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#define EQOS_DMA_REGS_BASE 0x1000
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struct eqos_dma_regs {
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uint32_t mode; /* 0x1000 */
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uint32_t sysbus_mode; /* 0x1004 */
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uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
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uint32_t ch0_control; /* 0x1100 */
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uint32_t ch0_tx_control; /* 0x1104 */
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uint32_t ch0_rx_control; /* 0x1108 */
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uint32_t unused_110c; /* 0x110c */
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uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
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uint32_t ch0_txdesc_list_address; /* 0x1114 */
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uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
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uint32_t ch0_rxdesc_list_address; /* 0x111c */
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uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
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uint32_t unused_1124; /* 0x1124 */
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uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
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uint32_t ch0_txdesc_ring_length; /* 0x112c */
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uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
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};
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#define EQOS_DMA_MODE_SWR BIT(0)
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#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
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#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
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#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
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#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
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#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
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#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
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#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
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#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
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#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
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#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
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#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
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#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
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#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
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#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
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#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
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#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
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/* Descriptors */
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#define EQOS_DESCRIPTOR_WORDS 4
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#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
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/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
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#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
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#define EQOS_DESCRIPTORS_TX 4
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#define EQOS_DESCRIPTORS_RX 4
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#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
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#define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
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EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
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#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
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#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
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#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
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struct eqos_desc {
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u32 des0;
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u32 des1;
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u32 des2;
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u32 des3;
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};
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#define EQOS_DESC3_OWN BIT(31)
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#define EQOS_DESC3_FD BIT(29)
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#define EQOS_DESC3_LD BIT(28)
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#define EQOS_DESC3_BUF1V BIT(24)
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struct eqos_eth_dev {
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struct udevice *dev;
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struct eqos_mac_regs *mac_regs_p;
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struct eqos_mtl_regs *mtl_regs_p;
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struct eqos_dma_regs *dma_regs_p;
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struct mii_dev *bus;
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struct phy_device *phydev;
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u32 interface;
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void *descs;
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struct eqos_desc *tx_descs;
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struct eqos_desc *rx_descs;
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int tx_desc_idx, rx_desc_idx;
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void *tx_dma_buf;
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void *rx_dma_buf;
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void *rx_pkt;
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};
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#endif
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#endif
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